[binutils, Arm] Add support for shift instructions in MVE
This patch adds the following instructions which are part of Armv8.1-M MVE: ASRL (imm) ASRL (reg) LSLL (imm) LSLL (reg) LSRL SQRSHRL SRQSHR SQSHLL SQSHL SRSHRL SRSHR UQRSHLL UQRSHL UQSHLL UQSHL URSHLL URSHL *** gas/ChangeLog *** 2019-05-21 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (operand_parse_code): New entries for OP_RRnpcsp_I32 (register or integer operands). (do_mve_scalar_shift): New. (insns): New instructions for asrl, lsll, lsrl, sqrshrl, sqrshr, sqshl sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll, uqshl, urshrl and urshr. * testsuite/gas/arm/mve-shift.d: New. * testsuite/gas/arm/mve-shift.s: New. * testsuite/gas/arm/mve-shift-bad.d: New. * testsuite/gas/arm/mve-shift-bad.s: New. * testsuite/gas/arm/mve-shift-bad.l: New. *** opcodes/ChangeLog *** 2019-05-21 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (emun mve_instructions): Updated for new instructions. (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl, sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll, uqshl, urshrl and urshr. (is_mve_okay_in_it): Add new instructions to TRUE list. (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15. (print_insn_mve): Updated to accept new %j, %<bitfield>m and %<bitfield>n patterns.
This commit is contained in:
parent
cd4797ee05
commit
23d00a419f
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@ -1,3 +1,16 @@
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2019-05-21 Sudakshina Das <sudi.das@arm.com>
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* config/tc-arm.c (operand_parse_code): New entries for
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OP_RRnpcsp_I32 (register or integer operands).
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(do_mve_scalar_shift): New.
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(insns): New instructions for asrl, lsll, lsrl, sqrshrl, sqrshr, sqshl
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sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll, uqshl, urshrl and urshr.
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* testsuite/gas/arm/mve-shift.d: New.
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* testsuite/gas/arm/mve-shift.s: New.
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* testsuite/gas/arm/mve-shift-bad.d: New.
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* testsuite/gas/arm/mve-shift-bad.s: New.
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* testsuite/gas/arm/mve-shift-bad.l: New.
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2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
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* testsuite/gas/mips/r6-branch-constraints.s: Rename to ...
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@ -7559,6 +7559,9 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
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I0: po_imm_or_fail (0, 0, FALSE); break;
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case OP_RRnpcsp_I32: po_reg_or_goto (REG_TYPE_RN, I32); break;
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I32: po_imm_or_fail (1, 32, FALSE); break;
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case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
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IF:
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if (!is_immediate_prefix (*str))
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@ -7818,6 +7821,7 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
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case OP_oRRnpcsp:
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case OP_RRnpcsp:
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case OP_RRnpcsp_I32:
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if (inst.operands[i].isreg)
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{
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if (inst.operands[i].reg == REG_PC)
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@ -14123,6 +14127,37 @@ v8_1_loop_reloc (int is_le)
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}
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}
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/* For shifts in MVE. */
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static void
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do_mve_scalar_shift (void)
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{
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if (!inst.operands[2].present)
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{
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inst.operands[2] = inst.operands[1];
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inst.operands[1].reg = 0xf;
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}
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inst.instruction |= inst.operands[0].reg << 16;
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inst.instruction |= inst.operands[1].reg << 8;
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if (inst.operands[2].isreg)
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{
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/* Assuming Rm is already checked not to be 11x1. */
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constraint (inst.operands[2].reg == inst.operands[0].reg, BAD_OVERLAP);
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constraint (inst.operands[2].reg == inst.operands[1].reg, BAD_OVERLAP);
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inst.instruction |= inst.operands[2].reg << 12;
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}
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else
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{
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/* Assuming imm is already checked as [1,32]. */
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unsigned int value = inst.operands[2].imm;
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inst.instruction |= (value & 0x1c) << 10;
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inst.instruction |= (value & 0x03) << 6;
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/* Change last 4 bits from 0xd to 0xf. */
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inst.instruction |= 0x2;
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}
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}
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/* MVE instruction encoder helpers. */
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#define M_MNEM_vabav 0xee800f01
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#define M_MNEM_vmladav 0xeef00e00
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@ -25137,6 +25172,21 @@ static const struct asm_opcode insns[] =
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & mve_ext
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ToC("lsll", ea50010d, 3, (RRe, RRo, RRnpcsp_I32), mve_scalar_shift),
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ToC("lsrl", ea50011f, 3, (RRe, RRo, I32), mve_scalar_shift),
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ToC("asrl", ea50012d, 3, (RRe, RRo, RRnpcsp_I32), mve_scalar_shift),
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ToC("uqrshll", ea51010d, 3, (RRe, RRo, RRnpcsp), mve_scalar_shift),
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ToC("sqrshrl", ea51012d, 3, (RRe, RRo, RRnpcsp), mve_scalar_shift),
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ToC("uqshll", ea51010f, 3, (RRe, RRo, I32), mve_scalar_shift),
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ToC("urshrl", ea51011f, 3, (RRe, RRo, I32), mve_scalar_shift),
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ToC("srshrl", ea51012f, 3, (RRe, RRo, I32), mve_scalar_shift),
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ToC("sqshll", ea51013f, 3, (RRe, RRo, I32), mve_scalar_shift),
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ToC("uqrshl", ea500f0d, 2, (RRnpcsp, RRnpcsp), mve_scalar_shift),
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ToC("sqrshr", ea500f2d, 2, (RRnpcsp, RRnpcsp), mve_scalar_shift),
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ToC("uqshl", ea500f0f, 2, (RRnpcsp, I32), mve_scalar_shift),
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ToC("urshr", ea500f1f, 2, (RRnpcsp, I32), mve_scalar_shift),
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ToC("srshr", ea500f2f, 2, (RRnpcsp, I32), mve_scalar_shift),
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ToC("sqshl", ea500f3f, 2, (RRnpcsp, I32), mve_scalar_shift),
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ToC("vpt", ee410f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
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ToC("vptt", ee018f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
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@ -0,0 +1,4 @@
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#name: Invalid MVE shift instructions
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#source: mve-shift-bad.s
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#as: -march=armv8.1-m.main+mve
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#error_output: mve-shift-bad.l
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@ -0,0 +1,12 @@
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.*: Assembler messages:
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.*: immediate value out of range -- `asrl r2,r3,#0'
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.*: immediate value out of range -- `asrl r2,r3,#33'
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.*: Error: Odd register not allowed here -- `asrl r1,r3,r5'
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.*: Error: Even register not allowed here -- `lsll r2,r4,#5'
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.*: Error: r15 not allowed here -- `lsll r2,r15,r5'
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.*: Warning: instruction is UNPREDICTABLE with SP operand
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.*: Error: registers may not be the same -- `sqrshrl r2,r3,r3'
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.*: Error: registers may not be the same -- `sqrshr r2,r2'
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.*: Error: registers may not be the same -- `uqrshll r2,r3,r2'
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.*: Error: thumb conditional instruction should be in IT block -- `uqshlgt r2,#32'
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.*: Error: constant expression required -- `urshrlle r2,r3,r5'
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@ -0,0 +1,15 @@
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.syntax unified
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.text
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foo:
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asrl r2, r3, #0
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asrl r2, r3, #33
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asrl r1, r3, r5
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lsll r2, r4, #5
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lsll r2, r15, r5
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lsrl r2, r13, #5
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sqrshrl r2, r3, r3
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sqrshr r2, r2
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uqrshll r2, r3, r2
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uqshlgt r2, #32
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urshrlle r2, r3, r5
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@ -0,0 +1,27 @@
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#name: Valid MVE shift instructions
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#source: mve-shift.s
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#as: -march=armv8.1-m.main+mve
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#objdump: -dr --prefix-addresses --show-raw-insn -marmv8.1-m.main
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.*: +file format .*arm.*
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Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> ea52 136f asrl r2, r3, #5
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0[0-9a-f]+ <[^>]+> ea52 532d asrl r2, r3, r5
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0[0-9a-f]+ <[^>]+> ea52 134f lsll r2, r3, #5
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0[0-9a-f]+ <[^>]+> ea52 530d lsll r2, r3, r5
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0[0-9a-f]+ <[^>]+> ea52 135f lsrl r2, r3, #5
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0[0-9a-f]+ <[^>]+> ea53 532d sqrshrl r2, r3, r5
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0[0-9a-f]+ <[^>]+> ea52 5f2d sqrshr r2, r5
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0[0-9a-f]+ <[^>]+> ea53 137f sqshll r2, r3, #5
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0[0-9a-f]+ <[^>]+> ea52 1f7f sqshl r2, #5
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0[0-9a-f]+ <[^>]+> ea53 73ef srshrl r2, r3, #31
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0[0-9a-f]+ <[^>]+> ea52 7fef srshr r2, #31
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0[0-9a-f]+ <[^>]+> ea53 530d uqrshll r2, r3, r5
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0[0-9a-f]+ <[^>]+> ea52 5f0d uqrshl r2, r5
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0[0-9a-f]+ <[^>]+> ea53 73cf uqshll r2, r3, #31
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0[0-9a-f]+ <[^>]+> bfce itee gt
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0[0-9a-f]+ <[^>]+> ea52 0f0f uqshlgt r2, #32
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0[0-9a-f]+ <[^>]+> ea53 031f urshrlle r2, r3, #32
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0[0-9a-f]+ <[^>]+> ea52 0f1f urshrle r2, #32
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#...
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@ -0,0 +1,21 @@
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.syntax unified
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.text
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foo:
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asrl r2, r3, #5
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asrl r2, r3, r5
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lsll r2, r3, #5
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lsll r2, r3, r5
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lsrl r2, r3, #5
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sqrshrl r2, r3, r5
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sqrshr r2, r5
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sqshll r2, r3, #5
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sqshl r2, #5
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srshrl r2, r3, #31
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srshr r2, #31
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uqrshll r2, r3, r5
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uqrshl r2, r5
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uqshll r2, r3, #31
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itee gt
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uqshlgt r2, #32
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urshrlle r2, r3, #32
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urshrle r2, #32
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@ -1,3 +1,14 @@
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2019-05-21 Sudakshina Das <sudi.das@arm.com>
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* arm-dis.c (emun mve_instructions): Updated for new instructions.
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(mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
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sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
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uqshl, urshrl and urshr.
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(is_mve_okay_in_it): Add new instructions to TRUE list.
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(is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
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(print_insn_mve): Updated to accept new %j,
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%<bitfield>m and %<bitfield>n patterns.
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2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
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* mips-opc.c (mips_builtin_opcodes): Change source register
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@ -264,6 +264,23 @@ enum mve_instructions
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MVE_VREV16,
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MVE_VREV32,
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MVE_VREV64,
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MVE_LSLL,
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MVE_LSLLI,
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MVE_LSRL,
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MVE_ASRL,
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MVE_ASRLI,
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MVE_SQRSHRL,
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MVE_SQRSHR,
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MVE_UQRSHL,
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MVE_UQRSHLL,
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MVE_UQSHL,
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MVE_UQSHLL,
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MVE_URSHRL,
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MVE_URSHR,
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MVE_SRSHRL,
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MVE_SRSHR,
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MVE_SQSHLL,
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MVE_SQSHL,
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MVE_NONE
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};
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@ -2026,6 +2043,7 @@ static const struct opcode32 neon_opcodes[] =
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%d print addr mode of MVE vldr[bhw] and vstr[bhw]
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%u print 'U' (unsigned) or 'S' for various mve instructions
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%i print MVE predicate(s) for vpt and vpst
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%j print a 5-bit immediate from hw2[14:12,7:6]
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%m print rounding mode for vcvt and vrint
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%n print vector comparison code for predicated instruction
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%s print size for various vcvt instructions
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@ -2046,6 +2064,8 @@ static const struct opcode32 neon_opcodes[] =
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%<bitfield>F print as a MVE S register
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%<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
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UNPREDICTABLE
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%<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
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%<bitfield>s print size for vector predicate & non VMOV instructions
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%<bitfield>I print carry flag or not
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%<bitfield>i print immediate for vstr/vldr reg +/- imm
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@ -3295,6 +3315,91 @@ static const struct mopcode32 mve_opcodes[] =
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0xee011f40, 0xff811f70,
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"vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_ASRLI,
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0xea50012f, 0xfff1813f,
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"asrl%c\t%17-19l, %9-11h, %j"},
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_ASRL,
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0xea50012d, 0xfff101ff,
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"asrl%c\t%17-19l, %9-11h, %12-15S"},
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_LSLLI,
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0xea50010f, 0xfff1813f,
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"lsll%c\t%17-19l, %9-11h, %j"},
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_LSLL,
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0xea50010d, 0xfff101ff,
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"lsll%c\t%17-19l, %9-11h, %12-15S"},
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_LSRL,
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0xea50011f, 0xfff1813f,
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"lsrl%c\t%17-19l, %9-11h, %j"},
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_SQRSHRL,
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0xea51012d, 0xfff101ff,
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"sqrshrl%c\t%17-19l, %9-11h, %12-15S"},
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_SQRSHR,
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0xea500f2d, 0xfff00fff,
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"sqrshr%c\t%16-19S, %12-15S"},
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_SQSHLL,
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0xea51013f, 0xfff1813f,
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"sqshll%c\t%17-19l, %9-11h, %j"},
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_SQSHL,
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0xea500f3f, 0xfff08f3f,
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"sqshl%c\t%16-19S, %j"},
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_SRSHRL,
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0xea51012f, 0xfff1813f,
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"srshrl%c\t%17-19l, %9-11h, %j"},
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_SRSHR,
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0xea500f2f, 0xfff08f3f,
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"srshr%c\t%16-19S, %j"},
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_UQRSHLL,
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0xea51010d, 0xfff101ff,
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"uqrshll%c\t%17-19l, %9-11h, %12-15S"},
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_UQRSHL,
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0xea500f0d, 0xfff00fff,
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"uqrshl%c\t%16-19S, %12-15S"},
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_UQSHLL,
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0xea51010f, 0xfff1813f,
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"uqshll%c\t%17-19l, %9-11h, %j"},
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_UQSHL,
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0xea500f0f, 0xfff08f3f,
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"uqshl%c\t%16-19S, %j"},
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_URSHRL,
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0xea51011f, 0xfff1813f,
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"urshrl%c\t%17-19l, %9-11h, %j"},
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{ARM_FEATURE_COPROC (FPU_MVE),
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MVE_URSHR,
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0xea500f1f, 0xfff08f3f,
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"urshr%c\t%16-19S, %j"},
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{ARM_FEATURE_CORE_LOW (0),
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MVE_NONE,
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0x00000000, 0x00000000, 0}
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@ -5169,6 +5274,23 @@ is_mve_okay_in_it (enum mve_instructions matched_insn)
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case MVE_VMOV2_VEC_LANE_TO_GP:
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case MVE_VMOV2_GP_TO_VEC_LANE:
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case MVE_VMOV_VEC_LANE_TO_GP:
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case MVE_LSLL:
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case MVE_LSLLI:
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case MVE_LSRL:
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case MVE_ASRL:
|
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case MVE_ASRLI:
|
||||
case MVE_SQRSHRL:
|
||||
case MVE_SQRSHR:
|
||||
case MVE_UQRSHL:
|
||||
case MVE_UQRSHLL:
|
||||
case MVE_UQSHL:
|
||||
case MVE_UQSHLL:
|
||||
case MVE_URSHRL:
|
||||
case MVE_URSHR:
|
||||
case MVE_SRSHRL:
|
||||
case MVE_SRSHR:
|
||||
case MVE_SQSHLL:
|
||||
case MVE_SQSHL:
|
||||
return TRUE;
|
||||
default:
|
||||
return FALSE;
|
||||
|
@ -5515,6 +5637,22 @@ is_mve_encoding_conflict (unsigned long given,
|
|||
else
|
||||
return FALSE;
|
||||
|
||||
case MVE_ASRLI:
|
||||
case MVE_ASRL:
|
||||
case MVE_LSLLI:
|
||||
case MVE_LSLL:
|
||||
case MVE_LSRL:
|
||||
case MVE_SQRSHRL:
|
||||
case MVE_SQSHLL:
|
||||
case MVE_SRSHRL:
|
||||
case MVE_UQRSHLL:
|
||||
case MVE_UQSHLL:
|
||||
case MVE_URSHRL:
|
||||
if (arm_decode_field (given, 9, 11) == 0x7)
|
||||
return TRUE;
|
||||
else
|
||||
return FALSE;
|
||||
|
||||
default:
|
||||
case MVE_VADD_FP_T1:
|
||||
case MVE_VADD_FP_T2:
|
||||
|
@ -6490,6 +6628,34 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
|
|||
return FALSE;
|
||||
}
|
||||
|
||||
case MVE_LSLL:
|
||||
case MVE_LSLLI:
|
||||
case MVE_LSRL:
|
||||
case MVE_ASRL:
|
||||
case MVE_ASRLI:
|
||||
case MVE_UQSHLL:
|
||||
case MVE_UQRSHLL:
|
||||
case MVE_URSHRL:
|
||||
case MVE_SRSHRL:
|
||||
case MVE_SQSHLL:
|
||||
case MVE_SQRSHRL:
|
||||
{
|
||||
unsigned long gpr = arm_decode_field (given, 9, 11);
|
||||
gpr = ((gpr << 1) | 1);
|
||||
if (gpr == 0xd)
|
||||
{
|
||||
*unpredictable_code = UNPRED_R13;
|
||||
return TRUE;
|
||||
}
|
||||
else if (gpr == 0xf)
|
||||
{
|
||||
*unpredictable_code = UNPRED_R15;
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
default:
|
||||
return FALSE;
|
||||
}
|
||||
|
@ -8983,6 +9149,15 @@ print_insn_mve (struct disassemble_info *info, long given)
|
|||
}
|
||||
break;
|
||||
|
||||
case 'j':
|
||||
{
|
||||
unsigned int imm5 = 0;
|
||||
imm5 |= arm_decode_field (given, 6, 7);
|
||||
imm5 |= (arm_decode_field (given, 12, 14) << 2);
|
||||
func (stream, "#%u", (imm5 == 0) ? 32 : imm5);
|
||||
}
|
||||
break;
|
||||
|
||||
case 'n':
|
||||
print_vec_condition (info, given, insn->mve_op);
|
||||
break;
|
||||
|
@ -9088,6 +9263,14 @@ print_insn_mve (struct disassemble_info *info, long given)
|
|||
else
|
||||
func (stream, "%s", arm_regnames[value]);
|
||||
break;
|
||||
|
||||
case 'S':
|
||||
if (value == 13 || value == 15)
|
||||
is_unpredictable = TRUE;
|
||||
else
|
||||
func (stream, "%s", arm_regnames[value]);
|
||||
break;
|
||||
|
||||
case 's':
|
||||
print_mve_size (info,
|
||||
value,
|
||||
|
|
Loading…
Reference in New Issue