OpenE2K
/
binutils-gdb
12
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Removes support in the ARM assembler for the unsigned variants of the VQ(R)DMLAH and VQ(R)DMLASH MVE instructions. 

Previously GAS would accept .u32, .u16 and .u8 suffixes to the VQ(R)DMLAH and VQ(R)DMLASH
instructions, however the Armv8.1-M Mainline specification states that these functions only
have signed variations (.s32, .s16 and .s8 suffixes).
This is documented here:
https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf?_ga=2.143079093.1892401233.1563295591-999473562.1560847439#page=1183

gas	* config/tc-arm.c (do_mve_vqdmlah): Use N_S_32 macro.
	(do_neon_qrdmlah): Use N_S_32 macro.
	* testsuite/gas/arm/mve-vqdmlah-bad.d: New test.
	* testsuite/gas/arm/mve-vqdmlah-bad.l: New test.
	* testsuite/gas/arm/mve-vqdmlah-bad.s: New test.
	* testsuite/gas/arm/mve-vqdmlah.d: Remove unsigned instruction tests.
	* testsuite/gas/arm/mve-vqdmlah.s: Remove unsigned instruction tests.
	* testsuite/gas/arm/mve-vqdmlash-bad.d: New test.
	* testsuite/gas/arm/mve-vqdmlash-bad.l: New test.
	* testsuite/gas/arm/mve-vqdmlash-bad.s: New test.
	* testsuite/gas/arm/mve-vqdmlash.d: Remove unsigned instruction tests.
	* testsuite/gas/arm/mve-vqdmlash.s: Remove unsigned instruction tests.

opcodes	* arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
	instructions.
This commit is contained in:
Barnaby Wilks 2019-08-05 12:43:38 +01:00 committed by Nick Clifton
parent a80cf5d88e
commit 23d188c74e
14 changed files with 64 additions and 2716 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
gas/ChangeLog
View File

@ -1,3 +1,18 @@
2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
* config/tc-arm.c (do_mve_vqdmlah): Use N_S_32 macro.
(do_neon_qrdmlah): Use N_S_32 macro.
* testsuite/gas/arm/mve-vqdmlah-bad.d: New test.
* testsuite/gas/arm/mve-vqdmlah-bad.l: New test.
* testsuite/gas/arm/mve-vqdmlah-bad.s: New test.
* testsuite/gas/arm/mve-vqdmlah.d: Remove unsigned instruction tests.
* testsuite/gas/arm/mve-vqdmlah.s: Remove unsigned instruction tests.
* testsuite/gas/arm/mve-vqdmlash-bad.d: New test.
* testsuite/gas/arm/mve-vqdmlash-bad.l: New test.
* testsuite/gas/arm/mve-vqdmlash-bad.s: New test.
* testsuite/gas/arm/mve-vqdmlash.d: Remove unsigned instruction tests.
* testsuite/gas/arm/mve-vqdmlash.s: Remove unsigned instruction tests.
2019-07-30 Mel Chen <mel.chen@sifive.com>
* testsuite/gas/riscv/alias-csr.s: Add testcase for CSR-access

4
gas/config/tc-arm.c
View File

@ -17900,7 +17900,7 @@ do_mve_vqdmlah (void)
{
enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
struct neon_type_el et
= neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
= neon_check_type (3, rs, N_EQK, N_EQK, N_S_32 | N_KEY);
if (inst.cond > COND_ALWAYS)
inst.pred_insn_type = INSIDE_VPT_INSN;
@ -18190,7 +18190,7 @@ do_neon_qrdmlah (void)
{
enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
struct neon_type_el et
= neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
= neon_check_type (3, rs, N_EQK, N_EQK, N_S_32 | N_KEY);
NEON_ENCODE (INTEGER, inst);
mve_encode_qqr (et.size, et.type == NT_unsigned, 0);

3
gas/testsuite/gas/arm/mve-vqdmlah-bad.d Normal file
View File

@ -0,0 +1,3 @@
#name: bad MVE VQDMLAH and VQRDMLAH instructions
#as: -march=armv8.1-m.main+mve.fp
#error_output: mve-vqdmlah-bad.l

7
gas/testsuite/gas/arm/mve-vqdmlah-bad.l Normal file
View File

@ -0,0 +1,7 @@
[^:]*: Assembler messages:
[^:]*:4: Error: bad type in SIMD instruction -- `vqdmlah.u8 q1,q2,r0'
[^:]*:4: Error: bad type in SIMD instruction -- `vqrdmlah.u8 q3,q4,r5'
[^:]*:4: Error: bad type in SIMD instruction -- `vqdmlah.u16 q1,q2,r0'
[^:]*:4: Error: bad type in SIMD instruction -- `vqrdmlah.u16 q3,q4,r5'
[^:]*:4: Error: bad type in SIMD instruction -- `vqdmlah.u32 q1,q2,r0'
[^:]*:4: Error: bad type in SIMD instruction -- `vqrdmlah.u32 q3,q4,r5'

4
gas/testsuite/gas/arm/mve-vqdmlah-bad.s Normal file
View File

@ -0,0 +1,4 @@
.irp data, u8, u16, u32
vqdmlah.\data q1, q2, r0
vqrdmlah.\data q3, q4, r5
.endr

1354
gas/testsuite/gas/arm/mve-vqdmlah.d
View File

File diff suppressed because it is too large Load Diff

6
gas/testsuite/gas/arm/mve-vqdmlah.s
View File

@ -1,6 +1,6 @@
.syntax unified
.thumb
.irp data, s8, u8, s16, u16, s32, u32
.irp data, s8, s16, s32
.irp op1, q0, q1, q2, q4, q7
.irp op2, q0, q1, q2, q4, q7
.irp op3, r0, r1, r2, r4, r7, r8, r10, r12, r14
@ -13,6 +13,6 @@ vqrdmlah.\data \op1, \op2, \op3
vpstete
vqdmlaht.s8 q0, q1, r2
vqdmlahe.u16 q7, q7, r14
vqdmlahe.s16 q7, q7, r14
vqrdmlaht.s32 q0, q0, r0
vqrdmlahe.u8 q7, q7, r14
vqrdmlahe.s8 q7, q7, r14

3
gas/testsuite/gas/arm/mve-vqdmlash-bad.d Normal file
View File

@ -0,0 +1,3 @@
#name: bad VQDMLASH and VQRDMLASH instructions
#as: -march=armv8.1-m.main+mve.fp
#error_output: mve-vqdmlash-bad.l

7
gas/testsuite/gas/arm/mve-vqdmlash-bad.l Normal file
View File

@ -0,0 +1,7 @@
[^:]*: Assembler messages:
[^:]*:4: Error: bad type in SIMD instruction -- `vqdmlash.u8 q0,q2,r0'
[^:]*:4: Error: bad type in SIMD instruction -- `vqrdmlash.u8 q1,q3,r1'
[^:]*:4: Error: bad type in SIMD instruction -- `vqdmlash.u16 q0,q2,r0'
[^:]*:4: Error: bad type in SIMD instruction -- `vqrdmlash.u16 q1,q3,r1'
[^:]*:4: Error: bad type in SIMD instruction -- `vqdmlash.u32 q0,q2,r0'
[^:]*:4: Error: bad type in SIMD instruction -- `vqrdmlash.u32 q1,q3,r1'

4
gas/testsuite/gas/arm/mve-vqdmlash-bad.s Normal file
View File

@ -0,0 +1,4 @@
.irp data, u8, u16, u32
vqdmlash.\data q0, q2, r0
vqrdmlash.\data q1, q3, r1
.endr

1354
gas/testsuite/gas/arm/mve-vqdmlash.d
View File

File diff suppressed because it is too large Load Diff

6
gas/testsuite/gas/arm/mve-vqdmlash.s
View File

@ -1,7 +1,7 @@
.syntax unified
.thumb
.irp data, s8, u8, s16, u16, s32, u32
.irp data, s8, s16, s32
.irp op1, q0, q1, q2, q4, q7
.irp op2, q0, q1, q2, q4, q7
.irp op3, r0, r1, r2, r4, r7, r8, r10, r12, r14
@ -13,6 +13,6 @@ vqrdmlash.\data \op1, \op2, \op3
.endr
vpstete
vqdmlasht.s8 q0, q1, r2
vqdmlashe.u16 q7, q7, r14
vqdmlashe.s16 q7, q7, r14
vqrdmlasht.s32 q0, q0, r0
vqrdmlashe.u8 q7, q7, r14
vqrdmlashe.s8 q7, q7, r14

5
opcodes/ChangeLog
View File

@ -1,3 +1,8 @@
2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
* arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
instructions.
2019-07-30 Mel Chen <mel.chen@sifive.com>
* riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,

8
opcodes/arm-dis.c
View File

@ -3019,25 +3019,25 @@ static const struct mopcode32 mve_opcodes[] =
/* Vector VQDMLAH. */
{ARM_FEATURE_COPROC (FPU_MVE),
MVE_VQDMLAH,
0xee000e60, 0xef811f70,
0xee000e60, 0xff811f70,
"vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VQRDMLAH. */
{ARM_FEATURE_COPROC (FPU_MVE),
MVE_VQRDMLAH,
0xee000e40, 0xef811f70,
0xee000e40, 0xff811f70,
"vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VQDMLASH. */
{ARM_FEATURE_COPROC (FPU_MVE),
MVE_VQDMLASH,
0xee001e60, 0xef811f70,
0xee001e60, 0xff811f70,
"vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VQRDMLASH. */
{ARM_FEATURE_COPROC (FPU_MVE),
MVE_VQRDMLASH,
0xee001e40, 0xef811f70,
0xee001e40, 0xff811f70,
"vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
/* Vector VQDMLSDH. */