Move aarch64_relocate_instruction to arch/aarch64-insn.c
This patch moves aarch64_relocate_instruction and visitor class to arch/aarch64-insn.c, so that both GDB and GDBserver can use it. gdb: 2015-10-12 Yao Qi <yao.qi@linaro.org> * arch/aarch64-insn.c (aarch64_decode_ldr_literal): Moved from gdbserver/linux-aarch64-low.c. (aarch64_relocate_instruction): Likewise. * arch/aarch64-insn.h (aarch64_decode_ldr_literal): Declare. (struct aarch64_insn_data): Moved from gdbserver/linux-aarch64-low.c. (struct aarch64_insn_visitor): Likewise. (aarch64_relocate_instruction): Declare. gdb/gdbserver: 2015-10-12 Yao Qi <yao.qi@linaro.org> * linux-aarch64-low.c (extract_signed_bitfield): Remove. (aarch64_decode_ldr_literal): Move to gdb/arch/aarch64-insn.c. (aarch64_relocate_instruction): Likewise. (struct aarch64_insn_data): Move to gdb/arch/aarch64-insn.h. (struct aarch64_insn_visitor): Likewise.
This commit is contained in:
Yao Qi
parent
0badd99faf
commit
246994ce35
@ -1,3 +1,14 @@
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2015-10-12 Yao Qi <yao.qi@linaro.org>
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* arch/aarch64-insn.c (aarch64_decode_ldr_literal): Moved from
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gdbserver/linux-aarch64-low.c.
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(aarch64_relocate_instruction): Likewise.
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* arch/aarch64-insn.h (aarch64_decode_ldr_literal): Declare.
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(struct aarch64_insn_data): Moved from
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gdbserver/linux-aarch64-low.c.
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(struct aarch64_insn_visitor): Likewise.
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(aarch64_relocate_instruction): Declare.
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2015-10-12 Pierre-Marie de Rodat <derodat@adacore.com>
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* eval.c (evaluate_subexp_standard) <STRUCTOP_STRUCT>: If
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@ -235,3 +235,96 @@ aarch64_decode_tb (CORE_ADDR addr, uint32_t insn, int *is_tbnz,
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}
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return 0;
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}
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/* Decode an opcode if it represents an LDR or LDRSW instruction taking a
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literal offset from the current PC.
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ADDR specifies the address of the opcode.
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INSN specifies the opcode to test.
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IS_W is set if the instruction is LDRSW.
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IS64 receives size field from the decoded instruction.
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RT receives the 'rt' field from the decoded instruction.
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OFFSET receives the 'imm' field from the decoded instruction.
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Return 1 if the opcodes matches and is decoded, otherwise 0. */
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int
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aarch64_decode_ldr_literal (CORE_ADDR addr, uint32_t insn, int *is_w,
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int *is64, unsigned *rt, int32_t *offset)
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{
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/* LDR 0T01 1000 iiii iiii iiii iiii iiir rrrr */
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/* LDRSW 1001 1000 iiii iiii iiii iiii iiir rrrr */
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if ((insn & 0x3f000000) == 0x18000000)
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{
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*is_w = (insn >> 31) & 0x1;
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if (*is_w)
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{
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/* LDRSW always takes a 64-bit destination registers. */
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*is64 = 1;
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}
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else
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*is64 = (insn >> 30) & 0x1;
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*rt = (insn >> 0) & 0x1f;
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*offset = extract_signed_bitfield (insn, 19, 5) << 2;
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if (aarch64_debug)
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debug_printf ("decode: %s 0x%x %s %s%u, #?\n",
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core_addr_to_string_nz (addr), insn,
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*is_w ? "ldrsw" : "ldr",
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*is64 ? "x" : "w", *rt);
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return 1;
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}
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return 0;
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}
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/* Visit an instruction INSN by VISITOR with all needed information in DATA.
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PC relative instructions need to be handled specifically:
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- B/BL
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- B.COND
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- CBZ/CBNZ
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- TBZ/TBNZ
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- ADR/ADRP
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- LDR/LDRSW (literal) */
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void
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aarch64_relocate_instruction (uint32_t insn,
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const struct aarch64_insn_visitor *visitor,
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struct aarch64_insn_data *data)
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{
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int is_bl;
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int is64;
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int is_sw;
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int is_cbnz;
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int is_tbnz;
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int is_adrp;
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unsigned rn;
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unsigned rt;
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unsigned rd;
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unsigned cond;
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unsigned bit;
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int32_t offset;
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if (aarch64_decode_b (data->insn_addr, insn, &is_bl, &offset))
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visitor->b (is_bl, offset, data);
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else if (aarch64_decode_bcond (data->insn_addr, insn, &cond, &offset))
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visitor->b_cond (cond, offset, data);
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else if (aarch64_decode_cb (data->insn_addr, insn, &is64, &is_cbnz, &rn,
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&offset))
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visitor->cb (offset, is_cbnz, rn, is64, data);
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else if (aarch64_decode_tb (data->insn_addr, insn, &is_tbnz, &bit, &rt,
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&offset))
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visitor->tb (offset, is_tbnz, rt, bit, data);
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else if (aarch64_decode_adr (data->insn_addr, insn, &is_adrp, &rd, &offset))
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visitor->adr (offset, rd, is_adrp, data);
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else if (aarch64_decode_ldr_literal (data->insn_addr, insn, &is_sw, &is64,
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&rt, &offset))
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visitor->ldr_literal (offset, is_sw, rt, is64, data);
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else
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visitor->others (insn, data);
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}
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@ -36,4 +36,54 @@ int aarch64_decode_cb (CORE_ADDR addr, uint32_t insn, int *is64,
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int aarch64_decode_tb (CORE_ADDR addr, uint32_t insn, int *is_tbnz,
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unsigned *bit, unsigned *rt, int32_t *imm);
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int aarch64_decode_ldr_literal (CORE_ADDR addr, uint32_t insn, int *is_w,
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int *is64, unsigned *rt, int32_t *offset);
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/* Data passed to each method of aarch64_insn_visitor. */
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struct aarch64_insn_data
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{
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/* The instruction address. */
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CORE_ADDR insn_addr;
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};
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/* Visit different instructions by different methods. */
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struct aarch64_insn_visitor
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{
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/* Visit instruction B/BL OFFSET. */
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void (*b) (const int is_bl, const int32_t offset,
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struct aarch64_insn_data *data);
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/* Visit instruction B.COND OFFSET. */
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void (*b_cond) (const unsigned cond, const int32_t offset,
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struct aarch64_insn_data *data);
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/* Visit instruction CBZ/CBNZ Rn, OFFSET. */
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void (*cb) (const int32_t offset, const int is_cbnz,
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const unsigned rn, int is64,
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struct aarch64_insn_data *data);
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/* Visit instruction TBZ/TBNZ Rt, #BIT, OFFSET. */
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void (*tb) (const int32_t offset, int is_tbnz,
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const unsigned rt, unsigned bit,
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struct aarch64_insn_data *data);
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/* Visit instruction ADR/ADRP Rd, OFFSET. */
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void (*adr) (const int32_t offset, const unsigned rd,
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const int is_adrp, struct aarch64_insn_data *data);
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/* Visit instruction LDR/LDRSW Rt, OFFSET. */
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void (*ldr_literal) (const int32_t offset, const int is_sw,
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const unsigned rt, const int is64,
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struct aarch64_insn_data *data);
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/* Visit instruction INSN of other kinds. */
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void (*others) (const uint32_t insn, struct aarch64_insn_data *data);
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};
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void aarch64_relocate_instruction (uint32_t insn,
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const struct aarch64_insn_visitor *visitor,
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struct aarch64_insn_data *data);
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#endif
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@ -1,3 +1,11 @@
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2015-10-12 Yao Qi <yao.qi@linaro.org>
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* linux-aarch64-low.c (extract_signed_bitfield): Remove.
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(aarch64_decode_ldr_literal): Move to gdb/arch/aarch64-insn.c.
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(aarch64_relocate_instruction): Likewise.
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(struct aarch64_insn_data): Move to gdb/arch/aarch64-insn.h.
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(struct aarch64_insn_visitor): Likewise.
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2015-10-12 Yao Qi <yao.qi@linaro.org>
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* linux-aarch64-low.c (struct aarch64_insn_data): New.
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@ -584,70 +584,6 @@ aarch64_get_thread_area (int lwpid, CORE_ADDR *addrp)
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return 0;
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}
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/* Extract a signed value from a bit field within an instruction
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encoding.
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INSN is the instruction opcode.
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WIDTH specifies the width of the bit field to extract (in bits).
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OFFSET specifies the least significant bit of the field where bits
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are numbered zero counting from least to most significant. */
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static int32_t
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extract_signed_bitfield (uint32_t insn, unsigned width, unsigned offset)
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{
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unsigned shift_l = sizeof (int32_t) * 8 - (offset + width);
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unsigned shift_r = sizeof (int32_t) * 8 - width;
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return ((int32_t) insn << shift_l) >> shift_r;
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}
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/* Decode an opcode if it represents an LDR or LDRSW instruction taking a
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literal offset from the current PC.
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ADDR specifies the address of the opcode.
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INSN specifies the opcode to test.
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IS_W is set if the instruction is LDRSW.
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IS64 receives size field from the decoded instruction.
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RT receives the 'rt' field from the decoded instruction.
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OFFSET receives the 'imm' field from the decoded instruction.
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Return 1 if the opcodes matches and is decoded, otherwise 0. */
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int
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aarch64_decode_ldr_literal (CORE_ADDR addr, uint32_t insn, int *is_w,
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int *is64, unsigned *rt, int32_t *offset)
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{
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/* LDR 0T01 1000 iiii iiii iiii iiii iiir rrrr */
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/* LDRSW 1001 1000 iiii iiii iiii iiii iiir rrrr */
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if ((insn & 0x3f000000) == 0x18000000)
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{
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*is_w = (insn >> 31) & 0x1;
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if (*is_w)
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{
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/* LDRSW always takes a 64-bit destination registers. */
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*is64 = 1;
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}
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else
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*is64 = (insn >> 30) & 0x1;
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*rt = (insn >> 0) & 0x1f;
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*offset = extract_signed_bitfield (insn, 19, 5) << 2;
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if (aarch64_debug)
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debug_printf ("decode: %s 0x%x %s %s%u, #?\n",
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core_addr_to_string_nz (addr), insn,
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*is_w ? "ldrsw" : "ldr",
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*is64 ? "x" : "w", *rt);
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return 1;
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}
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return 0;
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}
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/* List of opcodes that we need for building the jump pad and relocating
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an instruction. */
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@ -1924,49 +1860,6 @@ can_encode_int32 (int32_t val, unsigned bits)
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return rest == 0 || rest == -1;
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}
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/* Data passed to each method of aarch64_insn_visitor. */
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struct aarch64_insn_data
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{
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/* The instruction address. */
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CORE_ADDR insn_addr;
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};
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/* Visit different instructions by different methods. */
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struct aarch64_insn_visitor
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{
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/* Visit instruction B/BL OFFSET. */
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void (*b) (const int is_bl, const int32_t offset,
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struct aarch64_insn_data *data);
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/* Visit instruction B.COND OFFSET. */
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void (*b_cond) (const unsigned cond, const int32_t offset,
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struct aarch64_insn_data *data);
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/* Visit instruction CBZ/CBNZ Rn, OFFSET. */
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void (*cb) (const int32_t offset, const int is_cbnz,
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const unsigned rn, int is64,
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struct aarch64_insn_data *data);
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/* Visit instruction TBZ/TBNZ Rt, #BIT, OFFSET. */
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void (*tb) (const int32_t offset, int is_tbnz,
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const unsigned rt, unsigned bit,
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struct aarch64_insn_data *data);
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/* Visit instruction ADR/ADRP Rd, OFFSET. */
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void (*adr) (const int32_t offset, const unsigned rd,
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const int is_adrp, struct aarch64_insn_data *data);
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/* Visit instruction LDR/LDRSW Rt, OFFSET. */
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void (*ldr_literal) (const int32_t offset, const int is_sw,
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const unsigned rt, const int is64,
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struct aarch64_insn_data *data);
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/* Visit instruction INSN of other kinds. */
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void (*others) (const uint32_t insn, struct aarch64_insn_data *data);
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};
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/* Sub-class of struct aarch64_insn_data, store information of
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instruction relocation for fast tracepoint. Visitor can
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relocate an instruction from BASE.INSN_ADDR to NEW_ADDR and save
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@ -2195,54 +2088,6 @@ static const struct aarch64_insn_visitor visitor =
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aarch64_ftrace_insn_reloc_others,
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};
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/* Visit an instruction INSN by VISITOR with all needed information in DATA.
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PC relative instructions need to be handled specifically:
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- B/BL
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- B.COND
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- CBZ/CBNZ
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- TBZ/TBNZ
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- ADR/ADRP
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- LDR/LDRSW (literal) */
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static void
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aarch64_relocate_instruction (uint32_t insn,
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const struct aarch64_insn_visitor *visitor,
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struct aarch64_insn_data *data)
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{
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int is_bl;
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int is64;
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int is_sw;
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int is_cbnz;
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int is_tbnz;
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int is_adrp;
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unsigned rn;
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unsigned rt;
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unsigned rd;
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unsigned cond;
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unsigned bit;
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int32_t offset;
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if (aarch64_decode_b (data->insn_addr, insn, &is_bl, &offset))
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visitor->b (is_bl, offset, data);
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else if (aarch64_decode_bcond (data->insn_addr, insn, &cond, &offset))
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visitor->b_cond (cond, offset, data);
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else if (aarch64_decode_cb (data->insn_addr, insn, &is64, &is_cbnz, &rn,
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&offset))
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visitor->cb (offset, is_cbnz, rn, is64, data);
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else if (aarch64_decode_tb (data->insn_addr, insn, &is_tbnz, &bit, &rt,
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&offset))
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visitor->tb (offset, is_tbnz, rt, bit, data);
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else if (aarch64_decode_adr (data->insn_addr, insn, &is_adrp, &rd, &offset))
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visitor->adr (offset, rd, is_adrp, data);
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else if (aarch64_decode_ldr_literal (data->insn_addr, insn, &is_sw, &is64,
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&rt, &offset))
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visitor->ldr_literal (offset, is_sw, rt, is64, data);
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else
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visitor->others (insn, data);
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}
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/* Implementation of linux_target_ops method
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"install_fast_tracepoint_jump_pad". */
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