2007-05-18 Paul Brook <paul@codesourcery.com>
bfd/ * elf32-arm.c (ARM2THUMB_V5_STATIC_GLUE_SIZE): Define. (a2t1v5_ldr_insn, a2t1v5_ldr_insn): New. (record_arm_to_thumb_glue): Add v5t non-pic glue. (elf32_arm_create_thumb_stub): Ditto. ld/testsuite/ * ld-arm/arm-call.d: Update expected output.
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26079076f5
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@ -1,3 +1,10 @@
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2007-05-18 Paul Brook <paul@codesourcery.com>
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* elf32-arm.c (ARM2THUMB_V5_STATIC_GLUE_SIZE): Define.
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(a2t1v5_ldr_insn, a2t1v5_ldr_insn): New.
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(record_arm_to_thumb_glue): Add v5t non-pic glue.
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(elf32_arm_create_thumb_stub): Ditto.
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2007-05-16 H.J. Lu <hongjiu.lu@intel.com>
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Alan Modra <amodra@bigpond.net.au>
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@ -2582,6 +2582,13 @@ find_arm_glue (struct bfd_link_info *link_info,
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__func_addr:
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.word func @ behave as if you saw a ARM_32 reloc.
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(v5t static images)
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.arm
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__func_from_arm:
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ldr pc, __func_addr
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__func_addr:
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.word func @ behave as if you saw a ARM_32 reloc.
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(relocatable images)
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.arm
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__func_from_arm:
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@ -2597,6 +2604,10 @@ static const insn32 a2t1_ldr_insn = 0xe59fc000;
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static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
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static const insn32 a2t3_func_addr_insn = 0x00000001;
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#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
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static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
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static const insn32 a2t2v5_func_addr_insn = 0x00000001;
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#define ARM2THUMB_PIC_GLUE_SIZE 16
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static const insn32 a2t1p_ldr_insn = 0xe59fc004;
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static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
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@ -2745,6 +2756,8 @@ record_arm_to_thumb_glue (struct bfd_link_info * link_info,
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if (link_info->shared || globals->root.is_relocatable_executable
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|| globals->pic_veneer)
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size = ARM2THUMB_PIC_GLUE_SIZE;
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else if (globals->use_blx)
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size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
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else
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size = ARM2THUMB_STATIC_GLUE_SIZE;
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@ -4187,6 +4200,15 @@ elf32_arm_create_thumb_stub (struct bfd_link_info * info,
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bfd_put_32 (output_bfd, ret_offset,
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s->contents + my_offset + 12);
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}
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else if (globals->use_blx)
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{
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put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
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s->contents + my_offset);
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/* It's a thumb address. Add the low order bit. */
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bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
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s->contents + my_offset + 4);
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}
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else
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{
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put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
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@ -1,3 +1,7 @@
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2007-05-18 Paul Brook <paul@codesourcery.com>
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* ld-arm/arm-call.d: Update expected output.
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2007-05-17 Paul Brook <paul@codesourcery.com>
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* ld-elf/multibss1.s: Use %nobits instead of @nobits.
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@ -11,9 +11,9 @@ Disassembly of section .text:
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8010: fa00000a blx 8040 <t1>
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8014: fb000009 blx 8042 <t2>
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8018: ea00000f b 805c <__t1_from_arm>
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801c: ea000011 b 8068 <__t2_from_arm>
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801c: ea000010 b 8064 <__t2_from_arm>
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8020: 1b00000d blne 805c <__t1_from_arm>
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8024: 1b00000f blne 8068 <__t2_from_arm>
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8024: 1b00000e blne 8064 <__t2_from_arm>
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8028: 1b000003 blne 803c <arm>
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802c: eb000002 bl 803c <arm>
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8030: faffffff blx 8034 <thumblocal>
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@ -48,11 +48,9 @@ Disassembly of section .text:
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8058: f7ff efd2 blx 8000 <_start>
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0000805c <__t1_from_arm>:
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805c: e59fc000 ldr ip, \[pc, #0\] ; 8064 <__t1_from_arm\+0x8>
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8060: e12fff1c bx ip
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8064: 00008041 andeq r8, r0, r1, asr #32
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805c: e51ff004 ldr pc, \[pc, #-4\] ; 8060 <__t1_from_arm\+0x4>
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8060: 00008041 andeq r8, r0, r1, asr #32
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00008068 <__t2_from_arm>:
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8068: e59fc000 ldr ip, \[pc, #0\] ; 8070 <__t2_from_arm\+0x8>
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806c: e12fff1c bx ip
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8070: 00008043 andeq r8, r0, r3, asr #32
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00008064 <__t2_from_arm>:
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8064: e51ff004 ldr pc, \[pc, #-4\] ; 8068 <__t2_from_arm\+0x4>
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8068: 00008043 andeq r8, r0, r3, asr #32
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