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oops - omitted from previous delta

This commit is contained in:
Nick Clifton 2013-01-11 09:53:22 +00:00
parent 5817ffd1f8
commit 2624489484
40 changed files with 87546 additions and 0 deletions
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22
gas/testsuite/gas/metag/labelarithmetic.d Normal file
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#as: -mcpu=metac21
#objdump: -dr
#name: labelarithmetic
.*: +file format .*
Disassembly of section \.text:
00000000 <lbl1>:
.*: 20 04 2c 86 ADD TXL1START,CPC0,#0x10
00000004 <lbl2>:
.*: 04 20 00 80 MOV A0StP,CPC0
.*: a0 00 00 82 ADD A0StP,A0StP,#0x14
.*: 00 8c 01 a3 MOV TXL1END,A0StP
00000010 <loop_start>:
.*: 04 04 18 00 MOV D0Ar2,D0Ar4
.*: fe ff ff a0 NOP
00000018 <loop_end>:
.*: 04 02 18 01 MOV D1Ar1,D1Ar5

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gas/testsuite/gas/metag/labelarithmetic.s Normal file
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lbl1: ADD TXL1START, CPC0, #(loop_start-lbl1)
lbl2: MOV A0.0, CPC0
ADD A0.0, A0.0, #(loop_end-lbl2)
MOV TXL1END, A0.0
loop_start: MOV D0Ar2, D0Ar4
NOP
loop_end: MOV D1Ar1, D1Ar5

6876
gas/testsuite/gas/metag/metacore12.d Normal file
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gas/testsuite/gas/metag/metacore12.s Normal file
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gas/testsuite/gas/metag/metacore21-invalid.l Normal file
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.*: Assembler messages:
.*:4: Error: .*
.*:4: Error: .*
.*:4: Error: .*
.*:4: Error: .*
.*:4: Error: .*
.*:4: Error: .*
.*:4: Error: .*
.*:5: Error: .*
.*:5: Error: .*
.*:6: Error: .*
.*:6: Error: .*
.*:7: Error: .*
.*:7: Error: .*
.*:8: Error: .*
.*:8: Error: .*
.*:8: Error: .*

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gas/testsuite/gas/metag/metacore21-invalid.s Normal file
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# Check illegal instructions
.text
_start:
SETL [D0.0+D1.0],A0.0,A1.0
SETL [D0.0+D0.1],D0.2,D1.2
SETD [A0.0+A0.1],A0.2
ASL D0.0,D1.0,D0.0
GETD D0.0,[D0.0--D0.0]

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gas/testsuite/gas/metag/metacore21.d Normal file
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gas/testsuite/gas/metag/metacore21.s Normal file
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18
gas/testsuite/gas/metag/metacore21ext.d Normal file
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#as: -mcpu=metac21
#objdump: -dr
#name: metacpu21ext
.*: +file format .*
Disassembly of section \.text:
00000000 <.text>:
.*: 40 46 00 60 MULD D0Re0,D0Ar6,D0Ar2
.*: ad 41 c0 c7 MOVL RABZ,\[D0Ar6\+\+\]
.*: cd 41 c8 c7 MOVL RAWZ,\[D1Ar5\+\+\]
.*: ad 81 d0 c7 MOVL RADZ,\[D0Ar4\+\+\]
.*: cd 81 e0 c7 MOVL RABX,\[D1Ar3\+\+\]
.*: ad c1 e8 c7 MOVL RAWX,\[D0Ar2\+\+\]
.*: cd c1 f0 c7 MOVL RADX,\[D1Ar1\+\+\]
.*: ad 01 f9 c7 MOVL RAMX,\[D0FrT\+\+\]
.*: ed 81 f8 c7 MOVL RAMX,\[A0\.2\+\+\]

10
gas/testsuite/gas/metag/metacore21ext.s Normal file
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.text
MUL D0Re0,D0Ar6,D0Ar2
MOVL RABZ,[D0.1++]
MOVL RAWZ,[D1.1++]
MOVL RADZ,[D0.2++]
MOVL RABX,[D1.2++]
MOVL RAWX,[D0.3++]
MOVL RADX,[D1.3++]
MOVL RAMX,[D0.4++]
MOVL RAM16X,[A0.2++]

5
gas/testsuite/gas/metag/metadsp21-invalid.l Normal file
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.*: Assembler messages:
.*:4: Error: .*
.*:5: Error: .*
.*:6: Error: .*
.*:7: Error: .*

8
gas/testsuite/gas/metag/metadsp21-invalid.s Normal file
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# Check illegal instructions
.text
_start:
DL MOV D1Ar1,#0xff
DP MUL D0Re0, D0Ar6, D0Ar4
DN MUL D0Re0, D0Re0, [D0AR.0+D0ARI.1++]
DZ MUL [D0BW.1], D0Re0, [D0AR.0+D0ARI.1++]
ADD D1Ar1,D1Ar1,#0xff

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11
gas/testsuite/gas/metag/metadsp21ext.d Normal file
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#as: -mdsp=metac21
#objdump: -dr
#name: metadsp21ext
.*: +file format .*
Disassembly of section \.text:
00000000 <.text>:
.*: e0 ce 02 90 D T0 #0x0,#0xb,#0x7,#0xe
.*: e0 ce 82 90 D T0 #0x10,#0xb,#0x7,#0xe

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gas/testsuite/gas/metag/metadsp21ext.s Normal file
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.text
D T0 D0.0,D0.11,D0.7,D0.14
D T0 AC0.0,D0.11,D0.7,D0.14

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2230
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gas/testsuite/gas/metag/metafpu21ext.d Normal file
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#as: -mfpu=metac21
#objdump: -dr
#name: metafpu21ext
.*: +file format .*
Disassembly of section \.text:
00000000 <.text>:
.*: a0 80 00 f0 FD ABS FX\.0,FX\.2
.*: 80 00 18 f0 F ABS FX\.3,FX\.0
.*: c0 00 31 f0 FL ABS FX\.6,FX\.4
.*: 03 22 00 be F MMOVD D1Re0,D1Ar1,D1\.7,FX\.0,FX\.1,FX\.2
.*: 82 00 02 be F MMOVD D0Re0,D0Ar6,FX\.8,FX\.9
.*: 82 a0 00 bf F MMOVL D0Re0,D0Ar6,D0\.7,FX\.2,FX\.4,FX\.6
.*: 83 00 18 bf F MMOVL D1Ar1,D1RtP,FX\.0,FX\.2
.*: 03 22 00 ce F MMOVD FX\.0,FX\.1,FX\.2,D1Re0,D1Ar1,D1\.7
.*: 82 00 02 ce F MMOVD FX\.8,FX\.9,D0Re0,D0Ar6
.*: 82 a0 00 cf F MMOVL FX\.2,FX\.4,FX\.6,D0Re0,D0Ar6,D0\.7
.*: 83 00 18 cf F MMOVL FX\.0,FX\.2,D1Ar1,D1RtP
.*: 20 80 00 f0 FD MOV FX\.0,FX\.2
.*: 00 00 18 f0 F MOV FX\.3,FX\.0
.*: 40 00 31 f0 FL MOV FX\.6,FX\.4
.*: fb ff 07 f0 FD MOV FX\.0,#0xffff
.*: 81 00 18 f0 F MOV FX\.3,#0x10
.*: 05 78 30 f0 FL MOV FX\.6,#0xf00
.*: 20 81 00 f0 FD NEG FX\.0,FX\.2
.*: 00 01 18 f0 F NEG FX\.3,FX\.0
.*: 40 01 31 f0 FL NEG FX\.6,FX\.4
.*: 80 51 30 f0 F PACK FX\.6,FX\.1,FX\.8
.*: c0 01 30 f0 FL SWAP FX\.6,FX\.0
.*: 20 80 01 f3 FD CMP FX\.6,FX\.0
.*: 00 80 01 f3 F CMP FX\.6,FX\.0
.*: 40 80 01 f3 FL CMP FX\.6,FX\.0
.*: 20 80 09 f3 FDA CMP FX\.6,FX\.0
.*: 00 80 09 f3 FA CMP FX\.6,FX\.0
.*: 40 80 09 f3 FLA CMP FX\.6,FX\.0
.*: a0 80 01 f3 FDQ CMP FX\.6,FX\.0
.*: 80 80 01 f3 FQ CMP FX\.6,FX\.0
.*: c0 80 01 f3 FLQ CMP FX\.6,FX\.0
.*: a0 80 09 f3 FDAQ CMP FX\.6,FX\.0
.*: 80 80 09 f3 FAQ CMP FX\.6,FX\.0
.*: c0 80 09 f3 FLAQ CMP FX\.6,FX\.0
.*: 20 81 01 f3 FD CMP FX\.6,#0
.*: 00 81 01 f3 F CMP FX\.6,#0
.*: 40 81 01 f3 FL CMP FX\.6,#0
.*: a1 04 30 f3 FD MAX FX\.6,FX\.0,FX\.2
.*: 81 0a 19 f3 F MAX FX\.3,FX\.4,FX\.5
.*: c1 0c 11 f3 FL MAX FX\.2,FX\.4,FX\.6
.*: 21 04 30 f3 FD MIN FX\.6,FX\.0,FX\.2
.*: 01 0a 19 f3 F MIN FX\.3,FX\.4,FX\.5
.*: 41 0c 11 f3 FL MIN FX\.2,FX\.4,FX\.6
.*: 21 41 30 f2 F DTOF FX\.6,FX\.1
.*: 01 81 00 f2 F FTOD FX\.0,FX\.2
.*: 40 03 30 f2 FL FTOH FX\.6,FX\.0
.*: 00 43 19 f2 F FTOH FX\.3,FX\.5
.*: 20 03 10 f2 F DTOH FX\.2,FX\.0
.*: 00 71 30 f2 FZ FTOI FX\.6,FX\.1
.*: 00 21 11 f2 F FTOI FX\.2,FX\.4
.*: 40 21 20 f2 FL FTOI FX\.4,FX\.0
.*: 40 71 19 f2 FLZ FTOI FX\.3,FX\.5
.*: 20 61 30 f2 F DTOI FX\.6,FX\.1
.*: 20 71 30 f2 FZ DTOI FX\.6,FX\.1
.*: 20 23 11 f2 F DTOL FX\.2,FX\.4
.*: 20 33 11 f2 FZ DTOL FX\.2,FX\.4
.*: 00 c6 30 f2 F FTOX FX\.6,FX\.3,#0x3
.*: 40 08 20 f2 FL FTOX FX\.4,FX\.0,#0x4
.*: 20 10 11 f2 F DTOX FX\.2,FX\.4,#0x8
.*: a0 06 11 f2 F DTOXL FX\.2,FX\.4,#0x6
.*: 21 03 31 f2 F HTOD FX\.6,FX\.4
.*: 41 83 30 f2 FL HTOF FX\.6,FX\.2
.*: 01 03 11 f2 F HTOF FX\.2,FX\.4
.*: 01 61 30 f2 F ITOF FX\.6,FX\.1
.*: 41 21 20 f2 FL ITOF FX\.4,FX\.0
.*: 21 21 11 f2 F ITOD FX\.2,FX\.4
.*: 21 23 11 f2 F LTOD FX\.2,FX\.4
.*: 01 c4 10 f2 F XTOF FX\.2,FX\.3,#0x2
.*: 41 06 30 f2 FL XTOF FX\.6,FX\.0,#0x3
.*: 21 08 11 f2 F XTOD FX\.2,FX\.4,#0x4
.*: a1 07 11 f2 F XLTOD FX\.2,FX\.4,#0x7
.*: 21 88 00 f1 FD ADD FX\.0,FX\.2,FX\.4
.*: 01 40 18 f1 F ADD FX\.3,FX\.1,FX\.0
.*: 41 04 31 f1 FL ADD FX\.6,FX\.4,FX\.2
.*: a1 88 00 f1 FDI ADD FX\.0,FX\.2,FX\.4
.*: 81 40 18 f1 FI ADD FX\.3,FX\.1,FX\.0
.*: c1 04 31 f1 FLI ADD FX\.6,FX\.4,FX\.2
.*: 20 89 00 f1 FD MUL FX\.0,FX\.2,FX\.4
.*: 00 41 18 f1 F MUL FX\.3,FX\.1,FX\.0
.*: 40 05 31 f1 FL MUL FX\.6,FX\.4,FX\.2
.*: a0 89 00 f1 FDI MUL FX\.0,FX\.2,FX\.4
.*: 80 41 18 f1 FI MUL FX\.3,FX\.1,FX\.0
.*: c0 05 31 f1 FLI MUL FX\.6,FX\.4,FX\.2
.*: 21 89 00 f1 FD SUB FX\.0,FX\.2,FX\.4
.*: 01 41 18 f1 F SUB FX\.3,FX\.1,FX\.0
.*: 41 05 31 f1 FL SUB FX\.6,FX\.4,FX\.2
.*: a1 89 00 f1 FDI SUB FX\.0,FX\.2,FX\.4
.*: 81 41 18 f1 FI SUB FX\.3,FX\.1,FX\.0
.*: c1 05 31 f1 FLI SUB FX\.6,FX\.4,FX\.2
.*: 20 88 00 f6 FD MAC ACF\.0,FX\.2,FX\.4
.*: 00 40 00 f6 F MAC ACF\.0,FX\.1,FX\.0
.*: 24 88 00 f6 FD MAR FX\.0,FX\.2,FX\.4
.*: 04 40 18 f6 F MAR FX\.3,FX\.1,FX\.0
.*: 24 89 00 f6 FD MARS FX\.0,FX\.2,FX\.4
.*: 04 41 18 f6 F MARS FX\.3,FX\.1,FX\.0
.*: 28 0c 11 f6 FD MAW FX\.2,FX\.4,FX\.6
.*: 08 0c 08 f6 F MAW FX\.1,FX\.0,FX\.6
.*: 28 0d 11 f6 FD MAWS FX\.2,FX\.4,FX\.6
.*: 08 0d 08 f6 F MAWS FX\.1,FX\.0,FX\.6
.*: 29 0c 01 f6 FD MAW1 FX\.4,FX\.6
.*: 09 0c 00 f6 F MAW1 FX\.0,FX\.6
.*: 29 0d 01 f6 FD MAWS1 FX\.4,FX\.6
.*: 09 0d 00 f6 F MAWS1 FX\.0,FX\.6
.*: 20 88 00 f5 FD MXA FX\.0,FX\.2,FX\.4
.*: 00 40 18 f5 F MXA FX\.3,FX\.1,FX\.0
.*: 40 04 31 f5 FL MXA FX\.6,FX\.4,FX\.2
.*: a0 88 00 f5 FDI MXA FX\.0,FX\.2,FX\.4
.*: 80 40 18 f5 FI MXA FX\.3,FX\.1,FX\.0
.*: c0 04 31 f5 FLI MXA FX\.6,FX\.4,FX\.2
.*: 20 89 00 f5 FD MXAS FX\.0,FX\.2,FX\.4
.*: 00 41 18 f5 F MXAS FX\.3,FX\.1,FX\.0
.*: 40 05 31 f5 FL MXAS FX\.6,FX\.4,FX\.2
.*: a0 89 00 f5 FDI MXAS FX\.0,FX\.2,FX\.4
.*: 80 41 18 f5 FI MXAS FX\.3,FX\.1,FX\.0
.*: c0 05 31 f5 FLI MXAS FX\.6,FX\.4,FX\.2
.*: 21 88 00 f5 FD MXA1 FX\.0,FX\.2,FX\.4
.*: 01 40 18 f5 F MXA1 FX\.3,FX\.1,FX\.0
.*: 41 04 31 f5 FL MXA1 FX\.6,FX\.4,FX\.2
.*: a1 88 00 f5 FDI MXA1 FX\.0,FX\.2,FX\.4
.*: 81 40 18 f5 FI MXA1 FX\.3,FX\.1,FX\.0
.*: c1 04 31 f5 FLI MXA1 FX\.6,FX\.4,FX\.2
.*: 21 89 00 f5 FD MXAS1 FX\.0,FX\.2,FX\.4
.*: 01 41 18 f5 F MXAS1 FX\.3,FX\.1,FX\.0
.*: 41 05 31 f5 FL MXAS1 FX\.6,FX\.4,FX\.2
.*: a1 89 00 f5 FDI MXAS1 FX\.0,FX\.2,FX\.4
.*: 81 41 18 f5 FI MXAS1 FX\.3,FX\.1,FX\.0
.*: c1 05 31 f5 FLI MXAS1 FX\.6,FX\.4,FX\.2
.*: 30 88 00 f6 FD MUZ FX\.0,FX\.2,FX\.4
.*: 10 4c 21 f6 F MUZ FX\.4,FX\.5,FX\.6
.*: 50 04 31 f6 FL MUZ FX\.6,FX\.4,FX\.2
.*: b0 88 00 f6 FDI MUZ FX\.0,FX\.2,FX\.4
.*: 90 4c 21 f6 FI MUZ FX\.4,FX\.5,FX\.6
.*: d0 04 31 f6 FLI MUZ FX\.6,FX\.4,FX\.2
.*: 32 88 00 f6 FDQ MUZ FX\.0,FX\.2,FX\.4
.*: 12 4c 21 f6 FQ MUZ FX\.4,FX\.5,FX\.6
.*: 52 04 31 f6 FLQ MUZ FX\.6,FX\.4,FX\.2
.*: b2 88 00 f6 FDIQ MUZ FX\.0,FX\.2,FX\.4
.*: 92 4c 21 f6 FIQ MUZ FX\.4,FX\.5,FX\.6
.*: d2 04 31 f6 FLIQ MUZ FX\.6,FX\.4,FX\.2
.*: 30 89 00 f6 FD MUZS FX\.0,FX\.2,FX\.4
.*: 10 4d 21 f6 F MUZS FX\.4,FX\.5,FX\.6
.*: 50 05 31 f6 FL MUZS FX\.6,FX\.4,FX\.2
.*: 31 88 00 f6 FD MUZ1 FX\.0,FX\.2,FX\.4
.*: 11 4c 21 f6 F MUZ1 FX\.4,FX\.5,FX\.6
.*: 51 04 31 f6 FL MUZ1 FX\.6,FX\.4,FX\.2
.*: 31 89 00 f6 FD MUZS1 FX\.0,FX\.2,FX\.4
.*: 11 4d 21 f6 F MUZS1 FX\.4,FX\.5,FX\.6
.*: 51 05 31 f6 FL MUZS1 FX\.6,FX\.4,FX\.2
.*: 20 80 00 f7 FD RCP FX\.0,FX\.2
.*: 00 40 18 f7 F RCP FX\.3,FX\.1
.*: 40 00 31 f7 FL RCP FX\.6,FX\.4
.*: a0 80 00 f7 FDI RCP FX\.0,FX\.2
.*: 80 40 18 f7 FI RCP FX\.3,FX\.1
.*: c0 00 31 f7 FLI RCP FX\.6,FX\.4
.*: 20 84 00 f7 FDZ RCP FX\.0,FX\.2
.*: 00 44 18 f7 FZ RCP FX\.3,FX\.1
.*: 40 04 31 f7 FLZ RCP FX\.6,FX\.4
.*: a0 84 00 f7 FDIZ RCP FX\.0,FX\.2
.*: 80 44 18 f7 FIZ RCP FX\.3,FX\.1
.*: c0 04 31 f7 FLIZ RCP FX\.6,FX\.4
.*: 20 82 00 f7 FDQ RCP FX\.0,FX\.2
.*: 00 42 18 f7 FQ RCP FX\.3,FX\.1
.*: 40 02 31 f7 FLQ RCP FX\.6,FX\.4
.*: a0 82 00 f7 FDIQ RCP FX\.0,FX\.2
.*: 80 42 18 f7 FIQ RCP FX\.3,FX\.1
.*: c0 02 31 f7 FLIQ RCP FX\.6,FX\.4
.*: 20 81 00 f7 FD RSQ FX\.0,FX\.2
.*: 00 41 18 f7 F RSQ FX\.3,FX\.1
.*: 40 01 31 f7 FL RSQ FX\.6,FX\.4
.*: a0 81 00 f7 FDI RSQ FX\.0,FX\.2
.*: 80 41 18 f7 FI RSQ FX\.3,FX\.1
.*: c0 01 31 f7 FLI RSQ FX\.6,FX\.4
.*: 20 85 00 f7 FDZ RSQ FX\.0,FX\.2
.*: 00 45 18 f7 FZ RSQ FX\.3,FX\.1
.*: 40 05 31 f7 FLZ RSQ FX\.6,FX\.4
.*: a0 85 00 f7 FDIZ RSQ FX\.0,FX\.2
.*: 80 45 18 f7 FIZ RSQ FX\.3,FX\.1
.*: c0 05 31 f7 FLIZ RSQ FX\.6,FX\.4
.*: 20 83 00 f7 FDQ RSQ FX\.0,FX\.2
.*: 00 43 18 f7 FQ RSQ FX\.3,FX\.1
.*: 40 03 31 f7 FLQ RSQ FX\.6,FX\.4
.*: a0 83 00 f7 FDIQ RSQ FX\.0,FX\.2
.*: 80 43 18 f7 FIQ RSQ FX\.3,FX\.1
.*: c0 03 31 f7 FLIQ RSQ FX\.6,FX\.4
.*: 00 04 31 f4 FL ADDRE FX\.6,FX\.4,FX\.2
.*: 80 04 31 f4 FLI ADDRE FX\.6,FX\.4,FX\.2
.*: 01 04 31 f4 FL MULRE FX\.6,FX\.4,FX\.2
.*: 81 04 31 f4 FLI MULRE FX\.6,FX\.4,FX\.2
.*: 00 05 31 f4 FL SUBRE FX\.6,FX\.4,FX\.2
.*: 80 05 31 f4 FLI SUBRE FX\.6,FX\.4,FX\.2

191
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.text
FD ABS FX.0,FX.2
F ABS FX.3,FX.0
FL ABS FX.6,FX.4
F MMOVD D1.0,D1.3,D1.7,FX.0,FX.1,FX.2
F MMOVD D0.0,D0.1,FX.8,FX.9
F MMOVL D0.0,D0.1,D0.7,FX.2,FX.4,FX.6
F MMOVL D1.3,D1.4,FX.0,FX.2
F MMOVD FX.0,FX.1,FX.2,D1.0,D1.3,D1.7
F MMOVD FX.8,FX.9,D0.0,D0.1
F MMOVL FX.2,FX.4,FX.6,D0.0,D0.1,D0.7
F MMOVL FX.0,FX.2,D1.3,D1.4
FD MOV FX.0,FX.2
F MOV FX.3,FX.0
FL MOV FX.6,FX.4
FD MOV FX.0,#0xffff
F MOV FX.3,#0x10
FL MOV FX.6,#0xf00
FD NEG FX.0,FX.2
F NEG FX.3,FX.0
FL NEG FX.6,FX.4
F PACK FX.6,FX.1,FX.8
FL SWAP FX.6,FX.0
FD CMP FX.6,FX.0
F CMP FX.6,FX.0
FL CMP FX.6,FX.0
FDA CMP FX.6,FX.0
FA CMP FX.6,FX.0
FLA CMP FX.6,FX.0
FDQ CMP FX.6,FX.0
FQ CMP FX.6,FX.0
FLQ CMP FX.6,FX.0
FDAQ CMP FX.6,FX.0
FAQ CMP FX.6,FX.0
FLAQ CMP FX.6,FX.0
FD CMP FX.6,#0x0
F CMP FX.6,#0x0
FL CMP FX.6,#0x0
FD MAX FX.6,FX.0,FX.2
F MAX FX.3,FX.4,FX.5
FL MAX FX.2,FX.4,FX.6
FD MIN FX.6,FX.0,FX.2
F MIN FX.3,FX.4,FX.5
FL MIN FX.2,FX.4,FX.6
F DTOF FX.6,FX.1
F FTOD FX.0,FX.2
FL FTOH FX.6,FX.0
F FTOH FX.3,FX.5
F DTOH FX.2,FX.0
FZ FTOI FX.6,FX.1
F FTOI FX.2,FX.4
FL FTOI FX.4,FX.0
FLZ FTOI FX.3,FX.5
F DTOI FX.6,FX.1
FZ DTOI FX.6,FX.1
F DTOL FX.2,FX.4
FZ DTOL FX.2,FX.4
F FTOX FX.6,FX.3,#3
FL FTOX FX.4,FX.0,#4
F DTOX FX.2,FX.4,#8
F DTOXL FX.2,FX.4,#6
F HTOD FX.6,FX.4
FL HTOF FX.6,FX.2
F HTOF FX.2,FX.4
F ITOF FX.6,FX.1
FL ITOF FX.4,FX.0
F ITOD FX.2,FX.4
F LTOD FX.2,FX.4
F XTOF FX.2,FX.3,#2
FL XTOF FX.6,FX.0,#3
F XTOD FX.2,FX.4,#4
F XLTOD FX.2,FX.4,#7
FD ADD FX.0,FX.2,FX.4
F ADD FX.3,FX.1,FX.0
FL ADD FX.6,FX.4,FX.2
FDI ADD FX.0,FX.2,FX.4
FI ADD FX.3,FX.1,FX.0
FLI ADD FX.6,FX.4,FX.2
FD MUL FX.0,FX.2,FX.4
F MUL FX.3,FX.1,FX.0
FL MUL FX.6,FX.4,FX.2
FDI MUL FX.0,FX.2,FX.4
FI MUL FX.3,FX.1,FX.0
FLI MUL FX.6,FX.4,FX.2
FD SUB FX.0,FX.2,FX.4
F SUB FX.3,FX.1,FX.0
FL SUB FX.6,FX.4,FX.2
FDI SUB FX.0,FX.2,FX.4
FI SUB FX.3,FX.1,FX.0
FLI SUB FX.6,FX.4,FX.2
FD MAC ACF.0,FX.2,FX.4
F MAC ACF.0,FX.1,FX.0
FD MAR FX.0,FX.2,FX.4
F MAR FX.3,FX.1,FX.0
FD MARS FX.0,FX.2,FX.4
F MARS FX.3,FX.1,FX.0
FD MAW FX.2,FX.4,FX.6
F MAW FX.1,FX.0,FX.6
FD MAWS FX.2,FX.4,FX.6
F MAWS FX.1,FX.0,FX.6
FD MAW1 FX.4,FX.6
F MAW1 FX.0,FX.6
FD MAWS1 FX.4,FX.6
F MAWS1 FX.0,FX.6
FD MXA FX.0,FX.2,FX.4
F MXA FX.3,FX.1,FX.0
FL MXA FX.6,FX.4,FX.2
FDI MXA FX.0,FX.2,FX.4
FI MXA FX.3,FX.1,FX.0
FLI MXA FX.6,FX.4,FX.2
FD MXAS FX.0,FX.2,FX.4
F MXAS FX.3,FX.1,FX.0
FL MXAS FX.6,FX.4,FX.2
FDI MXAS FX.0,FX.2,FX.4
FI MXAS FX.3,FX.1,FX.0
FLI MXAS FX.6,FX.4,FX.2
FD MXA1 FX.0,FX.2,FX.4
F MXA1 FX.3,FX.1,FX.0
FL MXA1 FX.6,FX.4,FX.2
FDI MXA1 FX.0,FX.2,FX.4
FI MXA1 FX.3,FX.1,FX.0
FLI MXA1 FX.6,FX.4,FX.2
FD MXAS1 FX.0,FX.2,FX.4
F MXAS1 FX.3,FX.1,FX.0
FL MXAS1 FX.6,FX.4,FX.2
FDI MXAS1 FX.0,FX.2,FX.4
FI MXAS1 FX.3,FX.1,FX.0
FLI MXAS1 FX.6,FX.4,FX.2
FD MUZ FX.0,FX.2,FX.4
F MUZ FX.4,FX.5,FX.6
FL MUZ FX.6,FX.4,FX.2
FDI MUZ FX.0,FX.2,FX.4
FI MUZ FX.4,FX.5,FX.6
FLI MUZ FX.6,FX.4,FX.2
FDQ MUZ FX.0,FX.2,FX.4
FQ MUZ FX.4,FX.5,FX.6
FLQ MUZ FX.6,FX.4,FX.2
FDIQ MUZ FX.0,FX.2,FX.4
FIQ MUZ FX.4,FX.5,FX.6
FLIQ MUZ FX.6,FX.4,FX.2
FD MUZS FX.0,FX.2,FX.4
F MUZS FX.4,FX.5,FX.6
FL MUZS FX.6,FX.4,FX.2
FD MUZ1 FX.0,FX.2,FX.4
F MUZ1 FX.4,FX.5,FX.6
FL MUZ1 FX.6,FX.4,FX.2
FD MUZS1 FX.0,FX.2,FX.4
F MUZS1 FX.4,FX.5,FX.6
FL MUZS1 FX.6,FX.4,FX.2
FD RCP FX.0,FX.2
F RCP FX.3,FX.1
FL RCP FX.6,FX.4
FDI RCP FX.0,FX.2
FI RCP FX.3,FX.1
FLI RCP FX.6,FX.4
FDZ RCP FX.0,FX.2
FZ RCP FX.3,FX.1
FLZ RCP FX.6,FX.4
FDIZ RCP FX.0,FX.2
FIZ RCP FX.3,FX.1
FLIZ RCP FX.6,FX.4
FDQ RCP FX.0,FX.2
FQ RCP FX.3,FX.1
FLQ RCP FX.6,FX.4
FDIQ RCP FX.0,FX.2
FIQ RCP FX.3,FX.1
FLIQ RCP FX.6,FX.4
FD RSQ FX.0,FX.2
F RSQ FX.3,FX.1
FL RSQ FX.6,FX.4
FDI RSQ FX.0,FX.2
FI RSQ FX.3,FX.1
FLI RSQ FX.6,FX.4
FDZ RSQ FX.0,FX.2
FZ RSQ FX.3,FX.1
FLZ RSQ FX.6,FX.4
FDIZ RSQ FX.0,FX.2
FIZ RSQ FX.3,FX.1
FLIZ RSQ FX.6,FX.4
FDQ RSQ FX.0,FX.2
FQ RSQ FX.3,FX.1
FLQ RSQ FX.6,FX.4
FDIQ RSQ FX.0,FX.2
FIQ RSQ FX.3,FX.1
FLIQ RSQ FX.6,FX.4
FL ADDRE FX.6,FX.4,FX.2
FLI ADDRE FX.6,FX.4,FX.2
FL MULRE FX.6,FX.4,FX.2
FLI MULRE FX.6,FX.4,FX.2
FL SUBRE FX.6,FX.4,FX.2
FLI SUBRE FX.6,FX.4,FX.2

43
gas/testsuite/gas/metag/metag.exp Normal file
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# Meta assembler testsuite
# Copyright 2013
# Free Software Foundation, Inc.
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
if [istarget metag-*-*] {
# Meta 1.2 geninst
run_dump_test "metacore12"
# Meta 2.1 geninst
run_dump_test "metacore21"
# Meta 2.1 extra
run_dump_test "metacore21ext"
# Meta 2.1 FPU geninst
run_dump_test "metafpu21"
# Meta 2.1 FPU extra
run_dump_test "metafpu21ext"
# Meta 2.1 DSP
run_dump_test "metadsp21"
# Meta 2.1 DSP extra
run_dump_test "metadsp21ext"
# Meta 2.1 illegal instructions
run_list_test "metacore21-invalid" ""
# Meta 2.1 DSP illegal instructions
run_list_test "metadsp21-invalid" "-mdsp=metac21"
# label arithmetic
run_dump_test "labelarithmetic"
# TLS
run_dump_test "tls"
}

26
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#objdump: -dr
#name: tls
.*: +file format .*
Disassembly of section \.text:
00000000 <.text>:
0: 00 00 18 03 ADD D1Ar1,D1Ar1,#0
0: R_METAG_TLS_GD _a
4: 00 00 18 03 ADD D1Ar1,D1Ar1,#0
4: R_METAG_TLS_LDM _b
8: 01 00 00 02 ADDT D0Re0,D0Re0,#0
8: R_METAG_TLS_LDO_HI16 _b
c: 00 00 00 02 ADD D0Re0,D0Re0,#0
c: R_METAG_TLS_LDO_LO16 _b
10: 0d 00 20 a7 GETD D0FrT,\[A1LbP\]
10: R_METAG_TLS_IE _b
14: 05 00 00 02 MOVT D0Re0,#0
14: R_METAG_TLS_IENONPIC_HI16 _b
18: 00 00 00 02 ADD D0Re0,D0Re0,#0
18: R_METAG_TLS_IENONPIC_LO16 _b
1c: 01 00 00 02 ADDT D0Re0,D0Re0,#0
1c: R_METAG_TLS_LE_HI16 _b
20: 00 00 00 02 ADD D0Re0,D0Re0,#0
20: R_METAG_TLS_LE_LO16 _b

10
gas/testsuite/gas/metag/tls.s Normal file
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.text
ADD D1Ar1,D1Ar1,#(_a@TLSGD)
ADD D1Ar1,D1Ar1,#(_b@TLSLDM)
ADDT D0Re0,D0Re0,#HI(_b@TLSLDO)
ADD D0Re0,D0Re0,#LO(_b@TLSLDO)
GETD D0.4,[A1LbP+#(_b@TLSIE)]
MOVT D0Re0,#HI(_b@TLSIENONPIC)
ADD D0Re0,D0Re0,#LO(_b@TLSIENONPIC)
ADDT D0Re0,D0Re0,#HI(_b@TLSLE)
ADD D0Re0,D0Re0,#LO(_b@TLSLE)

5
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.text
.global external
external:
nop

61
ld/testsuite/ld-metag/metag.exp Normal file
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# Expect script for ld-metag tests
#
# Copyright (C) 2013 Free Software Foundation, Inc.
# Contributed by Imagination Technologies Ltd.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
# MA 02110-1301, USA.
#
if {!([istarget "metag-*-*"]) } {
return
}
# Set up a list as described in ld-lib.exp
set metag_tests {
{"Meta pc-relative relocs linker test" "" ""
{ "pcrel.s" "external.s" }
{ {objdump -Dz pcrel.d} }
"pcrel"
}
{"Simple PIC shared library" "-shared" ""
{shared.s}
{ {objdump -fdw shared.d} {objdump -Rw shared.r} }
"shared.so"
}
{"Long branch stub" "" ""
{stub.s}
{ {objdump -fdw stub.d} }
"stub"
}
{"Shared library for stub tests" "-shared" ""
{stub_shared.s}
{ {objdump -fdw stub_shared.d} {objdump -Rw stub_shared.r} }
"stub_shared.so"
}
{"Long branch stub (PIC, app)" "tmpdir/stub_shared.so" ""
{stub_pic_app.s}
{ {objdump -fdw stub_pic_app.d} {objdump -Rw stub_pic_app.r} }
"stub_pic_app"
}
{"Long branch stub (PIC, shared)" "-shared" ""
{stub_pic_shared.s}
{ {objdump -fdw stub_pic_shared.d} }
"stub_pic_shared.so"
}
}
run_ld_link_tests $metag_tests

18
ld/testsuite/ld-metag/pcrel.d Normal file
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.*: file format elf32-metag
Disassembly of section .text:
.* <_start>:
.*: a8 00 00 ab CALLR D0Re0,10005068 <external>
.*: 48 00 00 ab CALLR D0Re0,10005060 <global>
.*: 48 00 00 ab CALLR D0Re0,10005064 <local>
.* <global>:
.*: fe ff ff a0 NOP
.* <local>:
.*: fe ff ff a0 NOP
.* <external>:
.*: fe ff ff a0 NOP

12
ld/testsuite/ld-metag/pcrel.s Normal file
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.text
.global _start
_start:
CALLR D0.0, external
CALLR D0.0, global
CALLR D0.0, local
.global global
global:
nop
local:
nop

41
ld/testsuite/ld-metag/shared.d Normal file
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tmpdir/shared.so: file format elf32-metag
architecture: metag, flags 0x00000150:
HAS_SYMS, DYNAMIC, D_PAGED
start address 0x.*
Disassembly of section .plt:
.* <.*>:
.*: 01 00 90 82 ADDT A0.2,CPC0,#0
.*: 60 08 12 82 ADD A0.2,A0.2,#0x410c
.*: 20 0c 10 a3 MOV D0Re0,A0.2
.*: e3 01 00 b7 SETL \[A0StP\+\+\],D0Re0,D1Re0
.*: 2a 01 00 c6 GETD PC,\[D0Re0\+#4\]
.* <app_func2@plt>:
.*: 01 00 90 82 ADDT A0.2,CPC0,#0
.*: 80 07 12 82 ADD A0.2,A0.2,#0x40f0
.*: 6a 80 00 c6 GETD PC,\[A0.2\]
.*: 04 00 00 03 MOV D1Re0,#0
.*: e0 fe ff a0 B 184 <app_func2@plt-0x14>
Disassembly of section .text:
.* <lib_func1>:
.*: 05 32 20 00 MOV D0FrT,A0FrP
.*: 26 00 08 86 ADD A0FrP,A0StP,#0
.*: e3 01 20 b7 SETL \[A0StP\+\+\],D0FrT,D1RtP
.*: e9 02 08 b6 SETD \[A0StP\+#8\+\+\],A1LbP
.*: 40 00 00 82 ADD A0StP,A0StP,#0x8
.*: 01 00 88 83 ADDT A1LbP,CPC1,#0
.*: 60 06 0b 83 ADD A1LbP,A1LbP,#0x60cc
.*: 94 fe ff ab CALLR D1RtP,198 <app_func2@plt>
.*: 8d 01 0c a7 GETD D0Ar6,\[A1LbP\+#-8180\]
.*: 00 02 00 00 ADD D0Re0,D0Re0,D0Ar6
.*: 05 02 00 01 MOV D1Re0,A1LbP
.*: f9 ff 07 03 ADDT D1Re0,D1Re0,#0xffff
.*: c0 ff 06 03 ADD D1Re0,D1Re0,#0xdff8
.*: 64 fe 0f a7 GETD A1LbP,\[A0StP\+#-16\]
.*: e3 41 20 c7 GETL D0FrT,D1RtP,\[A0FrP\+\+\]
.*: 26 42 00 8e SUB A0StP,A0FrP,#0x8
.*: 05 18 08 80 MOV A0FrP,D0FrT
.*: a0 08 20 a3 MOV PC,D1RtP

9
ld/testsuite/ld-metag/shared.r Normal file
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tmpdir/shared.so: file format elf32-metag
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
.* R_METAG_GLOB_DAT _var1
.* R_METAG_JMP_SLOT app_func2

28
ld/testsuite/ld-metag/shared.s Normal file
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.text
.global lib_func1
.type lib_func1,function
lib_func1:
MOV D0FrT,A0FrP
ADD A0FrP,A0StP,#0
SETL [A0StP+#8++],D0.4,D1RtP
SETD [A0StP+#8++],A1LbP
ADD A0StP,A0StP,#8
ADDT A1LbP,CPC1,#HI(__GLOBAL_OFFSET_TABLE__)
ADD A1LbP,A1LbP,#LO(__GLOBAL_OFFSET_TABLE__+4)
CALLR D1RtP,app_func2@PLT
GETD D0Ar6,[A1LbP+#(_var1@GOT)]
ADD D0Re0,D0Re0,D0Ar6
MOV D1Re0,A1LbP
ADDT D1Re0,D1Re0,#HI(_local_var1@GOTOFF)
ADD D1Re0,D1Re0,#LO(_local_var1@GOTOFF)
GETD A1LbP,[A0StP+#(-(8+8))]
GETL D0.4,D1RtP,[A0FrP+#8++]
SUB A0StP,A0FrP,#(8)
MOV A0FrP,D0.4
MOV PC,D1RtP
.size lib_func1,.-lib_func1
.data
_local_var1:
.long 0

14
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@ -0,0 +1,14 @@
tmpdir/stub: file format elf32-metag
architecture: metag, flags 0x00000112:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x.*
Disassembly of section .text:
.* <__start-0x8>:
.*: 05 81 18 82 MOVT A0.3,#0x1020
.*: 03 83 1a ac JUMP A0.3,#0x5060
.* <__start>:
.*: d4 ff ff ab CALLR D1RtP,.* <__start-0x8>
\.\.\.
.* <_far>:
.*: fe ff ff a0 NOP

13
ld/testsuite/ld-metag/stub.s Normal file
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.text
.global __start
__start:
CALLR D1RtP,_far
.section .text.pad,"ax"
.space 0x200000
.section .text.far,"ax"
.global _far
_far:
NOP

34
ld/testsuite/ld-metag/stub_pic_app.d Normal file
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@ -0,0 +1,34 @@
tmpdir/stub_pic_app: file format elf32-metag
architecture: metag, flags 0x00000112:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x.*
Disassembly of section .plt:
.* <.*>:
.*: 05 81 00 02 MOVT D0Re0,#0x1020
.*: 20 97 04 02 ADD D0Re0,D0Re0,#0x92e4
.*: e3 01 00 b7 SETL \[A0StP\+\+\],D0Re0,D1Re0
.*: 2a 01 00 c6 GETD PC,\[D0Re0\+#4\]
.*: fe ff ff a0 NOP
.* <_lib_func@plt>:
.*: 05 81 10 82 MOVT A0.2,#0x1020
.*: e0 96 14 82 ADD A0.2,A0.2,#0x92dc
.*: 6a 80 00 c6 GETD PC,\[A0.2\]
.*: 04 00 00 03 MOV D1Re0,#0
.*: e0 fe ff a0 B .* <_lib_func@plt-0x14>
Disassembly of section .text:
.* <__start-0x10>:
.*: 05 81 18 82 MOVT A0.3,#0x1020
.*: a3 91 1a ac JUMP A0.3,#0x5234
.*: 05 81 18 82 MOVT A0.3,#0x1020
.*: 83 91 1a ac JUMP A0.3,#0x5230
.* <__start>:
.*: 94 ff ff ab CALLR D1RtP,.* <_lib_func@plt\+0x14>
.*: d4 fe ff ab CALLR D1RtP,.* <_lib_func@plt>
.*: 94 ff ff ab CALLR D1RtP,.* <_lib_func@plt\+0x1c>
\.\.\.
.* <_far2>:
.*: fe ff ff a0 NOP
.* <_far>:
.*: f4 ff ff ab CALLR D1RtP,.* <_far2>

9
ld/testsuite/ld-metag/stub_pic_app.r Normal file
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@ -0,0 +1,9 @@
tmpdir/stub_pic_app: file format elf32-metag
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
.* R_METAG_ADDR32 _lib_data
.* R_METAG_JMP_SLOT _lib_func

25
ld/testsuite/ld-metag/stub_pic_app.s Normal file
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@ -0,0 +1,25 @@
.text
.global __start
__start:
CALLR D1RtP,_far
CALLR D1RtP,_lib_func
CALLR D1RtP,_far2
.section .text.pad,"ax"
.space 0x200000
.global pad_end
pad_end:
.section .text.far,"ax"
.global _far2
_far2:
NOP
_far:
CALLR D1RtP,_far2@PLT
.data
.balign 4
.type _app_data,@object
.size _app_data,4
_app_data:
.long _lib_data

35
ld/testsuite/ld-metag/stub_pic_shared.d Normal file
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tmpdir/stub_pic_shared.so: file format elf32-metag
architecture: metag, flags 0x00000150:
HAS_SYMS, DYNAMIC, D_PAGED
start address 0x.*
Disassembly of section .plt:
.* <.*>:
.*: 01 01 90 82 ADDT A0.2,CPC0,#0x20
.*: 60 06 12 82 ADD A0.2,A0.2,#0x40cc
.*: 20 0c 10 a3 MOV D0Re0,A0.2
.*: e3 01 00 b7 SETL \[A0StP\+\+\],D0Re0,D1Re0
.*: 2a 01 00 c6 GETD PC,\[D0Re0\+#4\]
.* <_far2@plt>:
.*: 01 01 90 82 ADDT A0.2,CPC0,#0x20
.*: 80 05 12 82 ADD A0.2,A0.2,#0x40b0
.*: 6a 80 00 c6 GETD PC,\[A0.2\]
.*: 04 00 00 03 MOV D1Re0,#0
.*: e0 fe ff a0 B .* <_far2@plt-0x14>
Disassembly of section .text:
.* <__start-0xc>:
.*: 01 01 98 82 ADDT A0.3,CPC0,#0x20
.*: 00 01 18 82 ADD A0.3,A0.3,#0x20
.*: a0 0c 18 a3 MOV PC,A0.3
.* <__start>:
.*: b4 ff ff ab CALLR D1RtP,.* <_far2@plt\+0x14>
\.\.\.
.* <pad_end>:
.*: f9 fe 9f 82 ADDT A0.3,CPC0,#0xffdf
.*: e0 fe 1f 82 ADD A0.3,A0.3,#0xffdc
.*: a0 0c 18 a3 MOV PC,A0.3
.* <_far2>:
.*: fe ff ff a0 NOP
.* <_far>:
.*: 94 ff ff ab CALLR D1RtP,.* <pad_end>

17
ld/testsuite/ld-metag/stub_pic_shared.s Normal file
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.text
.global __start
__start:
CALLR D1RtP,_far
.section .text.pad,"ax"
.space 0x200000
.global pad_end
pad_end:
.section .text.far,"ax"
.global _far2
_far2:
NOP
_far:
CALLR D1RtP,_far2@PLT

36
ld/testsuite/ld-metag/stub_shared.d Normal file
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tmpdir/stub_shared.so: file format elf32-metag
architecture: metag, flags 0x00000150:
HAS_SYMS, DYNAMIC, D_PAGED
start address 0x.*
Disassembly of section .plt:
.* <.*>:
.*: 01 00 90 82 ADDT A0.2,CPC0,#0
.*: 00 07 12 82 ADD A0.2,A0.2,#0x40e0
.*: 20 0c 10 a3 MOV D0Re0,A0.2
.*: e3 01 00 b7 SETL \[A0StP\+\+\],D0Re0,D1Re0
.*: 2a 01 00 c6 GETD PC,\[D0Re0\+#4\]
.* <_far2@plt>:
.*: 01 00 90 82 ADDT A0.2,CPC0,#0
.*: 20 06 12 82 ADD A0.2,A0.2,#0x40c4
.*: 6a 80 00 c6 GETD PC,\[A0.2\]
.*: 04 00 00 03 MOV D1Re0,#0
.*: e0 fe ff a0 B .* <_far2@plt-0x14>
Disassembly of section .text:
.* <_lib_func>:
.*: 05 32 20 00 MOV D0FrT,A0FrP
.*: 26 00 08 86 ADD A0FrP,A0StP,#0
.*: e3 01 20 b7 SETL \[A0StP\+\+\],D0FrT,D1RtP
.*: e9 02 08 b6 SETD \[A0StP\+#8\+\+\],A1LbP
.*: 40 00 00 82 ADD A0StP,A0StP,#0x8
.*: 01 00 88 83 ADDT A1LbP,CPC1,#0
.*: 00 05 0b 83 ADD A1LbP,A1LbP,#0x60a0
.*: 94 fe ff ab CALLR D1RtP,.* <_far2@plt>
.*: 64 fe 0f a7 GETD A1LbP,\[A0StP\+#-16\]
.*: e3 41 20 c7 GETL D0FrT,D1RtP,\[A0FrP\+\+\]
.*: 26 42 00 8e SUB A0StP,A0FrP,#0x8
.*: 05 18 08 80 MOV A0FrP,D0FrT
.*: a0 08 20 a3 MOV PC,D1RtP

8
ld/testsuite/ld-metag/stub_shared.r Normal file
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@ -0,0 +1,8 @@
tmpdir/stub_shared.so: file format elf32-metag
DYNAMIC RELOCATION RECORDS
OFFSET TYPE VALUE
.* R_METAG_JMP_SLOT _far2

26
ld/testsuite/ld-metag/stub_shared.s Normal file
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.text
.global _lib_func
.type _lib_func,function
_lib_func:
MOV D0FrT,A0FrP
ADD A0FrP,A0StP,#0
SETL [A0StP+#8++],D0.4,D1RtP
SETD [A0StP+#8++],A1LbP
ADD A0StP,A0StP,#8
ADDT A1LbP,CPC1,#HI(__GLOBAL_OFFSET_TABLE__)
ADD A1LbP,A1LbP,#LO(__GLOBAL_OFFSET_TABLE__+4)
CALLR D1RtP,_far2@PLT
GETD A1LbP,[A0StP+#(-(8+8))]
GETL D0.4,D1RtP,[A0FrP+#8++]
SUB A0StP,A0FrP,#(8)
MOV A0FrP,D0.4
MOV PC,D1RtP
.size _lib_func,.-_lib_func
.data
.balign 4
.type _lib_data,@object
.size _lib_data,4
.global _lib_data
_lib_data:
.long 0