sim: cr16: push down sd/cpu vars
By itself, this commit doesn't really change anything. It lays the groundwork for using the cpu state in follow up commits, both for engine state and for cpu state. Splitting things up this way so it is easier to see how things have changed.
This commit is contained in:
Mike Frysinger
parent
137fbfd281
commit
267b3b8e06
@ -1,3 +1,28 @@
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2015-11-15 Mike Frysinger <vapier@gentoo.org>
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* cr16_sim.h (struct simops): Add SIM_DESC and SIM_CPU to func args.
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(SET_CREG, SET_HW_CREG, SET_PSR_BIT): Pass sd and cpu to move_to_cr.
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(dmem_addr, imem_addr, move_to_cr): Add SIM_DESC and SIM_CPU args.
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(RB, SW, RW, SLW, RLW): Pass sd and cpu to dmem_addr.
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* endian.c: Change cr16_sim.h include to sim-main.h.
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* gencode.c: Likewise. Add SIM_DESC and SIM_CPU args to all OPs.
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* interp.c (lookup_hash, map_memory, do_run, dmap_register,
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imap_register, sim_cr16_translate_dmap_addr, xfer_mem,
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sim_cr16_translate_imap_addr, sim_cr16_translate_addr): Add
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SIM_DESC and SIM_CPU args and adjust all callers.
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(trace_sd): Delete.
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(sim_open): Do not assign trace_sd.
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(sim_resume, sim_create_inferior): Set up cpu from the first one
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in sd.
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(cr16_reg_store): Get sim state from cpu.
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* simops.c (move_to_cr): Add SIM_DESC and SIM_CPU args.
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(trace_input_func, trace_input, do_trace_output_finish,
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do_trace_output_finish, trace_output_40, trace_output_32,
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trace_output_16, trace_output_void, trace_output_flag): Add
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SIM_DESC arg.
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(trace_input_func): Likewise. Change trace_sd to sd.
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(OP_*): Add SIM_DESC and SIM_CPU args to all OP funcs.
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2015-11-15 Mike Frysinger <vapier@gentoo.org>
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* cr16_sim.h (get_longlong, write_longlong, WRITE_16, READ_64,
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@ -66,7 +66,7 @@ struct simops
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uint32 opcode;
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int format;
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char fname[12];
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void (*func)();
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void (*func)(SIM_DESC, SIM_CPU *);
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int numops;
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operand_desc operands[4];
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};
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@ -251,8 +251,8 @@ struct _state
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creg_t cregs[16]; /* control registers */
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#define CREG(N) (State.cregs[(N)] + 0)
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#define SET_CREG(N,VAL) move_to_cr ((N), 0, (VAL), 0)
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#define SET_HW_CREG(N,VAL) move_to_cr ((N), 0, (VAL), 1)
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#define SET_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 0)
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#define SET_HW_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 1)
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reg_t sp[2]; /* holding area for SPI(0)/SPU(1) */
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#define HELD_SP(N) (State.sp[(N)] + 0)
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@ -318,7 +318,7 @@ enum
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#define PSR CREG (PSR_CR)
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#define SET_PSR(VAL) SET_CREG (PSR_CR, (VAL))
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#define SET_HW_PSR(VAL) SET_HW_CREG (PSR_CR, (VAL))
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#define SET_PSR_BIT(MASK,VAL) move_to_cr (PSR_CR, ~((creg_t) MASK), (VAL) ? (MASK) : 0, 1)
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#define SET_PSR_BIT(MASK,VAL) move_to_cr (sd, cpu, PSR_CR, ~((creg_t) MASK), (VAL) ? (MASK) : 0, 1)
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#define PSR_SM ((PSR & PSR_SM_BIT) != 0)
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#define SET_PSR_SM(VAL) SET_PSR_BIT (PSR_SM_BIT, (VAL))
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@ -421,11 +421,11 @@ enum
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/* sign-extend a 32-bit number */
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#define SEXT32(x) ((((x)&0xffffffff)^(~0x7fffffff))+0x80000000)
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extern uint8 *dmem_addr (uint32 offset);
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extern uint8 *imem_addr (uint32);
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extern uint8 *dmem_addr (SIM_DESC, SIM_CPU *, uint32 offset);
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extern uint8 *imem_addr (SIM_DESC, SIM_CPU *, uint32);
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extern bfd_vma decode_pc (void);
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#define RB(x) (*(dmem_addr(x)))
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#define RB(x) (*(dmem_addr (sd, cpu, x)))
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#define SB(addr,data) ( RB(addr) = (data & 0xff))
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#if defined(__GNUC__) && defined(__OPTIMIZE__) && !defined(NO_ENDIAN_INLINE)
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@ -440,10 +440,10 @@ extern void write_word (uint8 *addr, uint16 data);
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extern void write_longword (uint8 *addr, uint32 data);
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#endif
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#define SW(addr,data) write_word(dmem_addr(addr),data)
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#define RW(x) get_word(dmem_addr(x))
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#define SLW(addr,data) write_longword(dmem_addr(addr),data)
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#define RLW(x) get_longword(dmem_addr(x))
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#define SW(addr,data) write_word (dmem_addr (sd, cpu, addr), data)
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#define RW(x) get_word (dmem_addr (sd, cpu, x))
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#define SLW(addr,data) write_longword (dmem_addr (sd, cpu, addr), data)
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#define RLW(x) get_longword (dmem_addr (sd, cpu, x))
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#define READ_16(x) get_word(x)
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#define JMP(x) do { SET_PC (x); State.pc_changed = 1; } while (0)
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@ -467,7 +467,7 @@ extern void write_longword (uint8 *addr, uint32 data);
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(VAL & ~MASK)). In addition, unless PSR_HW_P, a VAL intended for
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PSR is masked for zero bits. */
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extern creg_t move_to_cr (int cr, creg_t mask, creg_t val, int psw_hw_p);
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extern creg_t move_to_cr (SIM_DESC, SIM_CPU *, int cr, creg_t mask, creg_t val, int psw_hw_p);
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#ifndef SIGTRAP
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#define SIGTRAP 5
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@ -23,7 +23,7 @@
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#ifndef ENDIAN_INLINE
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#define NO_ENDIAN_INLINE
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#include "cr16_sim.h"
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#include "sim-main.h"
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#define ENDIAN_INLINE
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#endif
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@ -53,8 +53,9 @@ write_header (void)
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/* Loop over instruction table until a full match is found. */
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for ( ; i < NUMOPCODES; i++)
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printf("void OP_%lX_%X (void);\t\t/* %s */\n", cr16_instruction[i].match,
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(32 - cr16_instruction[i].match_bits), cr16_instruction[i].mnemonic);
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printf("void OP_%lX_%X (SIM_DESC, SIM_CPU *);\t\t/* %s */\n",
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cr16_instruction[i].match, (32 - cr16_instruction[i].match_bits),
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cr16_instruction[i].mnemonic);
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}
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@ -66,15 +67,16 @@ write_template (void)
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{
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int i = 0,j, k, flags;
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printf ("#include \"cr16_sim.h\"\n");
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printf ("#include \"sim-main.h\"\n");
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printf ("#include \"simops.h\"\n\n");
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for ( ; i < NUMOPCODES; i++)
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{
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if (cr16_instruction[i].size != 0)
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{
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printf("/* %s */\nvoid\nOP_%lX_%X ()\n{\n", cr16_instruction[i].mnemonic,
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cr16_instruction[i].match, (32 - cr16_instruction[i].match_bits));
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printf ("/* %s */\nvoid\nOP_%lX_%X (SIM_DESC sd, SIM_CPU *cpu)\n{\n",
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cr16_instruction[i].mnemonic, cr16_instruction[i].match,
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(32 - cr16_instruction[i].match_bits));
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/* count operands. */
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j = 0;
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@ -129,7 +131,7 @@ write_opcodes (void)
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int i = 0, j = 0, k;
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/* write out opcode table. */
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printf ("#include \"cr16_sim.h\"\n");
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printf ("#include \"sim-main.h\"\n");
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printf ("#include \"simops.h\"\n\n");
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printf ("struct simops Simops[] = {\n");
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@ -40,9 +40,9 @@ host_callback *cr16_callback;
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uint32 OP[4];
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uint32 sign_flag;
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static struct hash_entry *lookup_hash (uint64 ins, int size);
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static struct hash_entry *lookup_hash (SIM_DESC, SIM_CPU *, uint64 ins, int size);
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static void get_operands (operand_desc *s, uint64 mcode, int isize, int nops);
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static INLINE uint8 *map_memory (unsigned phys_addr);
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static INLINE uint8 *map_memory (SIM_DESC, SIM_CPU *, unsigned phys_addr);
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#define MAX_HASH 16
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@ -73,7 +73,7 @@ hash(unsigned long long insn, int format)
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INLINE static struct hash_entry *
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lookup_hash (uint64 ins, int size)
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lookup_hash (SIM_DESC sd, SIM_CPU *cpu, uint64 ins, int size)
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{
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uint32 mask;
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struct hash_entry *h;
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@ -329,7 +329,7 @@ get_operands (operand_desc *s, uint64 ins, int isize, int nops)
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}
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static int
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do_run (SIM_DESC sd, uint64 mcode)
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do_run (SIM_DESC sd, SIM_CPU *cpu, uint64 mcode)
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{
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host_callback *cr16_callback = STATE_CALLBACK (sd);
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struct simops *s= Simops;
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@ -340,15 +340,15 @@ do_run (SIM_DESC sd, uint64 mcode)
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if ((cr16_debug & DEBUG_INSTRUCTION) != 0)
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(*cr16_callback->printf_filtered) (cr16_callback, "do_long 0x%x\n", mcode);
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#endif
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h = lookup_hash(mcode, 1);
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h = lookup_hash (sd, cpu, mcode, 1);
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if ((h == NULL) || (h->opcode == 0))
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return 0;
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if (h->size == 3)
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{
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iaddr = imem_addr ((uint32)PC + 2);
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iaddr = imem_addr (sd, cpu, (uint32)PC + 2);
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mcode = (mcode << 16) | get_longword( iaddr );
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}
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@ -365,7 +365,7 @@ do_run (SIM_DESC sd, uint64 mcode)
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//State.ins_type = h->flags;
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(h->ops->func)();
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(h->ops->func) (sd, cpu);
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return h->size;
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}
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@ -408,17 +408,17 @@ enum
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};
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static unsigned long
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dmap_register (void *regcache, int reg_nr)
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dmap_register (SIM_DESC sd, SIM_CPU *cpu, void *regcache, int reg_nr)
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{
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uint8 *raw = map_memory (SIM_CR16_MEMORY_DATA
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uint8 *raw = map_memory (sd, cpu, SIM_CR16_MEMORY_DATA
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+ DMAP0_OFFSET + 2 * reg_nr);
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return READ_16 (raw);
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}
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static unsigned long
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imap_register (void *regcache, int reg_nr)
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imap_register (SIM_DESC sd, SIM_CPU *cpu, void *regcache, int reg_nr)
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{
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uint8 *raw = map_memory (SIM_CR16_MEMORY_DATA
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uint8 *raw = map_memory (sd, cpu, SIM_CR16_MEMORY_DATA
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+ IMAP0_OFFSET + 2 * reg_nr);
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return READ_16 (raw);
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}
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@ -427,11 +427,15 @@ imap_register (void *regcache, int reg_nr)
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into a physical address. */
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static unsigned long
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sim_cr16_translate_dmap_addr (unsigned long offset,
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sim_cr16_translate_dmap_addr (SIM_DESC sd,
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SIM_CPU *cpu,
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unsigned long offset,
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int nr_bytes,
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unsigned long *phys,
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void *regcache,
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unsigned long (*dmap_register) (void *regcache,
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unsigned long (*dmap_register) (SIM_DESC,
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SIM_CPU *,
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void *regcache,
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int reg_nr))
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{
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short map;
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@ -451,7 +455,7 @@ sim_cr16_translate_dmap_addr (unsigned long offset,
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/* Don't cross a BLOCK boundary */
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nr_bytes = DMAP_BLOCK_SIZE - (offset % DMAP_BLOCK_SIZE);
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}
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map = dmap_register (regcache, regno);
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map = dmap_register (sd, cpu, regcache, regno);
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if (regno == 3)
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{
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/* Always maps to data memory */
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@ -490,11 +494,15 @@ sim_cr16_translate_dmap_addr (unsigned long offset,
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into a physical address. */
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static unsigned long
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sim_cr16_translate_imap_addr (unsigned long offset,
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sim_cr16_translate_imap_addr (SIM_DESC sd,
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SIM_CPU *cpu,
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unsigned long offset,
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int nr_bytes,
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unsigned long *phys,
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void *regcache,
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unsigned long (*imap_register) (void *regcache,
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unsigned long (*imap_register) (SIM_DESC,
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SIM_CPU *,
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void *regcache,
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int reg_nr))
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{
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short map;
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@ -514,7 +522,7 @@ sim_cr16_translate_imap_addr (unsigned long offset,
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/* Don't cross a BLOCK boundary */
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nr_bytes = IMAP_BLOCK_SIZE - offset;
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}
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map = imap_register (regcache, regno);
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map = imap_register (sd, cpu, regcache, regno);
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sp = (map & 0x3000) >> 12;
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segno = (map & 0x007f);
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switch (sp)
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@ -543,12 +551,20 @@ sim_cr16_translate_imap_addr (unsigned long offset,
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}
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static unsigned long
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sim_cr16_translate_addr (unsigned long memaddr, int nr_bytes,
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unsigned long *targ_addr, void *regcache,
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unsigned long (*dmap_register) (void *regcache,
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int reg_nr),
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unsigned long (*imap_register) (void *regcache,
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int reg_nr))
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sim_cr16_translate_addr (SIM_DESC sd,
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SIM_CPU *cpu,
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unsigned long memaddr,
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int nr_bytes,
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unsigned long *targ_addr,
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void *regcache,
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unsigned long (*dmap_register) (SIM_DESC,
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SIM_CPU *,
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void *regcache,
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int reg_nr),
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unsigned long (*imap_register) (SIM_DESC,
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SIM_CPU *,
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void *regcache,
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int reg_nr))
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{
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unsigned long phys;
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unsigned long seg;
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@ -587,13 +603,13 @@ sim_cr16_translate_addr (unsigned long memaddr, int nr_bytes,
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break;
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case 0x10: /* in logical data address segment */
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nr_bytes = sim_cr16_translate_dmap_addr (off, nr_bytes, &phys, regcache,
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dmap_register);
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nr_bytes = sim_cr16_translate_dmap_addr (sd, cpu, off, nr_bytes, &phys,
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regcache, dmap_register);
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break;
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case 0x11: /* in logical instruction address segment */
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nr_bytes = sim_cr16_translate_imap_addr (off, nr_bytes, &phys, regcache,
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imap_register);
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nr_bytes = sim_cr16_translate_imap_addr (sd, cpu, off, nr_bytes, &phys,
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regcache, imap_register);
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break;
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default:
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@ -609,7 +625,7 @@ sim_cr16_translate_addr (unsigned long memaddr, int nr_bytes,
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isn't going to cross a segment boundary. */
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uint8 *
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map_memory (unsigned phys_addr)
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map_memory (SIM_DESC sd, SIM_CPU *cpu, unsigned phys_addr)
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{
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uint8 **memory;
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uint8 *raw;
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@ -690,12 +706,12 @@ xfer_mem (SIM_DESC sd, SIM_ADDR virt,
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uint8 *memory;
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unsigned long phys;
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int phys_size;
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phys_size = sim_cr16_translate_addr (virt, size, &phys, NULL,
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phys_size = sim_cr16_translate_addr (sd, NULL, virt, size, &phys, NULL,
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dmap_register, imap_register);
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if (phys_size == 0)
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return 0;
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memory = map_memory (phys);
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memory = map_memory (sd, NULL, phys);
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#ifdef DEBUG
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if ((cr16_debug & DEBUG_INSTRUCTION) != 0)
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@ -746,6 +762,7 @@ cr16_pc_get (sim_cpu *cpu)
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static void
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cr16_pc_set (sim_cpu *cpu, sim_cia pc)
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{
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SIM_DESC sd = CPU_STATE (cpu);
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SET_PC (pc);
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}
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@ -761,8 +778,6 @@ free_state (SIM_DESC sd)
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static int cr16_reg_fetch (SIM_CPU *, int, unsigned char *, int);
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static int cr16_reg_store (SIM_CPU *, int, unsigned char *, int);
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SIM_DESC trace_sd = NULL;
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SIM_DESC
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sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *cb, struct bfd *abfd, char **argv)
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{
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@ -833,7 +848,6 @@ sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *cb, struct bfd *abfd,
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CPU_PC_STORE (cpu) = cr16_pc_set;
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}
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trace_sd = sd;
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cr16_callback = cb;
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/* put all the opcodes in the hash table. */
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@ -950,7 +964,7 @@ sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *cb, struct bfd *abfd,
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}
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uint8 *
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dmem_addr (uint32 offset)
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dmem_addr (SIM_DESC sd, SIM_CPU *cpu, uint32 offset)
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{
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unsigned long phys;
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uint8 *mem;
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@ -960,14 +974,14 @@ dmem_addr (uint32 offset)
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things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type
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is uint16 this is modulo'ed onto 0x0e5d. */
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phys_size = sim_cr16_translate_dmap_addr (offset, 1, &phys, NULL,
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phys_size = sim_cr16_translate_dmap_addr (sd, cpu, offset, 1, &phys, NULL,
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dmap_register);
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if (phys_size == 0)
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{
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mem = State.mem.fault;
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}
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else
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mem = map_memory (phys);
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mem = map_memory (sd, cpu, phys);
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#ifdef DEBUG
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if ((cr16_debug & DEBUG_MEMORY))
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{
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@ -983,17 +997,17 @@ dmem_addr (uint32 offset)
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}
|
||||
|
||||
uint8 *
|
||||
imem_addr (uint32 offset)
|
||||
imem_addr (SIM_DESC sd, SIM_CPU *cpu, uint32 offset)
|
||||
{
|
||||
unsigned long phys;
|
||||
uint8 *mem;
|
||||
int phys_size = sim_cr16_translate_imap_addr (offset, 1, &phys, NULL,
|
||||
int phys_size = sim_cr16_translate_imap_addr (sd, cpu, offset, 1, &phys, NULL,
|
||||
imap_register);
|
||||
if (phys_size == 0)
|
||||
{
|
||||
return State.mem.fault;
|
||||
}
|
||||
mem = map_memory (phys);
|
||||
mem = map_memory (sd, cpu, phys);
|
||||
#ifdef DEBUG
|
||||
if ((cr16_debug & DEBUG_MEMORY))
|
||||
{
|
||||
@ -1022,6 +1036,7 @@ sim_stop (SIM_DESC sd)
|
||||
void
|
||||
sim_resume (SIM_DESC sd, int step, int siggnal)
|
||||
{
|
||||
SIM_CPU *cpu = STATE_CPU (sd, 0);
|
||||
uint32 curr_ins_size = 0;
|
||||
uint64 mcode = 0;
|
||||
uint8 *iaddr;
|
||||
@ -1061,7 +1076,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
|
||||
|
||||
do
|
||||
{
|
||||
iaddr = imem_addr ((uint32)PC);
|
||||
iaddr = imem_addr (sd, cpu, (uint32)PC);
|
||||
if (iaddr == State.mem.fault)
|
||||
{
|
||||
#ifdef SIGBUS
|
||||
@ -1076,7 +1091,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
|
||||
|
||||
State.pc_changed = 0;
|
||||
|
||||
curr_ins_size = do_run(sd, mcode);
|
||||
curr_ins_size = do_run (sd, cpu, mcode);
|
||||
|
||||
#if CR16_DEBUG
|
||||
(*cr16_callback->printf_filtered) (cr16_callback, "INS: PC=0x%X, mcode=0x%X\n",PC,mcode);
|
||||
@ -1138,7 +1153,10 @@ sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env)
|
||||
if (cr16_debug)
|
||||
(*cr16_callback->printf_filtered) (cr16_callback, "sim_create_inferior: PC=0x%lx\n", (long) start_address);
|
||||
#endif
|
||||
SET_CREG (PC_CR, start_address);
|
||||
{
|
||||
SIM_CPU *cpu = STATE_CPU (sd, 0);
|
||||
SET_CREG (PC_CR, start_address);
|
||||
}
|
||||
|
||||
SLOT_FLUSH ();
|
||||
return SIM_RC_OK;
|
||||
@ -1265,6 +1283,7 @@ cr16_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
|
||||
static int
|
||||
cr16_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
|
||||
{
|
||||
SIM_DESC sd = CPU_STATE (cpu);
|
||||
int size;
|
||||
switch ((enum sim_cr16_regs) rn)
|
||||
{
|
||||
|
||||
1451
sim/cr16/simops.c
1451
sim/cr16/simops.c
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user