sim: mips: delete mmu stubs to move to common sim_{read,write}
The only unique thing about mip's sim_{read,write} helpers is the call to
address_translation on the incoming address. When we look closer at that
function though, we see it's just a stub that maps physical to virtual,
and the cache/return values are hardcoded. If we delete this function,
we can then collapse all the callers and drop the custom sim_{read,write}
logic entirely.
Some day we might want to add MMU support, but when we do, we'll want to
have the common layers handle things so all targets benefit.
This commit is contained in:
Mike Frysinger
parent
8b494522f9
commit
26f8bf63bf
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@ -1,3 +1,22 @@
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2015-12-26 Mike Frysinger <vapier@gentoo.org>
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* interp.c (sim_write, sim_read): Delete.
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(store_word): Delete call to AddressTranslation and set paddr=vaddr.
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(load_word): Likewise.
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* micromips.igen (cache): Likewise.
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* mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
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do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
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do_store_left, do_store_right, do_load_double, do_store_double):
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Likewise.
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(do_pref): Delete call to AddressTranslation and stub out Prefetch.
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(do_prefx): Likewise.
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* sim-main.c (address_translation, prefetch): Delete.
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(ifetch32, ifetch16): Delete call to AddressTranslation and set
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paddr=vaddr.
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* sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
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address_translation, AddressTranslation, prefetch, Prefetch): Delete.
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(LoadMemory, StoreMemory): Delete CCA arg.
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2015-12-24 Mike Frysinger <vapier@gentoo.org>
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* configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
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@ -840,59 +840,6 @@ mips_sim_close (SIM_DESC sd, int quitting)
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#endif
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}
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int
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sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
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{
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int index;
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sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
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/* Return the number of bytes written, or zero if error. */
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#ifdef DEBUG
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sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
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#endif
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/* We use raw read and write routines, since we do not want to count
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the GDB memory accesses in our statistics gathering. */
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for (index = 0; index < size; index++)
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{
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address_word vaddr = (address_word)addr + index;
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address_word paddr;
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int cca;
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if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
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break;
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if (sim_core_write_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
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break;
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}
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return(index);
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}
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int
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sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
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{
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int index;
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sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
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/* Return the number of bytes read, or zero if error. */
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#ifdef DEBUG
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sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
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#endif /* DEBUG */
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for (index = 0; (index < size); index++)
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{
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address_word vaddr = (address_word)addr + index;
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address_word paddr;
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int cca;
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if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
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break;
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if (sim_core_read_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
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break;
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}
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return(index);
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}
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int
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sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
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{
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@ -1491,26 +1438,21 @@ store_word (SIM_DESC sd,
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uword64 vaddr,
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signed_word val)
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{
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address_word paddr;
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int uncached;
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address_word paddr = vaddr;
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if ((vaddr & 3) != 0)
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SignalExceptionAddressStore ();
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else
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{
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if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
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isTARGET, isREAL))
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{
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const uword64 mask = 7;
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uword64 memval;
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unsigned int byte;
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const uword64 mask = 7;
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uword64 memval;
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unsigned int byte;
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paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
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byte = (vaddr & mask) ^ (BigEndianCPU << 2);
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memval = ((uword64) val) << (8 * byte);
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StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
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isREAL);
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}
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paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
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byte = (vaddr & mask) ^ (BigEndianCPU << 2);
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memval = ((uword64) val) << (8 * byte);
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StoreMemory (AccessLength_WORD, memval, 0, paddr, vaddr,
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isREAL);
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}
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}
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@ -1528,24 +1470,18 @@ load_word (SIM_DESC sd,
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}
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else
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{
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address_word paddr;
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int uncached;
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address_word paddr = vaddr;
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const uword64 mask = 0x7;
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const unsigned int reverse = ReverseEndian ? 1 : 0;
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const unsigned int bigend = BigEndianCPU ? 1 : 0;
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uword64 memval;
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unsigned int byte;
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if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
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isTARGET, isREAL))
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{
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const uword64 mask = 0x7;
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const unsigned int reverse = ReverseEndian ? 1 : 0;
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const unsigned int bigend = BigEndianCPU ? 1 : 0;
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uword64 memval;
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unsigned int byte;
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paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
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LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
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isDATA, isREAL);
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byte = (vaddr & mask) ^ (bigend << 2);
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return EXTEND32 (memval >> (8 * byte));
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}
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paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
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LoadMemory (&memval, NULL, AccessLength_WORD, paddr, vaddr, isDATA,
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isREAL);
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byte = (vaddr & mask) ^ (bigend << 2);
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return EXTEND32 (memval >> (8 * byte));
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}
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return 0;
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@ -845,11 +845,8 @@
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address_word base = GPR[BASE];
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address_word offset = EXTEND12 (IMMEDIATE);
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address_word vaddr = loadstore_ea (SD_, base, offset);
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address_word paddr;
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int uncached;
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if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
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isTARGET, isREAL))
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CacheOp (OP, vaddr, paddr, instruction_0);
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address_word paddr = vaddr;
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CacheOp (OP, vaddr, paddr, instruction_0);
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}
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@ -782,8 +782,7 @@
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address_word offset = EXTEND16 (insn_offset);
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{
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address_word vaddr = loadstore_ea (SD_, base, offset);
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address_word paddr;
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int uncached;
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address_word paddr = vaddr;
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if ((vaddr & 3) != 0)
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{
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SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer,
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@ -791,23 +790,19 @@
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}
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else
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{
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if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
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isTARGET, isREAL))
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{
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unsigned64 memval = 0;
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unsigned64 memval1 = 0;
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unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
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unsigned int shift = 2;
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unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
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unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
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unsigned int byte;
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paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
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LoadMemory (&memval, &memval1, uncached, AccessLength_WORD, paddr,
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vaddr, isDATA, isREAL);
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byte = ((vaddr & mask) ^ (bigend << shift));
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GPR[rt] = EXTEND32 (memval >> (8 * byte));
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LLBIT = 1;
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}
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unsigned64 memval = 0;
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unsigned64 memval1 = 0;
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unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
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unsigned int shift = 2;
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unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
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unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
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unsigned int byte;
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paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
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LoadMemory (&memval, &memval1, AccessLength_WORD, paddr, vaddr,
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isDATA, isREAL);
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byte = ((vaddr & mask) ^ (bigend << shift));
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GPR[rt] = EXTEND32 (memval >> (8 * byte));
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LLBIT = 1;
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}
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}
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}
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@ -818,8 +813,8 @@
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address_word offset = EXTEND16 (roffset);
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{
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address_word vaddr = loadstore_ea (SD_, base, offset);
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address_word paddr;
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int uncached;
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address_word paddr = vaddr;
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if ((vaddr & 7) != 0)
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{
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SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer,
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@ -827,16 +822,12 @@
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}
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else
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{
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if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
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isTARGET, isREAL))
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{
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unsigned64 memval = 0;
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unsigned64 memval1 = 0;
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LoadMemory (&memval, &memval1, uncached, AccessLength_DOUBLEWORD,
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paddr, vaddr, isDATA, isREAL);
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GPR[rt] = memval;
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LLBIT = 1;
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}
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unsigned64 memval = 0;
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unsigned64 memval1 = 0;
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LoadMemory (&memval, &memval1, AccessLength_DOUBLEWORD, paddr, vaddr,
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isDATA, isREAL);
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GPR[rt] = memval;
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LLBIT = 1;
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}
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}
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}
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@ -1084,13 +1075,8 @@
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address_word offset = EXTEND16 (insn_offset);
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{
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address_word vaddr = loadstore_ea (SD_, base, offset);
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address_word paddr;
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int uncached;
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{
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if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
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isTARGET, isREAL))
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Prefetch (uncached, paddr, vaddr, isDATA, hint);
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}
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address_word paddr = vaddr;
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/* Prefetch (paddr, vaddr, isDATA, hint); */
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}
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}
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@ -1101,8 +1087,8 @@
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address_word offset = EXTEND16 (offsetarg);
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{
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address_word vaddr = loadstore_ea (SD_, base, offset);
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address_word paddr;
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int uncached;
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address_word paddr = vaddr;
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if ((vaddr & 3) != 0)
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{
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SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer,
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@ -1110,27 +1096,21 @@
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}
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else
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{
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if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
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isTARGET, isREAL))
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{
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unsigned64 memval = 0;
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unsigned64 memval1 = 0;
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unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
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address_word reverseendian =
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(ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
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address_word bigendiancpu =
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(BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
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unsigned int byte;
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paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
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byte = ((vaddr & mask) ^ bigendiancpu);
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memval = ((unsigned64) GPR[rt] << (8 * byte));
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if (LLBIT)
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{
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StoreMemory (uncached, AccessLength_WORD, memval, memval1,
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paddr, vaddr, isREAL);
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}
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GPR[rt] = LLBIT;
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}
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unsigned64 memval = 0;
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unsigned64 memval1 = 0;
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unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
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address_word reverseendian =
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(ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
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address_word bigendiancpu =
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(BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
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unsigned int byte;
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paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
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byte = ((vaddr & mask) ^ bigendiancpu);
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memval = ((unsigned64) GPR[rt] << (8 * byte));
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if (LLBIT)
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StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr,
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isREAL);
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GPR[rt] = LLBIT;
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}
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}
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}
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@ -1141,8 +1121,8 @@
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address_word offset = EXTEND16 (roffset);
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{
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address_word vaddr = loadstore_ea (SD_, base, offset);
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address_word paddr;
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int uncached;
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address_word paddr = vaddr;
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if ((vaddr & 7) != 0)
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{
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SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer,
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@ -1150,19 +1130,13 @@
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}
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else
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{
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if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
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isTARGET, isREAL))
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{
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unsigned64 memval = 0;
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unsigned64 memval1 = 0;
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memval = GPR[rt];
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if (LLBIT)
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{
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StoreMemory (uncached, AccessLength_DOUBLEWORD, memval, memval1,
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paddr, vaddr, isREAL);
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}
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GPR[rt] = LLBIT;
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}
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unsigned64 memval = 0;
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unsigned64 memval1 = 0;
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memval = GPR[rt];
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if (LLBIT)
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StoreMemory (AccessLength_DOUBLEWORD, memval, memval1, paddr, vaddr,
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isREAL);
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GPR[rt] = LLBIT;
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}
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}
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}
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@ -1649,11 +1623,8 @@
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address_word index = GPR[rindex];
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{
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address_word vaddr = loadstore_ea (SD_, base, index);
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address_word paddr;
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int uncached;
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if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
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isREAL))
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Prefetch (uncached, paddr, vaddr, isDATA, hint);
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address_word paddr = vaddr;
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/* Prefetch (paddr, vaddr, isDATA, hint); */
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}
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}
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@ -1716,8 +1687,8 @@
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check_fpu (SD_);
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{
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address_word vaddr = loadstore_ea (SD_, base, offset);
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address_word paddr;
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int uncached;
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address_word paddr = vaddr;
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if ((vaddr & 3) != 0)
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{
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SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr,
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@ -1725,23 +1696,18 @@
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}
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else
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{
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if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
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isTARGET, isREAL))
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{
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uword64 memval = 0;
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uword64 memval1 = 0;
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uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
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address_word reverseendian =
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(ReverseEndian ?(mask ^ AccessLength_WORD): 0);
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address_word bigendiancpu =
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(BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
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unsigned int byte;
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paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
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byte = ((vaddr & mask) ^ bigendiancpu);
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memval = (((uword64)COP_SW(1, ft)) << (8 * byte));
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StoreMemory (uncached, AccessLength_WORD, memval, memval1, paddr,
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vaddr, isREAL);
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}
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uword64 memval = 0;
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uword64 memval1 = 0;
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uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
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address_word reverseendian =
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(ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
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address_word bigendiancpu =
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(BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
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unsigned int byte;
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paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
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byte = ((vaddr & mask) ^ bigendiancpu);
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memval = (((uword64)COP_SW(1, ft)) << (8 * byte));
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StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr, isREAL);
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}
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}
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}
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@ -1754,8 +1720,8 @@
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check_u64 (SD_, instruction_0);
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{
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address_word vaddr = loadstore_ea (SD_, base, index);
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address_word paddr;
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int uncached;
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address_word paddr = vaddr;
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if ((vaddr & 3) != 0)
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{
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SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer,
|
||||
|
|
@ -1763,23 +1729,19 @@
|
|||
}
|
||||
else
|
||||
{
|
||||
if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
|
||||
isTARGET, isREAL))
|
||||
{
|
||||
unsigned64 memval = 0;
|
||||
unsigned64 memval1 = 0;
|
||||
unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
||||
address_word reverseendian =
|
||||
(ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
|
||||
address_word bigendiancpu =
|
||||
(BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
|
||||
unsigned int byte;
|
||||
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
|
||||
byte = ((vaddr & mask) ^ bigendiancpu);
|
||||
memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
|
||||
StoreMemory (uncached, AccessLength_WORD, memval, memval1, paddr,
|
||||
vaddr, isREAL);
|
||||
}
|
||||
unsigned64 memval = 0;
|
||||
unsigned64 memval1 = 0;
|
||||
unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
||||
address_word reverseendian =
|
||||
(ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
|
||||
address_word bigendiancpu =
|
||||
(BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
|
||||
unsigned int byte;
|
||||
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
|
||||
byte = ((vaddr & mask) ^ bigendiancpu);
|
||||
memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
|
||||
StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr,
|
||||
isREAL);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -3163,18 +3125,16 @@
|
|||
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
|
||||
unsigned int byte;
|
||||
address_word paddr;
|
||||
int uncached;
|
||||
unsigned64 memval;
|
||||
address_word vaddr;
|
||||
|
||||
vaddr = loadstore_ea (SD_, base, offset);
|
||||
paddr = vaddr = loadstore_ea (SD_, base, offset);
|
||||
if ((vaddr & access) != 0)
|
||||
{
|
||||
SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
|
||||
}
|
||||
AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
|
||||
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
|
||||
LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
|
||||
LoadMemory (&memval, NULL, access, paddr, vaddr, isDATA, isREAL);
|
||||
byte = ((vaddr & mask) ^ bigendiancpu);
|
||||
return (memval >> (8 * byte));
|
||||
}
|
||||
|
|
@ -3187,7 +3147,6 @@
|
|||
unsigned int byte;
|
||||
unsigned int word;
|
||||
address_word paddr;
|
||||
int uncached;
|
||||
unsigned64 memval;
|
||||
address_word vaddr;
|
||||
int nr_lhs_bits;
|
||||
|
|
@ -3195,8 +3154,7 @@
|
|||
unsigned_word lhs_mask;
|
||||
unsigned_word temp;
|
||||
|
||||
vaddr = loadstore_ea (SD_, base, offset);
|
||||
AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
|
||||
paddr = vaddr = loadstore_ea (SD_, base, offset);
|
||||
paddr = (paddr ^ (reverseendian & mask));
|
||||
if (BigEndianMem == 0)
|
||||
paddr = paddr & ~access;
|
||||
|
|
@ -3213,7 +3171,7 @@
|
|||
(long) ((unsigned64) paddr >> 32), (long) paddr,
|
||||
word, byte, nr_lhs_bits, nr_rhs_bits); */
|
||||
|
||||
LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
|
||||
LoadMemory (&memval, NULL, byte, paddr, vaddr, isDATA, isREAL);
|
||||
if (word == 0)
|
||||
{
|
||||
/* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
|
||||
|
|
@ -3242,19 +3200,17 @@
|
|||
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
|
||||
unsigned int byte;
|
||||
address_word paddr;
|
||||
int uncached;
|
||||
unsigned64 memval;
|
||||
address_word vaddr;
|
||||
|
||||
vaddr = loadstore_ea (SD_, base, offset);
|
||||
AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
|
||||
paddr = vaddr = loadstore_ea (SD_, base, offset);
|
||||
/* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
|
||||
paddr = (paddr ^ (reverseendian & mask));
|
||||
if (BigEndianMem != 0)
|
||||
paddr = paddr & ~access;
|
||||
byte = ((vaddr & mask) ^ (bigendiancpu & mask));
|
||||
/* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
|
||||
LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
|
||||
LoadMemory (&memval, NULL, access - (access & byte), paddr, vaddr, isDATA, isREAL);
|
||||
/* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
|
||||
(long) paddr, byte, (long) paddr, (long) memval); */
|
||||
{
|
||||
|
|
@ -4043,20 +3999,18 @@
|
|||
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
|
||||
unsigned int byte;
|
||||
address_word paddr;
|
||||
int uncached;
|
||||
unsigned64 memval;
|
||||
address_word vaddr;
|
||||
|
||||
vaddr = loadstore_ea (SD_, base, offset);
|
||||
paddr = vaddr = loadstore_ea (SD_, base, offset);
|
||||
if ((vaddr & access) != 0)
|
||||
{
|
||||
SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
|
||||
}
|
||||
AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
|
||||
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
|
||||
byte = ((vaddr & mask) ^ bigendiancpu);
|
||||
memval = (word << (8 * byte));
|
||||
StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
|
||||
StoreMemory (access, memval, 0, paddr, vaddr, isREAL);
|
||||
}
|
||||
|
||||
:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
|
||||
|
|
@ -4067,14 +4021,12 @@
|
|||
unsigned int byte;
|
||||
unsigned int word;
|
||||
address_word paddr;
|
||||
int uncached;
|
||||
unsigned64 memval;
|
||||
address_word vaddr;
|
||||
int nr_lhs_bits;
|
||||
int nr_rhs_bits;
|
||||
|
||||
vaddr = loadstore_ea (SD_, base, offset);
|
||||
AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
|
||||
paddr = vaddr = loadstore_ea (SD_, base, offset);
|
||||
paddr = (paddr ^ (reverseendian & mask));
|
||||
if (BigEndianMem == 0)
|
||||
paddr = paddr & ~access;
|
||||
|
|
@ -4101,7 +4053,7 @@
|
|||
/* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
|
||||
(long) ((unsigned64) rt >> 32), (long) rt,
|
||||
(long) ((unsigned64) memval >> 32), (long) memval); */
|
||||
StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
|
||||
StoreMemory (byte, memval, 0, paddr, vaddr, isREAL);
|
||||
}
|
||||
|
||||
:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
|
||||
|
|
@ -4111,18 +4063,16 @@
|
|||
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
|
||||
unsigned int byte;
|
||||
address_word paddr;
|
||||
int uncached;
|
||||
unsigned64 memval;
|
||||
address_word vaddr;
|
||||
|
||||
vaddr = loadstore_ea (SD_, base, offset);
|
||||
AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
|
||||
paddr = vaddr = loadstore_ea (SD_, base, offset);
|
||||
paddr = (paddr ^ (reverseendian & mask));
|
||||
if (BigEndianMem != 0)
|
||||
paddr &= ~access;
|
||||
byte = ((vaddr & mask) ^ (bigendiancpu & mask));
|
||||
memval = (rt << (byte * 8));
|
||||
StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
|
||||
StoreMemory (access - (access & byte), memval, 0, paddr, vaddr, isREAL);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -5118,24 +5068,20 @@
|
|||
int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
|
||||
address_word vaddr;
|
||||
address_word paddr;
|
||||
int uncached;
|
||||
unsigned64 memval;
|
||||
unsigned64 v;
|
||||
|
||||
vaddr = loadstore_ea (SD_, base, offset);
|
||||
paddr = vaddr = loadstore_ea (SD_, base, offset);
|
||||
if ((vaddr & AccessLength_DOUBLEWORD) != 0)
|
||||
{
|
||||
SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
|
||||
AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
|
||||
sim_core_unaligned_signal);
|
||||
}
|
||||
AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
|
||||
isREAL);
|
||||
LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
|
||||
isDATA, isREAL);
|
||||
LoadMemory (&memval, NULL, AccessLength_WORD, paddr, vaddr, isDATA, isREAL);
|
||||
v = (unsigned64)memval;
|
||||
LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
|
||||
isDATA, isREAL);
|
||||
LoadMemory (&memval, NULL, AccessLength_WORD, paddr + 4, vaddr + 4, isDATA,
|
||||
isREAL);
|
||||
return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
|
||||
}
|
||||
|
||||
|
|
@ -5156,24 +5102,19 @@
|
|||
int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
|
||||
address_word vaddr;
|
||||
address_word paddr;
|
||||
int uncached;
|
||||
unsigned64 memval;
|
||||
|
||||
vaddr = loadstore_ea (SD_, base, offset);
|
||||
paddr = vaddr = loadstore_ea (SD_, base, offset);
|
||||
if ((vaddr & AccessLength_DOUBLEWORD) != 0)
|
||||
{
|
||||
SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
|
||||
AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
|
||||
sim_core_unaligned_signal);
|
||||
}
|
||||
AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
|
||||
isREAL);
|
||||
memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
|
||||
StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
|
||||
isREAL);
|
||||
StoreMemory (AccessLength_WORD, memval, 0, paddr, vaddr, isREAL);
|
||||
memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
|
||||
StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
|
||||
isREAL);
|
||||
StoreMemory (AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4, isREAL);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -6379,10 +6320,8 @@
|
|||
address_word offset = EXTEND16 (OFFSET);
|
||||
{
|
||||
address_word vaddr = loadstore_ea (SD_, base, offset);
|
||||
address_word paddr;
|
||||
int uncached;
|
||||
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
|
||||
CacheOp(OP,vaddr,paddr,instruction_0);
|
||||
address_word paddr = vaddr;
|
||||
CacheOp(OP, vaddr, paddr, instruction_0);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -28,81 +28,6 @@
|
|||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
/* Description from page A-22 of the "MIPS IV Instruction Set" manual
|
||||
(revision 3.1) */
|
||||
/* Translate a virtual address to a physical address and cache
|
||||
coherence algorithm describing the mechanism used to resolve the
|
||||
memory reference. Given the virtual address vAddr, and whether the
|
||||
reference is to Instructions ot Data (IorD), find the corresponding
|
||||
physical address (pAddr) and the cache coherence algorithm (CCA)
|
||||
used to resolve the reference. If the virtual address is in one of
|
||||
the unmapped address spaces the physical address and the CCA are
|
||||
determined directly by the virtual address. If the virtual address
|
||||
is in one of the mapped address spaces then the TLB is used to
|
||||
determine the physical address and access type; if the required
|
||||
translation is not present in the TLB or the desired access is not
|
||||
permitted the function fails and an exception is taken.
|
||||
|
||||
NOTE: Normally (RAW == 0), when address translation fails, this
|
||||
function raises an exception and does not return. */
|
||||
|
||||
INLINE_SIM_MAIN
|
||||
(int)
|
||||
address_translation (SIM_DESC sd,
|
||||
sim_cpu * cpu,
|
||||
address_word cia,
|
||||
address_word vAddr,
|
||||
int IorD,
|
||||
int LorS,
|
||||
address_word * pAddr,
|
||||
int *CCA,
|
||||
int raw)
|
||||
{
|
||||
int res = -1; /* TRUE : Assume good return */
|
||||
|
||||
#ifdef DEBUG
|
||||
sim_io_printf (sd, "AddressTranslation(0x%s,%s,%s,...);\n", pr_addr (vAddr), (IorD ? "isDATA" : "isINSTRUCTION"), (LorS ? "iSTORE" : "isLOAD"));
|
||||
#endif
|
||||
|
||||
/* Check that the address is valid for this memory model */
|
||||
|
||||
/* For a simple (flat) memory model, we simply pass virtual
|
||||
addressess through (mostly) unchanged. */
|
||||
vAddr &= 0xFFFFFFFF;
|
||||
|
||||
*pAddr = vAddr; /* default for isTARGET */
|
||||
*CCA = Uncached; /* not used for isHOST */
|
||||
|
||||
return (res);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* Description from page A-23 of the "MIPS IV Instruction Set" manual
|
||||
(revision 3.1) */
|
||||
/* Prefetch data from memory. Prefetch is an advisory instruction for
|
||||
which an implementation specific action is taken. The action taken
|
||||
may increase performance, but must not change the meaning of the
|
||||
program, or alter architecturally-visible state. */
|
||||
|
||||
INLINE_SIM_MAIN (void)
|
||||
prefetch (SIM_DESC sd,
|
||||
sim_cpu *cpu,
|
||||
address_word cia,
|
||||
int CCA,
|
||||
address_word pAddr,
|
||||
address_word vAddr,
|
||||
int DATA,
|
||||
int hint)
|
||||
{
|
||||
#ifdef DEBUG
|
||||
sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint);
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* For our simple memory model we do nothing */
|
||||
return;
|
||||
}
|
||||
|
||||
/* Description from page A-22 of the "MIPS IV Instruction Set" manual
|
||||
(revision 3.1) */
|
||||
/* Load a value from memory. Use the cache and main memory as
|
||||
|
|
@ -337,15 +262,13 @@ ifetch32 (SIM_DESC SD,
|
|||
address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
|
||||
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
|
||||
unsigned int byte;
|
||||
address_word paddr;
|
||||
int uncached;
|
||||
address_word paddr = vaddr;
|
||||
unsigned64 memval;
|
||||
|
||||
if ((vaddr & access) != 0)
|
||||
SignalExceptionInstructionFetch ();
|
||||
AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL);
|
||||
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
|
||||
LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isINSTRUCTION, isREAL);
|
||||
LoadMemory (&memval, NULL, access, paddr, vaddr, isINSTRUCTION, isREAL);
|
||||
byte = ((vaddr & mask) ^ bigendiancpu);
|
||||
return (memval >> (8 * byte));
|
||||
}
|
||||
|
|
@ -363,15 +286,13 @@ ifetch16 (SIM_DESC SD,
|
|||
address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
|
||||
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
|
||||
unsigned int byte;
|
||||
address_word paddr;
|
||||
int uncached;
|
||||
address_word paddr = vaddr;
|
||||
unsigned64 memval;
|
||||
|
||||
if ((vaddr & access) != 0)
|
||||
SignalExceptionInstructionFetch ();
|
||||
AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL);
|
||||
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
|
||||
LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isINSTRUCTION, isREAL);
|
||||
LoadMemory (&memval, NULL, access, paddr, vaddr, isINSTRUCTION, isREAL);
|
||||
byte = ((vaddr & mask) ^ bigendiancpu);
|
||||
return (memval >> (8 * byte));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -908,12 +908,6 @@ unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64);
|
|||
/* The following are generic to all versions of the MIPS architecture
|
||||
to date: */
|
||||
|
||||
/* Memory Access Types (for CCA): */
|
||||
#define Uncached (0)
|
||||
#define CachedNoncoherent (1)
|
||||
#define CachedCoherent (2)
|
||||
#define Cached (3)
|
||||
|
||||
#define isINSTRUCTION (1 == 0) /* FALSE */
|
||||
#define isDATA (1 == 1) /* TRUE */
|
||||
#define isLOAD (1 == 0) /* FALSE */
|
||||
|
|
@ -942,17 +936,13 @@ unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64);
|
|||
#define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
|
||||
|
||||
|
||||
INLINE_SIM_MAIN (int) address_translation (SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw);
|
||||
#define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
|
||||
address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
|
||||
|
||||
INLINE_SIM_MAIN (void) load_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD);
|
||||
#define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
|
||||
load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
|
||||
#define LoadMemory(memvalp,memval1p,AccessLength,pAddr,vAddr,IorD,raw) \
|
||||
load_memory (SD, CPU, cia, memvalp, memval1p, 0, AccessLength, pAddr, vAddr, IorD)
|
||||
|
||||
INLINE_SIM_MAIN (void) store_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr);
|
||||
#define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
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store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
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#define StoreMemory(AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
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store_memory (SD, CPU, cia, 0, AccessLength, MemElem, MemElem1, pAddr, vAddr)
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INLINE_SIM_MAIN (void) cache_op (SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction);
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#define CacheOp(op,pAddr,vAddr,instruction) \
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@ -962,10 +952,6 @@ INLINE_SIM_MAIN (void) sync_operation (SIM_DESC sd, sim_cpu *cpu, address_word c
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#define SyncOperation(stype) \
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sync_operation (SD, CPU, cia, (stype))
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INLINE_SIM_MAIN (void) prefetch (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint);
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#define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
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prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
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void unpredictable_action (sim_cpu *cpu, address_word cia);
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#define NotWordValue(val) not_word_value (SD_, (val))
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||||
#define Unpredictable() unpredictable (SD_)
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||||
|
|
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Loading…
Reference in New Issue