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RISC-V: Add support for addi that compresses to c.nop. 

gas/
	* testsuite/gas/riscv/c-zero-imm.s: Test addi that compresses to c.nop.
	* testsuite/gas/riscv/c-zero-imm.d: Likewise.
	opcodes/
	* riscv-opc.c (match_c_nop): New.
	(riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
This commit is contained in:
Jim Wilson 2018-01-15 14:53:44 -08:00
parent db422fb212
commit 2721d702a0
5 changed files with 22 additions and 2 deletions
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5
gas/ChangeLog
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@ -1,3 +1,8 @@
2018-01-15 Jim Wilson <jimw@sifive.com>
* testsuite/gas/riscv/c-zero-imm.s: Test addi that compresses to c.nop.
* testsuite/gas/riscv/c-zero-imm.d: Likewise.
2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (ToC): Define macro.

5
gas/testsuite/gas/riscv/c-zero-imm.d
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@ -11,6 +11,7 @@ Disassembly of section .text:
[ ]+2:[ ]+4581[ ]+li[ ]+a1,0
[ ]+4:[ ]+8a01[ ]+andi[ ]+a2,a2,0
[ ]+6:[ ]+8a81[ ]+andi[ ]+a3,a3,0
[ ]+8:[ ]+00070713[ ]+mv[ ]+a4,a4
[ ]+c:[ ]+0781[ ]+addi[ ]+a5,a5,0
[ ]+8:[ ]+0001[ ]+nop
[ ]+a:[ ]+00070713[ ]+mv[ ]+a4,a4
[ ]+e:[ ]+0781[ ]+addi[ ]+a5,a5,0
#...

1
gas/testsuite/gas/riscv/c-zero-imm.s
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@ -4,6 +4,7 @@
c.li a1,0
andi a2,a2,0
c.andi a3,0
addi x0,x0,0
# Don't let this compress to a hint.
addi a4,a4,0
# These are hints.

5
opcodes/ChangeLog
View File

@ -1,3 +1,8 @@
2018-01-15 Jim Wilson <jimw@sifive.com>
* riscv-opc.c (match_c_nop): New.
(riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2018-01-15 Nick Clifton <nickc@redhat.com>
* po/uk.po: Updated Ukranian translation.

8
opcodes/riscv-opc.c
View File

@ -122,6 +122,13 @@ match_c_add_with_hint (const struct riscv_opcode *op, insn_t insn)
return match_opcode (op, insn) && ((insn & MASK_CRS2) != 0);
}
static int
match_c_nop (const struct riscv_opcode *op, insn_t insn)
{
return (match_opcode (op, insn)
&& (((insn & MASK_RD) >> OP_SH_RD) == 0));
}
static int
match_c_addi16sp (const struct riscv_opcode *op, insn_t insn)
{
@ -225,6 +232,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"bne", "I", "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, 0 },
{"addi", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS },
{"addi", "C", "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
{"addi", "C", "d,CU,0", MATCH_C_NOP, MASK_C_ADDI | MASK_RVC_IMM, match_c_nop, INSN_ALIAS },
{"addi", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS },
{"addi", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, 0 },
{"add", "C", "d,CU,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS },