RISC-V: Add support for addi that compresses to c.nop.
gas/ * testsuite/gas/riscv/c-zero-imm.s: Test addi that compresses to c.nop. * testsuite/gas/riscv/c-zero-imm.d: Likewise. opcodes/ * riscv-opc.c (match_c_nop): New. (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
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@ -1,3 +1,8 @@
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2018-01-15 Jim Wilson <jimw@sifive.com>
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* testsuite/gas/riscv/c-zero-imm.s: Test addi that compresses to c.nop.
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* testsuite/gas/riscv/c-zero-imm.d: Likewise.
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2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
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2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* config/tc-arm.c (ToC): Define macro.
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* config/tc-arm.c (ToC): Define macro.
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@ -11,6 +11,7 @@ Disassembly of section .text:
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[ ]+2:[ ]+4581[ ]+li[ ]+a1,0
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[ ]+2:[ ]+4581[ ]+li[ ]+a1,0
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[ ]+4:[ ]+8a01[ ]+andi[ ]+a2,a2,0
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[ ]+4:[ ]+8a01[ ]+andi[ ]+a2,a2,0
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[ ]+6:[ ]+8a81[ ]+andi[ ]+a3,a3,0
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[ ]+6:[ ]+8a81[ ]+andi[ ]+a3,a3,0
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[ ]+8:[ ]+00070713[ ]+mv[ ]+a4,a4
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[ ]+8:[ ]+0001[ ]+nop
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[ ]+c:[ ]+0781[ ]+addi[ ]+a5,a5,0
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[ ]+a:[ ]+00070713[ ]+mv[ ]+a4,a4
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[ ]+e:[ ]+0781[ ]+addi[ ]+a5,a5,0
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#...
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#...
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@ -4,6 +4,7 @@
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c.li a1,0
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c.li a1,0
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andi a2,a2,0
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andi a2,a2,0
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c.andi a3,0
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c.andi a3,0
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addi x0,x0,0
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# Don't let this compress to a hint.
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# Don't let this compress to a hint.
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addi a4,a4,0
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addi a4,a4,0
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# These are hints.
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# These are hints.
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@ -1,3 +1,8 @@
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2018-01-15 Jim Wilson <jimw@sifive.com>
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* riscv-opc.c (match_c_nop): New.
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(riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
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2018-01-15 Nick Clifton <nickc@redhat.com>
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2018-01-15 Nick Clifton <nickc@redhat.com>
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* po/uk.po: Updated Ukranian translation.
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* po/uk.po: Updated Ukranian translation.
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@ -122,6 +122,13 @@ match_c_add_with_hint (const struct riscv_opcode *op, insn_t insn)
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return match_opcode (op, insn) && ((insn & MASK_CRS2) != 0);
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return match_opcode (op, insn) && ((insn & MASK_CRS2) != 0);
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}
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}
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static int
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match_c_nop (const struct riscv_opcode *op, insn_t insn)
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{
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return (match_opcode (op, insn)
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&& (((insn & MASK_RD) >> OP_SH_RD) == 0));
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}
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static int
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static int
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match_c_addi16sp (const struct riscv_opcode *op, insn_t insn)
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match_c_addi16sp (const struct riscv_opcode *op, insn_t insn)
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{
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{
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@ -225,6 +232,7 @@ const struct riscv_opcode riscv_opcodes[] =
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{"bne", "I", "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, 0 },
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{"bne", "I", "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, 0 },
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{"addi", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS },
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{"addi", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS },
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{"addi", "C", "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
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{"addi", "C", "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
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{"addi", "C", "d,CU,0", MATCH_C_NOP, MASK_C_ADDI | MASK_RVC_IMM, match_c_nop, INSN_ALIAS },
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{"addi", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS },
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{"addi", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS },
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{"addi", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, 0 },
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{"addi", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, 0 },
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{"add", "C", "d,CU,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS },
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{"add", "C", "d,CU,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS },
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