Add support for SIGILL (reserved-instruction-exception).

sim/d10v/ChangeLog

@@ -1,3 +1,8 @@
+Tue Apr 18 16:26:41 2000  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* interp.c (sim_resume): Deliver SIGILL.
+	(lookup_hash): Do not print SIGILL message.
+
 Tue Feb 22 18:24:56 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 
 	* Makefile.in (SIM_EXTRA_CFLAGS): Define SIM_HAVE_ENVIRONMENT.

sim/d10v/interp.c

@@ -99,8 +99,6 @@ lookup_hash (ins, size)
     {
       if (h->next == NULL)
 	{
-	  (*d10v_callback->printf_filtered)
-	    (d10v_callback, "ERROR: Illegal instruction %x at PC %x\n", ins, PC);
 	  State.exception = SIGILL;
 	  State.pc_changed = 1; /* Don't increment the PC. */
 	  return NULL;
@@ -979,6 +977,13 @@ sim_resume (sd, step, siggnal)
       JMP (AE_VECTOR_START);
       SLOT_FLUSH ();
       break;
+    case SIGILL:
+      SET_BPC (PC);
+      SET_BPSW (PSW);
+      SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
+      JMP (RIE_VECTOR_START);
+      SLOT_FLUSH ();
+      break;
     default:
       /* just ignore it */
       break;

sim/testsuite/d10v-elf/ChangeLog

@@ -1,3 +1,8 @@
+Tue Apr 18 16:32:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* t-rie-xx.s (test_rie_xx): New test.
+	* Makefile.in (TESTS): Update.
+
 Tue Feb 22 17:36:34 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 
 	* Makefile.in: Force d10v into operating mode.

sim/testsuite/d10v-elf/Makefile.in

@@ -83,6 +83,7 @@ TESTS = \
 	t-ae-st2w-ip.ok \
 	t-ae-st2w-is.ok \
 	t-mod-ld-pre.ok \
+	t-rie-xx.ok \
 #
 
 AS_FOR_TARGET = `\

sim/testsuite/d10v-elf/t-rie-xx.s

@@ -0,0 +1,12 @@
+.include "t-macros.i"
+
+	start
+
+	PSW_BITS = 0
+	point_dmap_at_imem
+	check_interrupt (VEC_RIE&DMAP_MASK)+DMAP_BASE PSW_BITS test_rie_xx
+	
+test_rie_xx:
+        .short 0xe120, 0x0000  ;; Example of RIE code
+	nop
+	exit47