S12Z opcodes: Fix bug disassembling certain shift instructions.
Shift and rotate instructions when the number of bit positions was an immediate value greater than 1 were incorrectly disassembled. This change fixes that problem and extends the test to check for it. gas/ChangeLog: testsuite/gas/s12z/shift.s: Add new test case. testsuite/gas/s12z/shift.d: Add expected result. opcodes/ChangeLog: s12z-dis.c (print_insn_shift) [SB_REG_REG_N]: Enter special case if the postbyte matches the appropriate pattern.
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@ -1,3 +1,8 @@
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2018-11-21 John Darrington <john@darrington.wattle.id.au>
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* testsuite/gas/s12z/shift.s: Add new test case.
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* testsuite/gas/s12z/shift.d: Add expected result.
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2018-11-21 John Darrington <john@darrington.wattle.id.au>
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* config/tc-s12z.c (opcodes): bhs, blo: New members.
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@ -1,5 +1,5 @@
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#objdump: -d
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#name:
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#name: Tests for shift and rotate instructions
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#source: shift.s
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@ -20,3 +20,5 @@ Disassembly of section .text:
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17: 10 3e 8e lsr.p \(d6,x\), #2
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1a: 10 f4 bf asl d7, #1
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1d: 10 bc bd asr d1, #2
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20: 16 de 78 asl d6, d6, #17
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23: 16 d6 78 asl d6, d6, #16
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@ -9,3 +9,5 @@
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lsr.p (d6,x), #2
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asl d7, #1
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asr d1, #2
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asl d6, d6, #17
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asl d6, d6, #16
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@ -1,3 +1,8 @@
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2018-11-21 John Darrington <john@darrington.wattle.id.au>
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* s12z-dis.c (print_insn_shift) [SB_REG_REG_N]: Enter special case
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if the postbyte matches the appropriate pattern.
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2018-11-13 Francois H. Theron <francois.theron@netronome.com>
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* nfp-dis.c: Fix crc[] disassembly if operands are swapped.
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@ -2363,25 +2363,31 @@ print_insn_shift (bfd_vma memaddr, struct disassemble_info* info, uint8_t byte)
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break;
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case SB_REG_REG_N:
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if (sb & 0x08)
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{
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operand_separator (info);
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if (byte & 0x10)
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{
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uint8_t xb;
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read_memory (memaddr + 1, &xb, 1, info);
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int shift = ((sb & 0x08) >> 3) | ((xb & 0x0f) << 1);
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(*info->fprintf_func) (info->stream, "#%d", shift);
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}
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else
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{
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(*info->fprintf_func) (info->stream, "%s:%d", __FILE__, __LINE__);
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}
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}
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else
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{
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opr_decode (memaddr + 1, info);
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}
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{
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uint8_t xb;
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read_memory (memaddr + 1, &xb, 1, info);
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/* This case is slightly unusual.
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If XB matches the binary pattern 0111XXXX, then instead of
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interpreting this as a general OPR postbyte in the IMMe4 mode,
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the XB byte is interpreted in s special way. */
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if ((xb & 0xF0) == 0x70)
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{
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operand_separator (info);
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if (byte & 0x10)
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{
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int shift = ((sb & 0x08) >> 3) | ((xb & 0x0f) << 1);
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(*info->fprintf_func) (info->stream, "#%d", shift);
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}
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else
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{
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(*info->fprintf_func) (info->stream, "%s:%d", __FILE__, __LINE__);
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}
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}
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else
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{
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opr_decode (memaddr + 1, info);
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}
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}
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break;
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case SB_REG_OPR_OPR:
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{
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