* v850-opc.c (v850_opcodes): Add initializer for size field
on all opcodes.
This commit is contained in:
Jeff Law
parent
4be84c4951
commit
280d40df39
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@ -1,6 +1,9 @@
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start-sanitize-v850
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Fri Aug 23 00:27:01 1996 Jeffrey A Law (law@cygnus.com)
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* v850-opc.c (v850_opcodes): Add initializer for size field
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on all opcodes.
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* v850-opc.c (v850_operands): D6 -> DS7. References changed.
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Add D8 for 8-bit unsigned field in short load/store insns.
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(IF4A, IF4D): These both need two registers.
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@ -123,106 +123,106 @@ const struct v850_operand v850_operands[] = {
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const struct v850_opcode v850_opcodes[] = {
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/* load/store instructions */
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{ "sld.b", OP(0x00), OP_MASK, IF4A },
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{ "sld.h", OP(0x00), OP_MASK, IF4C },
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{ "sld.w", OP(0x00), OP_MASK, IF4C },
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{ "sst.b", OP(0x00), OP_MASK, IF4B },
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{ "sst.h", OP(0x00), OP_MASK, IF4D },
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{ "sst.w", OP(0x00), OP_MASK, IF4D },
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{ "sld.b", OP(0x00), OP_MASK, IF4A, 2 },
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{ "sld.h", OP(0x00), OP_MASK, IF4C, 2 },
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{ "sld.w", OP(0x00), OP_MASK, IF4C, 2 },
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{ "sst.b", OP(0x00), OP_MASK, IF4B, 2 },
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{ "sst.h", OP(0x00), OP_MASK, IF4D, 2 },
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{ "sst.w", OP(0x00), OP_MASK, IF4D, 2 },
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{ "ld.b", OP(0x00), OP_MASK, IF7A },
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{ "ld.h", OP(0x00), OP_MASK, IF7A },
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{ "ld.w", OP(0x00), OP_MASK, IF7A },
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{ "st.b", OP(0x00), OP_MASK, IF7B },
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{ "st.h", OP(0x00), OP_MASK, IF7B },
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{ "st.w", OP(0x00), OP_MASK, IF7B },
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{ "ld.b", OP(0x00), OP_MASK, IF7A, 4 },
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{ "ld.h", OP(0x00), OP_MASK, IF7A, 4 },
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{ "ld.w", OP(0x00), OP_MASK, IF7A, 4 },
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{ "st.b", OP(0x00), OP_MASK, IF7B, 4 },
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{ "st.h", OP(0x00), OP_MASK, IF7B, 4 },
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{ "st.w", OP(0x00), OP_MASK, IF7B, 4 },
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/* arithmetic operation instructions */
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{ "mov", OP(0x00), OP_MASK, IF1 },
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{ "mov", OP(0x08), OP_MASK, IF2 },
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{ "movea", OP(0x31), OP_MASK, IF6 },
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{ "movhi", OP(0x31), OP_MASK, IF6 },
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{ "add", OP(0x0e), OP_MASK, IF1 },
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{ "add", OP(0x12), OP_MASK, IF2 },
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{ "addi", OP(0x30), OP_MASK, IF6 },
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{ "sub", OP(0x0d), OP_MASK, IF1 },
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{ "subr", OP(0x0c), OP_MASK, IF1 },
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{ "mulh", OP(0x07), OP_MASK, IF1 },
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{ "mulh", OP(0x17), OP_MASK, IF2 },
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{ "mulhi", OP(0x37), OP_MASK, IF6 },
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{ "divh", OP(0x02), OP_MASK, IF1 },
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{ "cmp", OP(0x0f), OP_MASK, IF1 },
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{ "cmp", OP(0x13), OP_MASK, IF2 },
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{ "setf", two(0x0000,0x0000), two(0x0000,0xffff), {CCCC,R2} },
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{ "mov", OP(0x00), OP_MASK, IF1, 2 },
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{ "mov", OP(0x08), OP_MASK, IF2, 2 },
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{ "movea", OP(0x31), OP_MASK, IF6, 4 },
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{ "movhi", OP(0x31), OP_MASK, IF6, 4 },
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{ "add", OP(0x0e), OP_MASK, IF1, 2 },
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{ "add", OP(0x12), OP_MASK, IF2, 2 },
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{ "addi", OP(0x30), OP_MASK, IF6, 4 },
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{ "sub", OP(0x0d), OP_MASK, IF1, 2 },
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{ "subr", OP(0x0c), OP_MASK, IF1, 2 },
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{ "mulh", OP(0x07), OP_MASK, IF1, 2 },
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{ "mulh", OP(0x17), OP_MASK, IF2, 2 },
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{ "mulhi", OP(0x37), OP_MASK, IF6, 4 },
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{ "divh", OP(0x02), OP_MASK, IF1, 2 },
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{ "cmp", OP(0x0f), OP_MASK, IF1, 2 },
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{ "cmp", OP(0x13), OP_MASK, IF2, 2 },
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{ "setf", two(0x0000,0x0000), two(0x0000,0xffff), {CCCC,R2}, 4 },
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/* saturated operation instructions */
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{ "satadd", OP(0x06), OP_MASK, IF1 },
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{ "satadd", OP(0x11), OP_MASK, IF2 },
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{ "satsub", OP(0x05), OP_MASK, IF1 },
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{ "satsubi", OP(0x33), OP_MASK, IF6 },
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{ "satsubr", OP(0x04), OP_MASK, IF1 },
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{ "satadd", OP(0x06), OP_MASK, IF1, 2 },
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{ "satadd", OP(0x11), OP_MASK, IF2, 2 },
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{ "satsub", OP(0x05), OP_MASK, IF1, 2 },
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{ "satsubi", OP(0x33), OP_MASK, IF6, 4 },
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{ "satsubr", OP(0x04), OP_MASK, IF1, 2 },
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/* logical operation instructions */
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{ "tst", OP(0x0b), OP_MASK, IF1 },
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{ "or", OP(0x08), OP_MASK, IF1 },
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{ "ori", OP(0x34), OP_MASK, IF6 },
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{ "and", OP(0x0a), OP_MASK, IF1 },
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{ "andi", OP(0x36), OP_MASK, IF6 },
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{ "xor", OP(0x09), OP_MASK, IF1 },
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{ "xori", OP(0x35), OP_MASK, IF6 },
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{ "not", OP(0x01), OP_MASK, IF1 },
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{ "sar", OP(0x15), OP_MASK, {I5U, R2} },
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{ "sar", two(0x07e0,0x00a0), two(0x07e0,0xffff), {R1,R2} },
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{ "shl", OP(0x16), OP_MASK, {I5U, R2} },
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{ "shl", two(0x07e0,0x00c0), two(0x07e0,0xffff), {R1,R2} },
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{ "shr", OP(0x14), OP_MASK, {I5U, R2} },
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{ "shr", two(0x07e0,0x0080), two(0x07e0,0xffff), {R1,R2} },
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{ "tst", OP(0x0b), OP_MASK, IF1, 2 },
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{ "or", OP(0x08), OP_MASK, IF1, 2 },
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{ "ori", OP(0x34), OP_MASK, IF6, 4 },
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{ "and", OP(0x0a), OP_MASK, IF1, 2 },
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{ "andi", OP(0x36), OP_MASK, IF6, 4 },
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{ "xor", OP(0x09), OP_MASK, IF1, 2 },
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{ "xori", OP(0x35), OP_MASK, IF6, 4 },
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{ "not", OP(0x01), OP_MASK, IF1, 4 },
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{ "sar", OP(0x15), OP_MASK, {I5U, R2}, 2 },
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{ "sar", two(0x07e0,0x00a0), two(0x07e0,0xffff), {R1,R2}, 4 },
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{ "shl", OP(0x16), OP_MASK, {I5U, R2}, 2 },
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{ "shl", two(0x07e0,0x00c0), two(0x07e0,0xffff), {R1,R2}, 4 },
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{ "shr", OP(0x14), OP_MASK, {I5U, R2}, 2 },
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{ "shr", two(0x07e0,0x0080), two(0x07e0,0xffff), {R1,R2}, 4 },
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/* branch instructions */
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/* signed integer */
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{ "bgt", BOP(0xf), BOP_MASK, IF3 },
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{ "bge", BOP(0xe), BOP_MASK, IF3 },
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{ "blt", BOP(0x6), BOP_MASK, IF3 },
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{ "ble", BOP(0x7), BOP_MASK, IF3 },
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{ "bgt", BOP(0xf), BOP_MASK, IF3, 2 },
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{ "bge", BOP(0xe), BOP_MASK, IF3, 2 },
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{ "blt", BOP(0x6), BOP_MASK, IF3, 2 },
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{ "ble", BOP(0x7), BOP_MASK, IF3, 2 },
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/* unsigned integer */
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{ "bh", BOP(0xb), BOP_MASK, IF3 },
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{ "bnh", BOP(0x3), BOP_MASK, IF3 },
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{ "bl", BOP(0x1), BOP_MASK, IF3 },
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{ "bnl", BOP(0x9), BOP_MASK, IF3 },
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{ "bh", BOP(0xb), BOP_MASK, IF3, 2 },
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{ "bnh", BOP(0x3), BOP_MASK, IF3, 2 },
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{ "bl", BOP(0x1), BOP_MASK, IF3, 2 },
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{ "bnl", BOP(0x9), BOP_MASK, IF3, 2 },
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/* common */
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{ "be", BOP(0x2), BOP_MASK, IF3 },
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{ "bne", BOP(0xa), BOP_MASK, IF3 },
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{ "be", BOP(0x2), BOP_MASK, IF3, 2 },
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{ "bne", BOP(0xa), BOP_MASK, IF3, 2 },
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/* others */
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{ "bv", BOP(0x0), BOP_MASK, IF3 },
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{ "bnv", BOP(0x8), BOP_MASK, IF3 },
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{ "bn", BOP(0x4), BOP_MASK, IF3 },
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{ "bp", BOP(0xc), BOP_MASK, IF3 },
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{ "bc", BOP(0x1), BOP_MASK, IF3 },
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{ "bnc", BOP(0x9), BOP_MASK, IF3 },
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{ "bz", BOP(0x2), BOP_MASK, IF3 },
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{ "bnz", BOP(0xa), BOP_MASK, IF3 },
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{ "br", BOP(0x5), BOP_MASK, IF3 },
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{ "bsa", BOP(0xd), BOP_MASK, IF3 },
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{ "bv", BOP(0x0), BOP_MASK, IF3, 2 },
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{ "bnv", BOP(0x8), BOP_MASK, IF3, 2 },
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{ "bn", BOP(0x4), BOP_MASK, IF3, 2 },
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{ "bp", BOP(0xc), BOP_MASK, IF3, 2 },
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{ "bc", BOP(0x1), BOP_MASK, IF3, 2 },
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{ "bnc", BOP(0x9), BOP_MASK, IF3, 2 },
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{ "bz", BOP(0x2), BOP_MASK, IF3, 2 },
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{ "bnz", BOP(0xa), BOP_MASK, IF3, 2 },
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{ "br", BOP(0x5), BOP_MASK, IF3, 2 },
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{ "bsa", BOP(0xd), BOP_MASK, IF3, 2 },
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{ "jmp", one(0x0060), one(0xffe0), R1 },
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{ "jarl", one(0x0780), one(0xf83f), { D22, R2 } },
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{ "jr", one(0x0780), one(0xffe0), { D22 } },
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{ "jmp", one(0x0060), one(0xffe0), R1, 2 },
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{ "jarl", one(0x0780), one(0xf83f), { D22, R2 }, 4 },
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{ "jr", one(0x0780), one(0xffe0), { D22 }, 4 },
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/* bit manipulation instructions */
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{ "set1", two(0x07c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
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{ "not1", two(0x47c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
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{ "clr1", two(0x87c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
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{ "tst1", two(0xc7c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1} },
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{ "set1", two(0x07c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1}, 4 },
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{ "not1", two(0x47c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1}, 4 },
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{ "clr1", two(0x87c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1}, 4 },
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{ "tst1", two(0xc7c0,0x0000), two(0xc7e0,0x0000), {B3, D16, R1}, 4 },
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/* special instructions */
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{ "di", two(0x07e0,0x0160), two(0xffff,0xffff), {0} },
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{ "ei", two(0x87e0,0x0160), two(0xffff,0xffff), {0} },
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{ "halt", two(0x07e0,0x0120), two(0xffff,0xffff), {0} },
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{ "reti", two(0x07e0,0x0140), two(0xffff,0xffff), {0} },
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{ "trap", two(0x07e0,0x0100), two(0xffe0,0xffff), I5U },
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{ "ldsr", two(0x07e0,0x0020), two(0x07e0,0xffff), IF1 },
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{ "stsr", two(0x07e0,0x0040), two(0x07e0,0xffff), IF1 },
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{ "nop", one(0x00), one(0xff), {0} },
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{ "di", two(0x07e0,0x0160), two(0xffff,0xffff), {0}, 4 },
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{ "ei", two(0x87e0,0x0160), two(0xffff,0xffff), {0}, 4 },
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{ "halt", two(0x07e0,0x0120), two(0xffff,0xffff), {0}, 4 },
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{ "reti", two(0x07e0,0x0140), two(0xffff,0xffff), {0}, 4 },
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{ "trap", two(0x07e0,0x0100), two(0xffe0,0xffff), I5U, 4 },
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{ "ldsr", two(0x07e0,0x0020), two(0x07e0,0xffff), IF1, 4 },
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{ "stsr", two(0x07e0,0x0040), two(0x07e0,0xffff), IF1, 4 },
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{ "nop", one(0x00), one(0xff), {0}, 2 },
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} ;
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