2004-02-20 Andrew Cagney <cagney@redhat.com>
* sh.cpu, sh.opc, sh64-compact.cpu, sh64-media.cpu: New files, all written by Ben Elliston.
This commit is contained in:
Andrew Cagney
parent
876f40905a
commit
299d901ce6
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@ -1,3 +1,8 @@
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2004-02-20 Andrew Cagney <cagney@redhat.com>
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* sh.cpu, sh.opc, sh64-compact.cpu, sh64-media.cpu: New files, all
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written by Ben Elliston.
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2004-01-14 Richard Sandiford <rsandifo@redhat.com>
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* frv.cpu (UNIT): Add IACC.
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@ -0,0 +1,368 @@
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; Hitachi SH architecture description. -*- Scheme -*-
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;
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; Copyright 2000, 2001 Free Software Foundation, Inc.
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;
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; Contributed by Red Hat Inc; developed under contract from Hitachi
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; Semiconductor (America) Inc.
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;
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; This file is part of the GNU Binutils.
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;
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; This program is free software; you can redistribute it and/or modify
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; it under the terms of the GNU General Public License as published by
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; the Free Software Foundation; either version 2 of the License, or
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; (at your option) any later version.
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;
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; This program is distributed in the hope that it will be useful,
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; GNU General Public License for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with this program; if not, write to the Free Software
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; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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(include "simplify.inc")
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(define-arch
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(name sh)
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(comment "Hitachi SuperH (SH)")
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(insn-lsb0? #t)
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(machs sh2 sh3 sh3e sh4 sh5)
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(isas compact media)
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)
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; Instruction sets.
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(define-isa
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(name media)
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(comment "SHmedia 32-bit instruction set")
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(base-insn-bitsize 32)
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)
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(define-isa
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(name compact)
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(comment "SHcompact 16-bit instruction set")
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(base-insn-bitsize 16)
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)
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; CPU family.
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(define-cpu
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(name sh64)
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(comment "SH 64-bit family")
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(endian either)
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(word-bitsize 32)
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)
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(define-mach
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(name sh2)
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(comment "SH-2 CPU core")
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(cpu sh64)
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(isas compact)
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)
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(define-mach
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(name sh3)
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(comment "SH-3 CPU core")
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(cpu sh64)
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(isas compact)
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)
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(define-mach
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(name sh3e)
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(comment "SH-3e CPU core")
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(cpu sh64)
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(isas compact)
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)
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(define-mach
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(name sh4)
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(comment "SH-4 CPU core")
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(cpu sh64)
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(isas compact)
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)
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(define-mach
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(name sh5)
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(comment "SH-5 CPU core")
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(cpu sh64)
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(isas compact media)
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)
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(define-model
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(name sh5)
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(comment "SH-5 reference implementation")
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(mach sh5)
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(unit u-exec "Execution unit" ()
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1 1 ; issue done
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() () () ())
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)
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; Hardware elements.
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(define-hardware
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(name h-pc)
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(comment "Program counter")
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(attrs PC (ISA compact,media))
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(type pc UDI)
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(get () (raw-reg h-pc))
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(set (newval) (sequence ()
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(set (raw-reg h-ism) (and newval 1))
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(set (raw-reg h-pc) (and newval (inv UDI 1)))))
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)
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(define-pmacro (-build-greg-name n) ((.sym r n) n))
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(define-hardware
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(name h-gr)
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(comment "General purpose integer registers")
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(attrs (ISA media,compact))
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(type register DI (64))
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(indices keyword "" (.map -build-greg-name (.iota 64)))
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(get (index)
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(if DI (eq index 63)
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(const 0)
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(raw-reg h-gr index)))
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(set (index newval)
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(if (ne index 63)
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(set (raw-reg h-gr index) newval)
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(nop)))
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)
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(define-hardware
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(name h-grc)
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(comment "General purpose integer registers (SHcompact view)")
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(attrs VIRTUAL (ISA compact))
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(type register SI (16))
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(indices keyword "" (.map -build-greg-name (.iota 16)))
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(get (index)
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(and (raw-reg h-gr index) (zext DI #xFFFFFFFF)))
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(set (index newval)
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(set (raw-reg h-gr index) (ext DI newval)))
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)
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(define-pmacro (-build-creg-name n) ((.sym cr n) n))
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(define-hardware
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(name h-cr)
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(comment "Control registers")
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(attrs (ISA media))
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(type register DI (64))
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(indices keyword "" (.map -build-creg-name (.iota 64)))
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(get (index)
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(if DI (eq index 0)
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(zext DI (reg h-sr))
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(raw-reg h-cr index)))
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(set (index newval)
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(if (eq index 0)
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(set (reg h-sr) newval)
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(set (raw-reg h-cr index) newval)))
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)
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(define-hardware
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(name h-sr)
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(comment "Status register")
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(attrs (ISA compact,media))
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(type register SI)
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)
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(define-hardware
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(name h-fpscr)
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(comment "Floating point status and control register")
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(attrs (ISA compact,media))
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(type register SI)
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)
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(define-hardware
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(name h-frbit)
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(comment "Floating point register file bit")
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(attrs (ISA media,compact) VIRTUAL)
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(type register BI)
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(get () (and (srl (reg h-sr) 14) 1))
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(set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 14))) (sll SI newvalue 14))))
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)
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(define-hardware
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(name h-szbit)
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(comment "Floating point transfer size bit")
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(attrs (ISA media,compact) VIRTUAL)
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(type register BI)
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(get () (and (srl (reg h-sr) 13) 1))
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(set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 13))) (sll SI newvalue 13))))
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)
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(define-hardware
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(name h-prbit)
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(comment "Floating point precision bit")
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(attrs (ISA media,compact) VIRTUAL)
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(type register BI)
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(get () (and (srl (reg h-sr) 12) 1))
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(set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 12))) (sll SI newvalue 12))))
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)
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(define-hardware
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(name h-sbit)
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(comment "Multiply-accumulate saturation flag")
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(attrs (ISA compact) VIRTUAL)
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(type register BI)
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(get () (and (srl (reg h-sr) 1) 1))
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(set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv 2)) (sll SI newvalue 1))))
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)
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(define-hardware
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(name h-mbit)
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(comment "Divide-step M flag")
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(attrs (ISA compact) VIRTUAL)
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(type register BI)
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(get () (and (srl (reg h-sr) 9) 1))
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(set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 9))) (sll SI newvalue 9))))
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)
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(define-hardware
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(name h-qbit)
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(comment "Divide-step Q flag")
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(attrs (ISA compact) VIRTUAL)
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(type register BI)
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(get () (and (srl (reg h-sr) 8) 1))
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(set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 8))) (sll SI newvalue 8))))
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)
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(define-pmacro (-build-freg-name n) ((.sym fr n) n))
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(define-hardware
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(name h-fr)
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(comment "Single precision floating point registers")
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(attrs (ISA media,compact))
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(type register SF (64))
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(indices keyword "" (.map -build-freg-name (.iota 64)))
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)
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(define-pmacro (-build-fpair-name n) ((.sym fp n) n))
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(define-hardware
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(name h-fp)
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(comment "Single precision floating point register pairs")
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(attrs (ISA media,compact))
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(type register DF (32))
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(indices keyword "" (.map -build-fpair-name (.iota 32)))
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)
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(define-pmacro (-build-fvec-name n) ((.sym fv n) n))
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(define-hardware
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(name h-fv)
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(comment "Single precision floating point vectors")
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(attrs VIRTUAL (ISA media,compact))
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(type register SF (16))
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(indices keyword "" (.map -build-fvec-name (.iota 16)))
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; Mask with $F to ensure 0 <= index < 15.
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(get (index) (reg h-fr (mul (and UQI index 15) 4)))
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(set (index newval) (set (reg h-fr (mul (and UQI index 15) 4)) newval))
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)
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(define-hardware
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(name h-fmtx)
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(comment "Single precision floating point matrices")
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(attrs VIRTUAL (ISA media))
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(type register SF (4))
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(indices keyword "" ((mtrx0 0) (mtrx1 1) (mtrx2 2) (mtrx3 3)))
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; Mask with $3 to ensure 0 <= index < 4.
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(get (index) (reg h-fr (mul (and UQI index 3) 16)))
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(set (index newval) (set (reg h-fr (mul (and UQI index 3) 16)) newval))
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)
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(define-pmacro (-build-dreg-name n) ((.sym dr n) n))
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(define-hardware
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(name h-dr)
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(comment "Double precision floating point registers")
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(attrs (ISA media,compact) VIRTUAL)
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(type register DF (32))
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(indices keyword "" (.map -build-dreg-name (.iota 64)))
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(get (index)
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(subword DF
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(or
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(sll DI (zext DI (subword SI (reg h-fr index) 0)) 32)
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(zext DI (subword SI (reg h-fr (add index 1)) 0))) 0))
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(set (index newval)
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(sequence ()
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(set (reg h-fr index)
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(subword SF (subword SI newval 0) 0))
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(set (reg h-fr (add index 1))
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(subword SF (subword SI newval 1) 0))))
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)
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(define-hardware
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(name h-tr)
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(comment "Branch target registers")
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(attrs (ISA media))
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(type register DI (8))
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(indices keyword "" ((tr0 0) (tr1 1) (tr2 2) (tr3 3) (tr4 4) (tr5 5) (tr6 6) (tr7 7)))
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)
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(define-hardware
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(name h-endian)
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(comment "Current endian mode")
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(attrs (ISA compact,media) VIRTUAL)
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(type register BI)
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(get () (c-call BI "sh64_endian"))
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(set (newval) (error "cannot alter target byte order mid-program"))
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)
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(define-hardware
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(name h-ism)
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(comment "Current instruction set mode")
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(attrs (ISA compact,media))
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(type register BI)
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(get () (raw-reg h-ism))
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(set (newval) (error "cannot set ism directly"))
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)
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; Operands.
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(dnop endian "Endian mode" ((ISA compact,media)) h-endian f-nil)
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(dnop ism "Instruction set mode" ((ISA compact,media)) h-ism f-nil)
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; Universally useful macros.
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; A pmacro for use in semantic bodies of unimplemented insns.
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(define-pmacro (unimp mnemonic) (nop))
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; Join 2 ints together in natural bit order.
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(define-pmacro (-join-si s1 s0)
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(or (sll (zext DI s1) 32)
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(zext DI s0)))
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; Join 4 half-ints together in natural bit order.
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(define-pmacro (-join-hi h3 h2 h1 h0)
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(or (sll (zext DI h3) 48)
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(or (sll (zext DI h2) 32)
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(or (sll (zext DI h1) 16)
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(zext DI h0)))))
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; Join 8 quarter-ints together in natural bit order.
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(define-pmacro (-join-qi b7 b6 b5 b4 b3 b2 b1 b0)
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(or (sll (zext DI b7) 56)
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(or (sll (zext DI b6) 48)
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(or (sll (zext DI b5) 40)
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(or (sll (zext DI b4) 32)
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(or (sll (zext DI b3) 24)
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(or (sll (zext DI b2) 16)
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(or (sll (zext DI b1) 8)
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(zext DI b0)))))))))
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; Include the two instruction set descriptions from their respective
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; source files.
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(if (keep-isa? (compact))
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(include "sh64-compact.cpu"))
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(if (keep-isa? (media))
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(include "sh64-media.cpu"))
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@ -0,0 +1,78 @@
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/* SHmedia opcode support. -*- C -*-
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Copyright 2000 Free Software Foundation, Inc.
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Contributed by Red Hat Inc; developed under contract from Hitachi
|
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Semiconductor (America) Inc.
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||||
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This file is part of the GNU Binutils.
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This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/* This file is an addendum to sh-media.cpu. Heavy use of C code isn't
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appropriate in .cpu files, so it resides here. This especially applies
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to assembly/disassembly where parsing/printing can be quite involved.
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Such things aren't really part of the specification of the cpu, per se,
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so .cpu files provide the general framework and .opc files handle the
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nitty-gritty details as necessary.
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Each section is delimited with start and end markers.
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<arch>-opc.h additions use: "-- opc.h"
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<arch>-opc.c additions use: "-- opc.c"
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<arch>-asm.c additions use: "-- asm.c"
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<arch>-dis.c additions use: "-- dis.c"
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<arch>-ibd.h additions use: "-- ibd.h"
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*/
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/* -- opc.h */
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/* Allows reason codes to be output when assembler errors occur. */
|
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#define CGEN_VERBOSE_ASSEMBLER_ERRORS
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|
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/* Override disassembly hashing - there are variable bits in the top
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byte of these instructions. */
|
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#define CGEN_DIS_HASH_SIZE 8
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#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 6) % CGEN_DIS_HASH_SIZE)
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/* -- asm.c */
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static const char *
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parse_fsd (cd, strp, opindex, valuep)
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CGEN_CPU_DESC cd;
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const char **strp;
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int opindex;
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long *valuep;
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{
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abort();
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}
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/* -- dis.c */
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static void
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print_likely (cd, dis_info, value, attrs, pc, length)
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CGEN_CPU_DESC cd;
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PTR dis_info;
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long value;
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unsigned int attrs;
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bfd_vma pc;
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int length;
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{
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disassemble_info *info = (disassemble_info *) dis_info;
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(*info->fprintf_func) (info->stream, (value) ? "/l" : "/u");
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}
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/* -- */
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
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