RISC-V: Fix [dis]assembly of srai/srli
These were simple copy/paste errors from the compressed left shift pattern, which can't have a 0-register.
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@ -1,3 +1,10 @@
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2017-03-13 Andrew Waterman <andrew@sifive.com>
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* riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
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<srl> Likewise.
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<srai> Likewise.
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<sra> Likewise.
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2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (opcode_modifiers): Replace S with Load.
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@ -210,14 +210,14 @@ const struct riscv_opcode riscv_opcodes[] =
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{"sll", "C", "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, INSN_ALIAS },
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{"sll", "I", "d,s,t", MATCH_SLL, MASK_SLL, match_opcode, 0 },
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{"sll", "I", "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, INSN_ALIAS },
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{"srli", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS },
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{"srli", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_opcode, INSN_ALIAS },
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{"srli", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, 0 },
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{"srl", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS },
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{"srl", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_opcode, INSN_ALIAS },
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{"srl", "I", "d,s,t", MATCH_SRL, MASK_SRL, match_opcode, 0 },
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{"srl", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, INSN_ALIAS },
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{"srai", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS },
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{"srai", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_opcode, INSN_ALIAS },
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{"srai", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, 0 },
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{"sra", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS },
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{"sra", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_opcode, INSN_ALIAS },
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{"sra", "I", "d,s,t", MATCH_SRA, MASK_SRA, match_opcode, 0 },
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{"sra", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, INSN_ALIAS },
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{"sub", "C", "Cs,Cw,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, INSN_ALIAS },
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