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[GAS, ARM] Invalid LDR immediate transformation

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2015-11-24  Christophe Monat <christophe.monat@st.com>

	* config/tc-arm.c (move_or_literal_pool): Do not transform ldr
	ri,=imm into movs when ri is a high register in T1.

2015-11-24  Christophe Monat <christophe.monat@st.com>

	* gas/arm/thumb2_ldr_immediate_armv6t2.s: Added high register
	tests.
	* gas/arm/thumb2_ldr_immediate_armv6t2.d: Accounted for new test
	cases.
	* gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s: New.
	* gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d: New.
This commit is contained in:
Christophe Monat 2015-11-24 22:17:54 +01:00 committed by Christophe Lyon
parent be81798bb6
commit 2c32be708d
7 changed files with 78 additions and 3 deletions
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5
gas/ChangeLog
View File

@ -1,3 +1,8 @@
2015-11-24 Christophe Monat <christophe.monat@st.com>
* config/tc-arm.c (move_or_literal_pool): Do not transform ldr
ri,=imm into movs when ri is a high register in T1.
2015-11-20 Nick Clifton <nickc@redhat.com>
* po/fr.po: Updated French translation.

3
gas/config/tc-arm.c
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@ -7839,7 +7839,8 @@ move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
{
if (thumb_p)
{
if ((v & ~0xFF) == 0)
/* This can be encoded only for a low register. */
if ((v & ~0xFF) == 0 && (inst.operands[i].reg < 8))
{
/* This can be done with a mov(1) instruction. */
inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);

9
gas/testsuite/ChangeLog
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@ -1,3 +1,12 @@
2015-11-24 Christophe Monat <christophe.monat@st.com>
* gas/arm/thumb2_ldr_immediate_armv6t2.s: Added high register
tests.
* gas/arm/thumb2_ldr_immediate_armv6t2.d: Accounted for new test
cases.
* gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s: New.
* gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d: New.
2015-11-24 Matthew Wahab <matthew.wahab@arm.com>
* gas/arm/armv7e-m+fpv5-d16.d: Skip test for *-*-pe, *-wince-* and

10
gas/testsuite/gas/arm/thumb2_ldr_immediate_armv6t2.d
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@ -1,4 +1,4 @@
# name: Ldr immediate on armv6
# name: Ldr immediate on armv6t2
# as: -march=armv6t2
# objdump: -dr --prefix-addresses --show-raw-insn
#skip: *-*-pe *-wince-* *-*-coff
@ -10,7 +10,13 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f04f 2163 mov.w r1, #1660969728 .*
0[0-9a-f]+ <[^>]+> f04f 1151 mov.w r1, #5308497 .*
0[0-9a-f]+ <[^>]+> f44f 228e mov.w r2, #290816 .*
0[0-9a-f]+ <[^>]+> 4a01 ldr r2, \[pc, #4\] .*
0[0-9a-f]+ <[^>]+> 4a07 ldr r2, \[pc, #28\] .*
0[0-9a-f]+ <[^>]+> f241 32f1 movw r2, #5105 .*
0[0-9a-f]+ <[^>]+> f04f 3872 mov.w r8, #1920103026 .*
0[0-9a-f]+ <[^>]+> f04f 2863 mov.w r8, #1660969728 .*
0[0-9a-f]+ <[^>]+> f04f 1851 mov.w r8, #5308497 .*
0[0-9a-f]+ <[^>]+> f44f 298e mov.w r9, #290816 .*
0[0-9a-f]+ <[^>]+> f8df 9008 ldr.w r9, \[pc, #8\] .*
0[0-9a-f]+ <[^>]+> f241 39f1 movw r9, #5105 .*
0[0-9a-f]+ <[^>]+> 0000 .short 0x0000
0[0-9a-f]+ <[^>]+> ff320000 .word 0xff320000

6
gas/testsuite/gas/arm/thumb2_ldr_immediate_armv6t2.s
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@ -9,4 +9,10 @@ thumb2_ldr:
ldr r2,=0x00047000
ldr r2,=0xFF320000
ldr r2,=0x000013F1
ldr r8,=0x72727272
ldr r8,=0x63006300
ldr r8,=0x00510051
ldr r9,=0x00047000
ldr r9,=0xFF320000
ldr r9,=0x000013F1
.pool

24
gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d Normal file
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@ -0,0 +1,24 @@
# name: Ldr small immediate high registers on armv6t2
# as: -march=armv6t2
# objdump: -dr --prefix-addresses --show-raw-insn
# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
.*: +file format .*arm.*
Disassembly of section \.text:
0[0-9a-f]+ <[^>]+> 2000[[:space:]]+movs[[:space:]]+r0, #0.*
0[0-9a-f]+ <[^>]+> 2108[[:space:]]+movs[[:space:]]+r1, #8.*
0[0-9a-f]+ <[^>]+> 2251[[:space:]]+movs[[:space:]]+r2, #81.*
0[0-9a-f]+ <[^>]+> 231f[[:space:]]+movs[[:space:]]+r3, #31.*
0[0-9a-f]+ <[^>]+> 242f[[:space:]]+movs[[:space:]]+r4, #47.*
0[0-9a-f]+ <[^>]+> 253f[[:space:]]+movs[[:space:]]+r5, #63.*
0[0-9a-f]+ <[^>]+> 2680[[:space:]]+movs[[:space:]]+r6, #128.*
0[0-9a-f]+ <[^>]+> 27ff[[:space:]]+movs[[:space:]]+r7, #255.*
0[0-9a-f]+ <[^>]+> f04f 0800[[:space:]]+mov\.w[[:space:]]+r8, #0.*
0[0-9a-f]+ <[^>]+> f04f 0908[[:space:]]+mov\.w[[:space:]]+r9, #8.*
0[0-9a-f]+ <[^>]+> f04f 0a51[[:space:]]+mov\.w[[:space:]]+sl, #81.*
0[0-9a-f]+ <[^>]+> f04f 0b1f[[:space:]]+mov\.w[[:space:]]+fp, #31.*
0[0-9a-f]+ <[^>]+> f04f 0c2f[[:space:]]+mov\.w[[:space:]]+ip, #47.*
0[0-9a-f]+ <[^>]+> f04f 0d3f[[:space:]]+mov\.w[[:space:]]+sp, #63.*
0[0-9a-f]+ <[^>]+> f04f 0e80[[:space:]]+mov\.w[[:space:]]+lr, #128.*
0[0-9a-f]+ <[^>]+> f04f 0fff[[:space:]]+mov\.w[[:space:]]+pc, #255.*

24
gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s Normal file
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@ -0,0 +1,24 @@
.thumb
.syntax unified
.thumb_func
thumb2_ldr:
# These can be encoded into movs since constant is small
# And register can be encoded in 3 bits
ldr r0,=0x00
ldr r1,=0x08
ldr r2,=0x51
ldr r3,=0x1F
ldr r4,=0x2F
ldr r5,=0x3F
ldr r6,=0x80
ldr r7,=0xFF
# These shall be encoded into mov.w
# Since register cannot be encoded in 3 bits
ldr r8,=0x00
ldr r9,=0x08
ldr r10,=0x51
ldr r11,=0x1F
ldr r12,=0x2F
ldr r13,=0x3F
ldr r14,=0x80
ldr r15,=0xFF