RISC-V: Disable the CSR checking by default.
Add new .option `csr-check/no-csr-check` and GAS option `-mcsr-check /-mno-csr-check` to enbale/disable the CSR checking. Disable the CSR checking by default. gas/ * config/tc-riscv.c: Add new .option and GAS options to enbale/disable the CSR checking. We disable the CSR checking by default. (reg_lookup_internal): Check the `riscv_opts.csr_check` before we doing the CSR checking. * doc/c-riscv.texi: Add description for the new .option and assembler options. * testsuite/gas/riscv/priv-reg-fail-fext.d: Add `-mcsr-check` to enable the CSR checking. * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
This commit is contained in:
parent
bd0cf5a6ba
commit
2ca89224b1
|
@ -1,5 +1,19 @@
|
|||
2020-02-20 Nelson Chu <nelson.chu@sifive.com>
|
||||
|
||||
* config/tc-riscv.c (struct riscv_set_options): New field csr_check.
|
||||
(riscv_opts): Initialize it.
|
||||
(reg_lookup_internal): Check the `riscv_opts.csr_check`
|
||||
before doing the CSR checking.
|
||||
(enum options): Add OPTION_CSR_CHECK and OPTION_NO_CSR_CHECK.
|
||||
(md_longopts): Add mcsr-check and mno-csr-check.
|
||||
(md_parse_option): Handle new enum option values.
|
||||
(s_riscv_option): Handle new long options.
|
||||
* doc/c-riscv.texi: Add description for the new .option and assembler
|
||||
options.
|
||||
* testsuite/gas/riscv/priv-reg-fail-fext.d: Add `-mcsr-check` to enable
|
||||
the CSR checking.
|
||||
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
|
||||
|
||||
* config/tc-riscv.c (csr_extra_hash): New.
|
||||
(enum riscv_csr_class): New enum. Used to decide
|
||||
whether or not this CSR is legal in the current ISA string.
|
||||
|
|
|
@ -83,6 +83,7 @@ struct riscv_set_options
|
|||
int rve; /* Generate RVE code. */
|
||||
int relax; /* Emit relocs the linker is allowed to relax. */
|
||||
int arch_attr; /* Emit arch attribute. */
|
||||
int csr_check; /* Enable the CSR checking. */
|
||||
};
|
||||
|
||||
static struct riscv_set_options riscv_opts =
|
||||
|
@ -92,6 +93,7 @@ static struct riscv_set_options riscv_opts =
|
|||
0, /* rve */
|
||||
1, /* relax */
|
||||
DEFAULT_RISCV_ATTR, /* arch_attr */
|
||||
0. /* csr_check */
|
||||
};
|
||||
|
||||
static void
|
||||
|
@ -572,7 +574,9 @@ reg_lookup_internal (const char *s, enum reg_class class)
|
|||
if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
|
||||
return -1;
|
||||
|
||||
if (class == RCLASS_CSR && !reg_csr_lookup_internal (s))
|
||||
if (class == RCLASS_CSR
|
||||
&& riscv_opts.csr_check
|
||||
&& !reg_csr_lookup_internal (s))
|
||||
return -1;
|
||||
|
||||
return DECODE_REG_NUM (r);
|
||||
|
@ -2272,6 +2276,8 @@ enum options
|
|||
OPTION_NO_RELAX,
|
||||
OPTION_ARCH_ATTR,
|
||||
OPTION_NO_ARCH_ATTR,
|
||||
OPTION_CSR_CHECK,
|
||||
OPTION_NO_CSR_CHECK,
|
||||
OPTION_END_OF_ENUM
|
||||
};
|
||||
|
||||
|
@ -2286,6 +2292,8 @@ struct option md_longopts[] =
|
|||
{"mno-relax", no_argument, NULL, OPTION_NO_RELAX},
|
||||
{"march-attr", no_argument, NULL, OPTION_ARCH_ATTR},
|
||||
{"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR},
|
||||
{"mcsr-check", no_argument, NULL, OPTION_CSR_CHECK},
|
||||
{"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK},
|
||||
|
||||
{NULL, no_argument, NULL, 0}
|
||||
};
|
||||
|
@ -2364,6 +2372,14 @@ md_parse_option (int c, const char *arg)
|
|||
riscv_opts.arch_attr = FALSE;
|
||||
break;
|
||||
|
||||
case OPTION_CSR_CHECK:
|
||||
riscv_opts.csr_check = TRUE;
|
||||
break;
|
||||
|
||||
case OPTION_NO_CSR_CHECK:
|
||||
riscv_opts.csr_check = FALSE;
|
||||
break;
|
||||
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
@ -2756,6 +2772,10 @@ s_riscv_option (int x ATTRIBUTE_UNUSED)
|
|||
riscv_opts.relax = TRUE;
|
||||
else if (strcmp (name, "norelax") == 0)
|
||||
riscv_opts.relax = FALSE;
|
||||
else if (strcmp (name, "csr-check") == 0)
|
||||
riscv_opts.csr_check = TRUE;
|
||||
else if (strcmp (name, "no-csr-check") == 0)
|
||||
riscv_opts.csr_check = FALSE;
|
||||
else if (strcmp (name, "push") == 0)
|
||||
{
|
||||
struct riscv_option_stack *s;
|
||||
|
|
|
@ -73,6 +73,15 @@ specification.
|
|||
Don't generate the default riscv elf attribute section if the .attribute
|
||||
directives are not set.
|
||||
|
||||
@cindex @samp{-mcsr-check} option, RISC-V
|
||||
@item -mcsr-check
|
||||
Enable the CSR checking for the ISA-dependent CRS and the read-only CSR.
|
||||
The ISA-dependent CSR are only valid when the specific ISA is set. The
|
||||
read-only CSR can not be written by the CSR instructions.
|
||||
|
||||
@cindex @samp{-mno-csr-check} option, RISC-V
|
||||
@item -mno-csr-check
|
||||
Don't do CSR cheching.
|
||||
@end table
|
||||
@c man end
|
||||
|
||||
|
@ -174,6 +183,10 @@ opportunistically relax some code sequences, but sometimes this behavior is not
|
|||
desirable.
|
||||
@end table
|
||||
|
||||
@item csr-check
|
||||
@itemx no-csr-check
|
||||
Enables or disables the CSR checking.
|
||||
|
||||
@cindex INSN directives
|
||||
@item .insn @var{value}
|
||||
@itemx .insn @var{value}
|
||||
|
|
|
@ -1,3 +1,3 @@
|
|||
#as: -march=rv32i
|
||||
#as: -march=rv32i -mcsr-check
|
||||
#source: priv-reg.s
|
||||
#warning_output: priv-reg-fail-fext.l
|
||||
|
|
|
@ -1,3 +1,3 @@
|
|||
#as: -march=rv64if
|
||||
#as: -march=rv64if -mcsr-check
|
||||
#source: priv-reg.s
|
||||
#warning_output: priv-reg-fail-rv32-only.l
|
||||
|
|
Loading…
Reference in New Issue