x86: Handle {disp32} for (%bp)/(%ebp)/(%rbp)
Since (%bp)/(%ebp)/(%rbp) are encoded as 0(%bp)/0(%ebp)/0(%rbp), use
disp32/disp16 on 0(%bp)/0(%ebp)/0(%rbp) for {disp32}.
Note: Since there is no disp32 on 0(%bp), use disp16 instead.
PR gas/26305
* config/tc-i386.c (build_modrm_byte): Use disp32/disp16 on
(%bp)/(%ebp)/(%rbp) for {disp32}.
* doc/c-i386.texi: Update {disp32} documentation.
* testsuite/gas/i386/pseudos.s: Add (%bp)/(%ebp) tests.
* testsuite/gas/i386/x86-64-pseudos.s: Add (%ebp)/(%rbp) tests.
* testsuite/gas/i386/pseudos.d: Updated.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
(cherry picked from commit 1a02d6b0ff80048df106cbb776a550278f8c9d9c)
This commit is contained in:
H.J. Lu
parent
c4747a6a57
commit
2cd5bade18
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@ -1,3 +1,14 @@
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2020-07-28 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/26305
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* config/tc-i386.c (build_modrm_byte): Use disp32/disp16 on
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(%bp)/(%ebp)/(%rbp) for {disp32}.
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* doc/c-i386.texi: Update {disp32} documentation.
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* testsuite/gas/i386/pseudos.s: Add (%bp)/(%ebp) tests.
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* testsuite/gas/i386/x86-64-pseudos.s: Add (%ebp)/(%rbp) tests.
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* testsuite/gas/i386/pseudos.d: Updated.
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* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
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2020-07-24 Nick Clifton <nickc@redhat.com>
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* configure: Regenerate.
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@ -8084,7 +8084,12 @@ build_modrm_byte (void)
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if (operand_type_check (i.types[op], disp) == 0)
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{
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/* fake (%bp) into 0(%bp) */
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i.types[op].bitfield.disp8 = 1;
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if (i.disp_encoding == disp_encoding_32bit)
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/* NB: Use disp16 since there is no disp32
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in 16-bit mode. */
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i.types[op].bitfield.disp16 = 1;
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else
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i.types[op].bitfield.disp8 = 1;
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fake_zero_displacement = 1;
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}
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}
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@ -8129,7 +8134,10 @@ build_modrm_byte (void)
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if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
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{
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fake_zero_displacement = 1;
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i.types[op].bitfield.disp8 = 1;
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if (i.disp_encoding == disp_encoding_32bit)
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i.types[op].bitfield.disp32 = 1;
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else
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i.types[op].bitfield.disp8 = 1;
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}
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i.sib.scale = i.log2_scale_factor;
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if (i.index_reg == 0)
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@ -816,7 +816,7 @@ Different encoding options can be specified via pseudo prefixes:
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@samp{@{disp8@}} -- prefer 8-bit displacement.
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@item
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@samp{@{disp32@}} -- prefer 32-bit displacement.
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@samp{@{disp32@}} -- prefer 32-bit (16-bit in 16-bit mode) displacement.
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@item
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@samp{@{load@}} -- prefer load-form instruction.
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@ -288,6 +288,15 @@ Disassembly of section .text:
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+[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2
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+[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2
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+[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2
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+[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al
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+[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al
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+[a-f0-9]+: 8a 85 00 00 00 00 mov 0x0\(%ebp\),%al
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+[a-f0-9]+: 67 8a 07 mov \(%bx\),%al
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+[a-f0-9]+: 67 8a 07 mov \(%bx\),%al
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+[a-f0-9]+: 67 8a 07 mov \(%bx\),%al
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+[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al
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+[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al
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+[a-f0-9]+: 67 8a 86 00 00 mov 0x0\(%bp\),%al
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+[a-f0-9]+: c4 e1 78 28 d7 vmovaps %xmm7,%xmm2
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+[a-f0-9]+: c4 e1 78 28 d7 vmovaps %xmm7,%xmm2
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+[a-f0-9]+: c4 e1 78 29 fa vmovaps %xmm7,%xmm2
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@ -316,4 +325,13 @@ Disassembly of section .text:
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+[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2
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+[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2
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+[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2
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+[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al
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+[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al
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+[a-f0-9]+: 8a 85 00 00 00 00 mov 0x0\(%ebp\),%al
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+[a-f0-9]+: 67 8a 07 mov \(%bx\),%al
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+[a-f0-9]+: 67 8a 07 mov \(%bx\),%al
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+[a-f0-9]+: 67 8a 07 mov \(%bx\),%al
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+[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al
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+[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al
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+[a-f0-9]+: 67 8a 86 00 00 mov 0x0\(%bp\),%al
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#pass
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@ -293,6 +293,18 @@ _start:
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{disp8} movaps 128(%eax),%xmm2
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{disp32} movaps 128(%eax),%xmm2
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movb (%ebp),%al
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{disp8} movb (%ebp),%al
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{disp32} movb (%ebp),%al
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movb (%bx),%al
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{disp8} movb (%bx),%al
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{disp32} movb (%bx),%al
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movb (%bp),%al
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{disp8} movb (%bp),%al
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{disp32} movb (%bp),%al
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.intel_syntax noprefix
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{vex3} vmovaps xmm2,xmm7
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{vex3} {load} vmovaps xmm2,xmm7
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@ -322,3 +334,15 @@ _start:
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movaps xmm2,XMMWORD PTR [eax+128]
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{disp8} movaps xmm2,XMMWORD PTR [eax+128]
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{disp32} movaps xmm2,XMMWORD PTR [eax+128]
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mov al, BYTE PTR [ebp]
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{disp8} mov al, BYTE PTR [ebp]
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{disp32} mov al, BYTE PTR [ebp]
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mov al, BYTE PTR [bx]
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{disp8} mov al, BYTE PTR [bx]
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{disp32} mov al, BYTE PTR [bx]
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mov al, BYTE PTR [bp]
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{disp8} mov al, BYTE PTR [bp]
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{disp32} mov al, BYTE PTR [bp]
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@ -310,6 +310,12 @@ Disassembly of section .text:
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+[a-f0-9]+: 41 0f 28 10 movaps \(%r8\),%xmm2
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+[a-f0-9]+: 40 0f 38 01 01 rex phaddw \(%rcx\),%mm0
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+[a-f0-9]+: 41 0f 38 01 00 phaddw \(%r8\),%mm0
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+[a-f0-9]+: 8a 45 00 mov 0x0\(%rbp\),%al
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+[a-f0-9]+: 8a 45 00 mov 0x0\(%rbp\),%al
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+[a-f0-9]+: 8a 85 00 00 00 00 mov 0x0\(%rbp\),%al
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+[a-f0-9]+: 67 8a 45 00 mov 0x0\(%ebp\),%al
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+[a-f0-9]+: 67 8a 45 00 mov 0x0\(%ebp\),%al
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+[a-f0-9]+: 67 8a 85 00 00 00 00 mov 0x0\(%ebp\),%al
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+[a-f0-9]+: c4 e1 78 28 d7 vmovaps %xmm7,%xmm2
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+[a-f0-9]+: c4 e1 78 28 d7 vmovaps %xmm7,%xmm2
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+[a-f0-9]+: c4 e1 78 29 fa vmovaps %xmm7,%xmm2
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@ -348,4 +354,10 @@ Disassembly of section .text:
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+[a-f0-9]+: 41 0f 28 10 movaps \(%r8\),%xmm2
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+[a-f0-9]+: 40 0f 38 01 01 rex phaddw \(%rcx\),%mm0
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+[a-f0-9]+: 41 0f 38 01 00 phaddw \(%r8\),%mm0
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+[a-f0-9]+: 8a 45 00 mov 0x0\(%rbp\),%al
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+[a-f0-9]+: 8a 45 00 mov 0x0\(%rbp\),%al
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+[a-f0-9]+: 8a 85 00 00 00 00 mov 0x0\(%rbp\),%al
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+[a-f0-9]+: 67 8a 45 00 mov 0x0\(%ebp\),%al
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+[a-f0-9]+: 67 8a 45 00 mov 0x0\(%ebp\),%al
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+[a-f0-9]+: 67 8a 85 00 00 00 00 mov 0x0\(%ebp\),%al
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#pass
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@ -315,6 +315,14 @@ _start:
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{rex} phaddw (%rcx),%mm0
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{rex} phaddw (%r8),%mm0
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movb (%rbp),%al
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{disp8} movb (%rbp),%al
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{disp32} movb (%rbp),%al
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movb (%ebp),%al
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{disp8} movb (%ebp),%al
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{disp32} movb (%ebp),%al
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.intel_syntax noprefix
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{vex3} vmovaps xmm2,xmm7
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{vex3} {load} vmovaps xmm2,xmm7
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@ -354,3 +362,11 @@ _start:
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{rex} movaps xmm2,XMMWORD PTR [r8]
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{rex} phaddw mm0,QWORD PTR [rcx]
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{rex} phaddw mm0,QWORD PTR [r8]
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mov al, BYTE PTR [rbp]
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{disp8} mov al, BYTE PTR [rbp]
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{disp32} mov al, BYTE PTR [rbp]
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mov al, BYTE PTR [ebp]
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{disp8} mov al, BYTE PTR [ebp]
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{disp32} mov al, BYTE PTR [ebp]
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