[PATCH 24/57][Arm][GAS] Add support for MVE instructions: vmlas, vmulh and vrmulh
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_mve_vmlas): New encoding function. (do_mve_vmulh): Likewise. (insns): Add entries for MVE mnemonics. * testsuite/gas/arm/mve-vmlas-bad.d: New test. * testsuite/gas/arm/mve-vmlas-bad.l: New test. * testsuite/gas/arm/mve-vmlas-bad.s: New test. * testsuite/gas/arm/mve-vmulh-bad.d: New test. * testsuite/gas/arm/mve-vmulh-bad.l: New test. * testsuite/gas/arm/mve-vmulh-bad.s: New test.
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@ -1,3 +1,15 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (do_mve_vmlas): New encoding function.
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(do_mve_vmulh): Likewise.
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(insns): Add entries for MVE mnemonics.
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* testsuite/gas/arm/mve-vmlas-bad.d: New test.
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* testsuite/gas/arm/mve-vmlas-bad.l: New test.
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* testsuite/gas/arm/mve-vmlas-bad.s: New test.
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* testsuite/gas/arm/mve-vmulh-bad.d: New test.
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* testsuite/gas/arm/mve-vmulh-bad.l: New test.
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* testsuite/gas/arm/mve-vmulh-bad.s: New test.
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/tc-arm.c (enum operand_parse_code): New operand.
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@ -15704,6 +15704,33 @@ do_mve_viddup (void)
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inst.is_neon = 1;
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}
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static void
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do_mve_vmlas (void)
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{
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enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
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struct neon_type_el et
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= neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
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if (inst.operands[2].reg == REG_PC)
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as_tsktsk (MVE_BAD_PC);
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else if (inst.operands[2].reg == REG_SP)
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as_tsktsk (MVE_BAD_SP);
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if (inst.cond > COND_ALWAYS)
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inst.pred_insn_type = INSIDE_VPT_INSN;
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else
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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inst.instruction |= (et.type == NT_unsigned) << 28;
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inst.instruction |= HI1 (inst.operands[0].reg) << 22;
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inst.instruction |= neon_logbits (et.size) << 20;
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inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
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inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
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inst.instruction |= HI1 (inst.operands[1].reg) << 7;
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inst.instruction |= inst.operands[2].reg;
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inst.is_neon = 1;
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}
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static void
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do_mve_vmaxnma_vminnma (void)
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{
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@ -17235,6 +17262,21 @@ do_mve_vsbc (void)
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mve_encode_qqq (1, 64);
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}
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static void
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do_mve_vmulh (void)
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{
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enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
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struct neon_type_el et
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= neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
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if (inst.cond > COND_ALWAYS)
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inst.pred_insn_type = INSIDE_VPT_INSN;
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else
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inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
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mve_encode_qqq (et.type == NT_unsigned, et.size);
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}
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static void
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do_mve_vmull (void)
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{
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@ -24649,6 +24691,10 @@ static const struct asm_opcode insns[] =
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mCEF(vrmlsldavhx, _vrmlsldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
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mCEF(vrmlsldavhax, _vrmlsldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
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mToC("vmlas", ee011e40, 3, (RMQ, RMQ, RR), mve_vmlas),
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mToC("vmulh", ee010e01, 3, (RMQ, RMQ, RMQ), mve_vmulh),
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mToC("vrmulh", ee011e01, 3, (RMQ, RMQ, RMQ), mve_vmulh),
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & mve_fp_ext
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mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul),
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@ -0,0 +1,5 @@
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#name: Bad MVE VMLAS instructions
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#as: -march=armv8.1-m.main+mve
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#error_output: mve-vmlas-bad.l
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.*: +file format .*arm.*
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@ -0,0 +1,16 @@
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[^:]*: Assembler messages:
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[^:]*:10: Error: bad type in SIMD instruction -- `vmlas.s64 q0,q1,r2'
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[^:]*:11: Error: bad type in SIMD instruction -- `vmlas.f32 q0,q1,r2'
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[^:]*:12: Warning: instruction is UNPREDICTABLE with SP operand
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[^:]*:13: Warning: instruction is UNPREDICTABLE with PC operand
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:16: Error: syntax error -- `vmlaseq.s16 q0,q1,r2'
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[^:]*:17: Error: syntax error -- `vmlaseq.s16 q0,q1,r2'
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[^:]*:19: Error: syntax error -- `vmlaseq.s16 q0,q1,r2'
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[^:]*:20: Error: vector predicated instruction should be in VPT/VPST block -- `vmlast.s16 q0,q1,r2'
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[^:]*:22: Error: instruction missing MVE vector predication code -- `vmlas.s16 q0,q1,r2'
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@ -0,0 +1,22 @@
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.macro cond
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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vmlas.s16 q0, q1, r2
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.endr
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.endm
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.syntax unified
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.thumb
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vmlas.s64 q0, q1, r2
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vmlas.f32 q0, q1, r2
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vmlas.u32 q0, q1, sp
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vmlas.u32 q0, q1, pc
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cond
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it eq
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vmlaseq.s16 q0, q1, r2
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vmlaseq.s16 q0, q1, r2
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vpst
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vmlaseq.s16 q0, q1, r2
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vmlast.s16 q0, q1, r2
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vpst
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vmlas.s16 q0, q1, r2
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@ -0,0 +1,5 @@
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#name: bad MVE VMULH and VRMULH instructions
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#as: -march=armv8.1-m.main+mve.fp
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#error_output: mve-vmulh-bad.l
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.*: +file format .*arm.*
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@ -0,0 +1,29 @@
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[^:]*: Assembler messages:
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[^:]*:10: Error: bad type in SIMD instruction -- `vmulh.f16 q0,q1,q2'
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[^:]*:11: Error: bad type in SIMD instruction -- `vmulh.i32 q0,q1,q2'
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[^:]*:12: Error: bad type in SIMD instruction -- `vmulh.s64 q0,q1,q2'
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[^:]*:13: Error: bad type in SIMD instruction -- `vrmulh.f16 q0,q1,q2'
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[^:]*:14: Error: bad type in SIMD instruction -- `vrmulh.i32 q0,q1,q2'
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[^:]*:15: Error: bad type in SIMD instruction -- `vrmulh.s64 q0,q1,q2'
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[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
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[^:]*:19: Error: syntax error -- `vmulheq.s16 q0,q1,q2'
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[^:]*:20: Error: syntax error -- `vmulheq.s16 q0,q1,q2'
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[^:]*:22: Error: syntax error -- `vmulheq.s16 q0,q1,q2'
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[^:]*:23: Error: vector predicated instruction should be in VPT/VPST block -- `vmulht.s16 q0,q1,q2'
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[^:]*:25: Error: instruction missing MVE vector predication code -- `vmulh.s16 q0,q1,q2'
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[^:]*:27: Error: syntax error -- `vrmulheq.s16 q0,q1,q2'
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[^:]*:28: Error: syntax error -- `vrmulheq.s16 q0,q1,q2'
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[^:]*:30: Error: syntax error -- `vrmulheq.s16 q0,q1,q2'
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[^:]*:31: Error: vector predicated instruction should be in VPT/VPST block -- `vrmulht.s16 q0,q1,q2'
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[^:]*:33: Error: instruction missing MVE vector predication code -- `vrmulh.s16 q0,q1,q2'
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@ -0,0 +1,33 @@
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.macro cond op
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.irp cond, eq, ne, gt, ge, lt, le
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it \cond
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\op\().u16 q0, q1, q2
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.endr
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.endm
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.syntax unified
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.thumb
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vmulh.f16 q0, q1, q2
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vmulh.i32 q0, q1, q2
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vmulh.s64 q0, q1, q2
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vrmulh.f16 q0, q1, q2
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vrmulh.i32 q0, q1, q2
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vrmulh.s64 q0, q1, q2
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cond vmulh
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cond vrmulh
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it eq
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vmulheq.s16 q0, q1, q2
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vmulheq.s16 q0, q1, q2
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vpst
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vmulheq.s16 q0, q1, q2
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vmulht.s16 q0, q1, q2
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vpst
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vmulh.s16 q0, q1, q2
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it eq
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vrmulheq.s16 q0, q1, q2
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vrmulheq.s16 q0, q1, q2
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vpst
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vrmulheq.s16 q0, q1, q2
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vrmulht.s16 q0, q1, q2
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vpst
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vrmulh.s16 q0, q1, q2
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