2007-10-09 Markus Deuling <deuling@de.ibm.com>
* xtensa-tdep.c: Replace following current-gdbarch based macros by their expression: (xtensa_pseudo_register_read) (xtensa_pseudo_register_write): XTENSA_TARGET_FLAGS. (ARG_NOF, ARG_1ST, xtensa_extract_return_value) (xtensa_store_return_value, xtensa_push_dummy_call): CALL_ABI. (xtensa_pseudo_register_read) (xtensa_pseudo_register_write): ISA_USE_WINDOWED_REGISTERS. (xtensa_breakpoint_from_pc): ISA_USE_DENSITY_INSTRUCTIONS. (xtensa_register_type, xtensa_supply_gregset, xtensa_frame_cache) (xtensa_frame_prev_register): NUM_AREGS. (xtensa_pseudo_register_read, xtensa_pseudo_register_write, (xtensa_supply_gregset, xtensa_frame_cache, xtensa_frame_prev_register, (xtensa_extract_return_value, xtensa_store_return_value): WB_REGNUM. (xtensa_supply_gregset, xtensa_frame_cache) (xtensa_frame_prev_register): WS_REGNUM. (xtensa_supply_gregset): LBEG_REGNUM, LEND_REGNUM, LCOUNT_REGNUM, SAR_REGNUM, EXCCAUSE_REGNUM, EXCVADDR_REGNUM (xtensa_register_name, xtensa_register_type, xtensa_reg_to_regnum) (xtensa_pseudo_register_read, xtensa_pseudo_register_write) (xtensa_register_reggroup_p): REGMAP. (call0_track_op): LITBASE_REGNUM. (xtensa_register_type, xtensa_reg_to_regnum, call0_frame_cache):A0_BASE (xtensa_supply_gregset, call0_frame_get_reg_at_entry) (xtensa_frame_prev_register, AREG_NUMBER) (xtensa_register_type): AR_BASE. (xtensa_pseudo_register_read, xtensa_pseudo_register_write): FP_ALIAS. (AREG_NUMBER): AREGS_MASK, WB_MASK, A0_REGNUM. (ARG_1ST, xtensa_pseudo_register_read, xtensa_pseudo_register_write) (xtensa_frame_cache, xtensa_frame_prev_register) (xtensa_extract_return_value, xtensa_store_return_value) (xtensa_push_dummy_call, call0_frame_cache): A0_REGNUM. (xtensa_register_type, xtensa_pseudo_register_read, xtensa_frame_cache) (xtensa_pseudo_register_write, xtensa_unwind_dummy_id) (xtensa_frame_prev_register, xtensa_push_dummy_call) (call0_frame_cache): A1_REGNUM. (xtensa_extract_return_value, xtensa_store_return_value): A2_REGNUM. (xtensa_push_dummy_call): A4_REGNUM. (ARGS_FIRST_REG): A6_REGNUM. (xtensa_pseudo_register_read, xtensa_pseudo_register_write) (xtensa_frame_prev_register): A15_REGNUM. * xtensa-tdep.h: Delete current_gdbarch based macros after replacing them in the appropriate source file: XTENSA_TARGET_FLAGS, SPILL_LOCATION, SPILL_SIZE, CALL_ABI, NUM_AREGS, ISA_USE_WINDOWED_REGISTERS, ISA_USE_DENSITY_INSTRUCTIONS, WB_REGNUM, ISA_USE_EXCEPTIONS, ISA_USE_EXT_L32R, DEBUG_DATA_VADDR_TRAP_COUNT, DEBUG_INST_VADDR_TRAP_COUNT, ISA_MAX_INSN_SIZE, DEBUG_NUM_IBREAKS, DEBUG_NUM_DBREAKS, WS_REGNUM, LBEG_REGNUM, LEND_REGNUM, SAR_REGNUM, REGMAP, LITBASE_REGNUM, DEBUGCAUSE_REGNUM, EXCCAUSE_REGNUM, AR_BASE, EXCVADDR_REGNUM, NUM_IBREAKS, REGMAP_BYTES, NUM_CONTEXTS, FP_ALIAS, FP_LAYOUT, FP_LAYOUT_BYTES, GREGMAP, AREGS_MASK, WB_MASK, A0_REGNUM, A1_REGNUM, A2_REGNUM, A3_REGNUM, A4_REGNUM, A5_REGNUM, A6_REGNUM, A7_REGNUM, A8_REGNUM, A9_REGNUM, A10_REGNUM, A11_REGNUM, A12_REGNUM, A13_REGNUM, A14_REGNUM, A15_REGNUM.
This commit is contained in:
parent
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commit
304fe2552d
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@ -1,3 +1,60 @@
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2007-10-09 Markus Deuling <deuling@de.ibm.com>
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* xtensa-tdep.c: Replace following current-gdbarch based macros by
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their expression:
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(xtensa_pseudo_register_read)
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(xtensa_pseudo_register_write): XTENSA_TARGET_FLAGS.
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(ARG_NOF, ARG_1ST, xtensa_extract_return_value)
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(xtensa_store_return_value, xtensa_push_dummy_call): CALL_ABI.
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(xtensa_pseudo_register_read)
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(xtensa_pseudo_register_write): ISA_USE_WINDOWED_REGISTERS.
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(xtensa_breakpoint_from_pc): ISA_USE_DENSITY_INSTRUCTIONS.
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(xtensa_register_type, xtensa_supply_gregset, xtensa_frame_cache)
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(xtensa_frame_prev_register): NUM_AREGS.
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(xtensa_pseudo_register_read, xtensa_pseudo_register_write,
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(xtensa_supply_gregset, xtensa_frame_cache, xtensa_frame_prev_register,
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(xtensa_extract_return_value, xtensa_store_return_value): WB_REGNUM.
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(xtensa_supply_gregset, xtensa_frame_cache)
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(xtensa_frame_prev_register): WS_REGNUM.
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(xtensa_supply_gregset): LBEG_REGNUM, LEND_REGNUM, LCOUNT_REGNUM,
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SAR_REGNUM, EXCCAUSE_REGNUM, EXCVADDR_REGNUM
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(xtensa_register_name, xtensa_register_type, xtensa_reg_to_regnum)
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(xtensa_pseudo_register_read, xtensa_pseudo_register_write)
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(xtensa_register_reggroup_p): REGMAP.
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(call0_track_op): LITBASE_REGNUM.
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(xtensa_register_type, xtensa_reg_to_regnum, call0_frame_cache):A0_BASE
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(xtensa_supply_gregset, call0_frame_get_reg_at_entry)
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(xtensa_frame_prev_register, AREG_NUMBER)
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(xtensa_register_type): AR_BASE.
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(xtensa_pseudo_register_read, xtensa_pseudo_register_write): FP_ALIAS.
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(AREG_NUMBER): AREGS_MASK, WB_MASK, A0_REGNUM.
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(ARG_1ST, xtensa_pseudo_register_read, xtensa_pseudo_register_write)
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(xtensa_frame_cache, xtensa_frame_prev_register)
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(xtensa_extract_return_value, xtensa_store_return_value)
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(xtensa_push_dummy_call, call0_frame_cache): A0_REGNUM.
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(xtensa_register_type, xtensa_pseudo_register_read, xtensa_frame_cache)
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(xtensa_pseudo_register_write, xtensa_unwind_dummy_id)
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(xtensa_frame_prev_register, xtensa_push_dummy_call)
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(call0_frame_cache): A1_REGNUM.
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(xtensa_extract_return_value, xtensa_store_return_value): A2_REGNUM.
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(xtensa_push_dummy_call): A4_REGNUM.
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(ARGS_FIRST_REG): A6_REGNUM.
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(xtensa_pseudo_register_read, xtensa_pseudo_register_write)
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(xtensa_frame_prev_register): A15_REGNUM.
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* xtensa-tdep.h: Delete current_gdbarch based macros after replacing
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them in the appropriate source file:
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XTENSA_TARGET_FLAGS, SPILL_LOCATION, SPILL_SIZE, CALL_ABI, NUM_AREGS,
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ISA_USE_WINDOWED_REGISTERS, ISA_USE_DENSITY_INSTRUCTIONS, WB_REGNUM,
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ISA_USE_EXCEPTIONS, ISA_USE_EXT_L32R, DEBUG_DATA_VADDR_TRAP_COUNT,
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DEBUG_INST_VADDR_TRAP_COUNT, ISA_MAX_INSN_SIZE, DEBUG_NUM_IBREAKS,
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DEBUG_NUM_DBREAKS, WS_REGNUM, LBEG_REGNUM, LEND_REGNUM, SAR_REGNUM,
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REGMAP, LITBASE_REGNUM, DEBUGCAUSE_REGNUM, EXCCAUSE_REGNUM, AR_BASE,
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EXCVADDR_REGNUM, NUM_IBREAKS, REGMAP_BYTES, NUM_CONTEXTS, FP_ALIAS,
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FP_LAYOUT, FP_LAYOUT_BYTES, GREGMAP, AREGS_MASK, WB_MASK, A0_REGNUM,
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A1_REGNUM, A2_REGNUM, A3_REGNUM, A4_REGNUM, A5_REGNUM, A6_REGNUM,
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A7_REGNUM, A8_REGNUM, A9_REGNUM, A10_REGNUM, A11_REGNUM, A12_REGNUM,
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A13_REGNUM, A14_REGNUM, A15_REGNUM.
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2007-10-09 Markus Deuling <deuling@de.ibm.com>
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* h8300-tdep.c (h8300_frame_cache): Use get_frame_arch to get at
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@ -78,7 +78,7 @@ static int xtensa_debug_level = 0;
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/* On Windowed ABI, we use a6 through a11 for passing arguments
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to a function called by GDB because CALL4 is used. */
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#define ARGS_FIRST_REG A6_REGNUM
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#define ARGS_FIRST_REG gdbarch_tdep (current_gdbarch)->a0_base + 6
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#define ARGS_NUM_REGS 6
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#define REGISTER_SIZE 4
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@ -92,12 +92,18 @@ static int xtensa_debug_level = 0;
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/* Convert a live Ax register number to the corresponding Areg number. */
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#define AREG_NUMBER(r, wb) \
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((((r) - A0_REGNUM + (((wb) & WB_MASK) << WB_SHIFT)) & AREGS_MASK) + AR_BASE)
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((((r) - (gdbarch_tdep (current_gdbarch)->a0_base + 0) + (((wb) \
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& ((gdbarch_tdep (current_gdbarch)->num_aregs - 1) >> 2)) << WB_SHIFT)) & \
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(gdbarch_tdep (current_gdbarch)->num_aregs - 1)) \
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+ gdbarch_tdep (current_gdbarch)->ar_base)
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/* ABI-independent macros. */
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#define ARG_NOF (CALL_ABI == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
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#define ARG_1ST (CALL_ABI == CallAbiCall0Only \
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? (A0_REGNUM) + C0_ARGS : (ARGS_FIRST_REG))
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#define ARG_NOF (gdbarch_tdep (current_gdbarch)->call_abi \
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== CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
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#define ARG_1ST (gdbarch_tdep (current_gdbarch)->call_abi \
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== CallAbiCall0Only \
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? (gdbarch_tdep (current_gdbarch)->a0_base + 0) + C0_ARGS \
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: (ARGS_FIRST_REG))
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extern struct gdbarch_tdep *xtensa_config_tdep (struct gdbarch_info *);
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extern int xtensa_config_byte_order (struct gdbarch_info *);
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@ -180,7 +186,7 @@ xtensa_register_name (int regnum)
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/* Return the name stored in the register map. */
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if (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch)
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+ gdbarch_num_pseudo_regs (current_gdbarch))
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return REGMAP[regnum].name;
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return gdbarch_tdep (current_gdbarch)->regmap[regnum].name;
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internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum);
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return 0;
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@ -208,18 +214,22 @@ static struct type *
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xtensa_register_type (struct gdbarch *gdbarch, int regnum)
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{
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/* Return signed integer for ARx and Ax registers. */
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if ((regnum >= AR_BASE && regnum < AR_BASE + NUM_AREGS)
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|| (regnum >= A0_BASE && regnum < A0_BASE + 16))
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if ((regnum >= gdbarch_tdep (current_gdbarch)->ar_base
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&& regnum < gdbarch_tdep (current_gdbarch)->ar_base
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+ gdbarch_tdep (current_gdbarch)->num_aregs)
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|| (regnum >= gdbarch_tdep (current_gdbarch)->a0_base
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&& regnum < gdbarch_tdep (current_gdbarch)->a0_base + 16))
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return builtin_type_int;
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if (regnum == gdbarch_pc_regnum (current_gdbarch) || regnum == A1_REGNUM)
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if (regnum == gdbarch_pc_regnum (current_gdbarch)
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|| regnum == gdbarch_tdep (current_gdbarch)->a0_base + 1)
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return lookup_pointer_type (builtin_type_void);
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/* Return the stored type for all other registers. */
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else if (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch)
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+ gdbarch_num_pseudo_regs (current_gdbarch))
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{
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xtensa_register_t* reg = ®MAP[regnum];
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xtensa_register_t* reg = &gdbarch_tdep (current_gdbarch)->regmap[regnum];
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/* Set ctype for this register (only the first time). */
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@ -292,13 +302,13 @@ xtensa_reg_to_regnum (int regnum)
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int i;
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if (regnum >= 0 && regnum < 16)
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return A0_BASE + regnum;
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return gdbarch_tdep (current_gdbarch)->a0_base + regnum;
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for (i = 0;
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i < gdbarch_num_regs (current_gdbarch)
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+ gdbarch_num_pseudo_regs (current_gdbarch);
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i++)
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if (regnum == REGMAP[i].target_number)
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if (regnum == gdbarch_tdep (current_gdbarch)->regmap[i].target_number)
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return i;
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internal_error (__FILE__, __LINE__,
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DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
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regnum, xtensa_register_name (regnum));
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if (regnum == FP_ALIAS)
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regnum = A1_REGNUM;
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if (regnum == gdbarch_num_regs (current_gdbarch)
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+ gdbarch_num_pseudo_regs (current_gdbarch))
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regnum = gdbarch_tdep (current_gdbarch)->a0_base + 1;
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/* Read aliases a0..a15, if this is a Windowed ABI. */
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if (ISA_USE_WINDOWED_REGISTERS
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&& (regnum >= A0_REGNUM) && (regnum <= A15_REGNUM))
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if (gdbarch_tdep (current_gdbarch)->isa_use_windowed_registers
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&& (regnum >= gdbarch_tdep (current_gdbarch)->a0_base + 0)
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&& (regnum <= gdbarch_tdep (current_gdbarch)->a0_base + 15))
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{
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gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
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regcache_raw_read (regcache, WB_REGNUM, buf);
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regcache_raw_read (regcache,
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gdbarch_tdep (current_gdbarch)->wb_regnum, buf);
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regnum = AREG_NUMBER (regnum, extract_unsigned_integer (buf, 4));
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}
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&& regnum < gdbarch_num_regs (current_gdbarch)
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+ gdbarch_num_pseudo_regs (current_gdbarch))
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{
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xtensa_register_t *reg = ®MAP[regnum];
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xtensa_register_t *reg = &gdbarch_tdep (current_gdbarch)->regmap[regnum];
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xtensa_register_type_t type = reg->type;
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int flags = XTENSA_TARGET_FLAGS;
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int flags = gdbarch_tdep (current_gdbarch)->target_flags;
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/* We cannot read Unknown or Unmapped registers. */
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if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
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DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
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regnum, xtensa_register_name (regnum));
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if (regnum == FP_ALIAS)
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regnum = A1_REGNUM;
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if (regnum == gdbarch_num_regs (current_gdbarch)
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+ gdbarch_num_pseudo_regs (current_gdbarch))
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regnum = gdbarch_tdep (current_gdbarch)->a0_base + 1;
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/* Renumber register, if aliase a0..a15 on Windowed ABI. */
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if (ISA_USE_WINDOWED_REGISTERS
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&& (regnum >= A0_REGNUM) && (regnum <= A15_REGNUM))
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if (gdbarch_tdep (current_gdbarch)->isa_use_windowed_registers
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&& (regnum >= gdbarch_tdep (current_gdbarch)->a0_base + 0)
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&& (regnum <= gdbarch_tdep (current_gdbarch)->a0_base + 15))
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{
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gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
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unsigned int wb;
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regcache_raw_read (regcache, WB_REGNUM, buf);
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regcache_raw_read (regcache,
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gdbarch_tdep (current_gdbarch)->wb_regnum, buf);
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regnum = AREG_NUMBER (regnum, extract_unsigned_integer (buf, 4));
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}
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&& regnum < gdbarch_num_regs (current_gdbarch)
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+ gdbarch_num_pseudo_regs (current_gdbarch))
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{
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xtensa_register_t *reg = ®MAP[regnum];
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xtensa_register_t *reg = &gdbarch_tdep (current_gdbarch)->regmap[regnum];
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xtensa_register_type_t type = reg->type;
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int flags = XTENSA_TARGET_FLAGS;
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int flags = gdbarch_tdep (current_gdbarch)->target_flags;
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/* On most targets, we cannot write registers
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of type "Unknown" or "Unmapped". */
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@ -717,7 +733,7 @@ xtensa_register_reggroup_p (struct gdbarch *gdbarch,
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int regnum,
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struct reggroup *group)
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{
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xtensa_register_t* reg = ®MAP[regnum];
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xtensa_register_t* reg = &gdbarch_tdep (current_gdbarch)->regmap[regnum];
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xtensa_register_type_t type = reg->type;
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xtensa_register_group_t rg = reg->group;
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int cp_number;
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@ -776,28 +792,42 @@ xtensa_supply_gregset (const struct regset *regset,
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if (regnum == gdbarch_ps_regnum (current_gdbarch) || regnum == -1)
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regcache_raw_supply (rc, gdbarch_ps_regnum (current_gdbarch),
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(char *) ®s->ps);
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if (regnum == WB_REGNUM || regnum == -1)
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regcache_raw_supply (rc, WB_REGNUM, (char *) ®s->windowbase);
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if (regnum == WS_REGNUM || regnum == -1)
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regcache_raw_supply (rc, WS_REGNUM, (char *) ®s->windowstart);
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if (regnum == LBEG_REGNUM || regnum == -1)
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regcache_raw_supply (rc, LBEG_REGNUM, (char *) ®s->lbeg);
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if (regnum == LEND_REGNUM || regnum == -1)
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regcache_raw_supply (rc, LEND_REGNUM, (char *) ®s->lend);
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if (regnum == LCOUNT_REGNUM || regnum == -1)
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regcache_raw_supply (rc, LCOUNT_REGNUM, (char *) ®s->lcount);
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if (regnum == SAR_REGNUM || regnum == -1)
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regcache_raw_supply (rc, SAR_REGNUM, (char *) ®s->sar);
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if (regnum == EXCCAUSE_REGNUM || regnum == -1)
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regcache_raw_supply (rc, EXCCAUSE_REGNUM, (char *) ®s->exccause);
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if (regnum == EXCVADDR_REGNUM || regnum == -1)
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regcache_raw_supply (rc, EXCVADDR_REGNUM, (char *) ®s->excvaddr);
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if (regnum >= AR_BASE && regnum < AR_BASE + NUM_AREGS)
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regcache_raw_supply (rc, regnum, (char *) ®s->ar[regnum - AR_BASE]);
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if (regnum == gdbarch_tdep (current_gdbarch)->wb_regnum || regnum == -1)
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regcache_raw_supply (rc, gdbarch_tdep (current_gdbarch)->wb_regnum,
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(char *) ®s->windowbase);
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if (regnum == gdbarch_tdep (current_gdbarch)->ws_regnum || regnum == -1)
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regcache_raw_supply (rc, gdbarch_tdep (current_gdbarch)->ws_regnum,
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(char *) ®s->windowstart);
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if (regnum == gdbarch_tdep (current_gdbarch)->lbeg_regnum || regnum == -1)
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regcache_raw_supply (rc, gdbarch_tdep (current_gdbarch)->lbeg_regnum,
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(char *) ®s->lbeg);
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if (regnum == gdbarch_tdep (current_gdbarch)->lend_regnum || regnum == -1)
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regcache_raw_supply (rc, gdbarch_tdep (current_gdbarch)->lend_regnum,
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(char *) ®s->lend);
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if (regnum == gdbarch_tdep (current_gdbarch)->lcount_regnum || regnum == -1)
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regcache_raw_supply (rc, gdbarch_tdep (current_gdbarch)->lcount_regnum,
|
||||
(char *) ®s->lcount);
|
||||
if (regnum == gdbarch_tdep (current_gdbarch)->sar_regnum || regnum == -1)
|
||||
regcache_raw_supply (rc, gdbarch_tdep (current_gdbarch)->sar_regnum,
|
||||
(char *) ®s->sar);
|
||||
if (regnum == gdbarch_tdep (current_gdbarch)->exccause_regnum
|
||||
|| regnum == -1)
|
||||
regcache_raw_supply (rc, gdbarch_tdep (current_gdbarch)->exccause_regnum,
|
||||
(char *) ®s->exccause);
|
||||
if (regnum == gdbarch_tdep (current_gdbarch)->excvaddr_regnum || regnum == -1)
|
||||
regcache_raw_supply (rc, gdbarch_tdep (current_gdbarch)->excvaddr_regnum,
|
||||
(char *) ®s->excvaddr);
|
||||
if (regnum >=gdbarch_tdep (current_gdbarch)->ar_base
|
||||
&& regnum < gdbarch_tdep (current_gdbarch)->ar_base
|
||||
+ gdbarch_tdep (current_gdbarch)->num_aregs)
|
||||
regcache_raw_supply (rc, regnum,
|
||||
(char *) ®s->ar[regnum - gdbarch_tdep
|
||||
(current_gdbarch)->ar_base]);
|
||||
else if (regnum == -1)
|
||||
{
|
||||
for (i = 0; i < NUM_AREGS; ++i)
|
||||
regcache_raw_supply (rc, AR_BASE + i, (char *) ®s->ar[i]);
|
||||
for (i = 0; i < gdbarch_tdep (current_gdbarch)->num_aregs; ++i)
|
||||
regcache_raw_supply (rc, gdbarch_tdep (current_gdbarch)->ar_base + i,
|
||||
(char *) ®s->ar[i]);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -981,7 +1011,8 @@ xtensa_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
|
|||
DEBUGTRACE ("xtensa_unwind_dummy_id ()\n");
|
||||
|
||||
pc = frame_pc_unwind (next_frame);
|
||||
fp = frame_unwind_register_unsigned (next_frame, A1_REGNUM);
|
||||
fp = frame_unwind_register_unsigned
|
||||
(next_frame, gdbarch_tdep (current_gdbarch)->a0_base + 1);
|
||||
|
||||
/* Make dummy frame ID unique by adding a constant. */
|
||||
return frame_id_build (fp + SP_ALIGNMENT, pc);
|
||||
|
@ -1026,16 +1057,19 @@ xtensa_frame_cache (struct frame_info *next_frame, void **this_cache)
|
|||
if (windowed)
|
||||
{
|
||||
/* Get WINDOWBASE, WINDOWSTART, and PS registers. */
|
||||
wb = frame_unwind_register_unsigned (next_frame, WB_REGNUM);
|
||||
ws = frame_unwind_register_unsigned (next_frame, WS_REGNUM);
|
||||
wb = frame_unwind_register_unsigned
|
||||
(next_frame, gdbarch_tdep (current_gdbarch)->wb_regnum);
|
||||
ws = frame_unwind_register_unsigned
|
||||
(next_frame, gdbarch_tdep (current_gdbarch)->ws_regnum);
|
||||
ps = frame_unwind_register_unsigned (next_frame, ps_regnum);
|
||||
|
||||
op1 = read_memory_integer (pc, 1);
|
||||
if (XTENSA_IS_ENTRY (op1))
|
||||
{
|
||||
int callinc = CALLINC (ps);
|
||||
ra = frame_unwind_register_unsigned (next_frame,
|
||||
A0_REGNUM + callinc * 4);
|
||||
ra = frame_unwind_register_unsigned
|
||||
(next_frame,
|
||||
gdbarch_tdep (current_gdbarch)->a0_base + 0 + callinc * 4);
|
||||
|
||||
DEBUGINFO("[xtensa_frame_cache] 'entry' at 0x%08x\n (callinc = %d)",
|
||||
(int)pc, callinc);
|
||||
|
@ -1044,14 +1078,17 @@ xtensa_frame_cache (struct frame_info *next_frame, void **this_cache)
|
|||
cache->wd.callsize = 0;
|
||||
cache->wd.wb = wb;
|
||||
cache->wd.ws = ws;
|
||||
cache->prev_sp = frame_unwind_register_unsigned (next_frame,
|
||||
A1_REGNUM);
|
||||
cache->prev_sp = frame_unwind_register_unsigned
|
||||
(next_frame, gdbarch_tdep
|
||||
(current_gdbarch)->a0_base + 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
ra = frame_unwind_register_unsigned (next_frame, A0_REGNUM);
|
||||
ra = frame_unwind_register_unsigned
|
||||
(next_frame, gdbarch_tdep (current_gdbarch)->a0_base + 0);
|
||||
cache->wd.callsize = WINSIZE (ra);
|
||||
cache->wd.wb = (wb - cache->wd.callsize / 4) & (NUM_AREGS / 4 - 1);
|
||||
cache->wd.wb = (wb - cache->wd.callsize / 4)
|
||||
& (gdbarch_tdep (current_gdbarch)->num_aregs / 4 - 1);
|
||||
cache->wd.ws = ws & ~(1 << wb);
|
||||
}
|
||||
|
||||
|
@ -1065,7 +1102,8 @@ xtensa_frame_cache (struct frame_info *next_frame, void **this_cache)
|
|||
int i;
|
||||
|
||||
/* Set A0...A3. */
|
||||
sp = frame_unwind_register_unsigned (next_frame, A1_REGNUM) - 16;
|
||||
sp = frame_unwind_register_unsigned
|
||||
(next_frame, gdbarch_tdep (current_gdbarch)->a0_base + 1) - 16;
|
||||
|
||||
for (i = 0; i < 4; i++, sp += 4)
|
||||
{
|
||||
|
@ -1097,12 +1135,15 @@ xtensa_frame_cache (struct frame_info *next_frame, void **this_cache)
|
|||
cache->prev_sp =
|
||||
read_memory_integer (cache->wd.aregs[1],
|
||||
register_size (current_gdbarch,
|
||||
A1_REGNUM));
|
||||
gdbarch_tdep (current_gdbarch)->a0_base
|
||||
+ 1));
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Read caller's frame SP directly from the previous window. */
|
||||
int regnum = AREG_NUMBER (A1_REGNUM, cache->wd.wb);
|
||||
int regnum = AREG_NUMBER
|
||||
(gdbarch_tdep (current_gdbarch)->a0_base + 1,
|
||||
cache->wd.wb);
|
||||
|
||||
cache->prev_sp = xtensa_read_register (regnum);
|
||||
}
|
||||
|
@ -1113,7 +1154,8 @@ xtensa_frame_cache (struct frame_info *next_frame, void **this_cache)
|
|||
call0_frame_cache (next_frame, cache, pc);
|
||||
}
|
||||
|
||||
cache->base = frame_unwind_register_unsigned (next_frame,A1_REGNUM);
|
||||
cache->base = frame_unwind_register_unsigned
|
||||
(next_frame, gdbarch_tdep (current_gdbarch)->a0_base + 1);
|
||||
|
||||
return cache;
|
||||
}
|
||||
|
@ -1157,8 +1199,9 @@ call0_frame_get_reg_at_entry (struct frame_info *next_frame,
|
|||
{
|
||||
CORE_ADDR fp, spe;
|
||||
int stkofs;
|
||||
int reg = (regnum >= AR_BASE && regnum <= (AR_BASE + C0_NREGS))
|
||||
? regnum - AR_BASE : regnum;
|
||||
int reg = (regnum >= gdbarch_tdep (current_gdbarch)->ar_base
|
||||
&& regnum <= (gdbarch_tdep (current_gdbarch)->ar_base + C0_NREGS))
|
||||
? regnum - gdbarch_tdep (current_gdbarch)->ar_base : regnum;
|
||||
|
||||
/* Determine stack pointer on entry to this function, based on FP. */
|
||||
spe = cache->c0.c0_fp - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
|
||||
|
@ -1213,18 +1256,18 @@ xtensa_frame_prev_register (struct frame_info *next_frame,
|
|||
|
||||
if (regnum ==gdbarch_pc_regnum (current_gdbarch))
|
||||
saved_reg = cache->ra;
|
||||
else if (regnum == A1_REGNUM)
|
||||
else if (regnum == gdbarch_tdep (current_gdbarch)->a0_base + 1)
|
||||
saved_reg = cache->prev_sp;
|
||||
else if (!cache->call0)
|
||||
{
|
||||
if (regnum == WS_REGNUM)
|
||||
if (regnum == gdbarch_tdep (current_gdbarch)->ws_regnum)
|
||||
{
|
||||
if (cache->wd.ws != 0)
|
||||
saved_reg = cache->wd.ws;
|
||||
else
|
||||
saved_reg = 1 << cache->wd.wb;
|
||||
}
|
||||
else if (regnum == WB_REGNUM)
|
||||
else if (regnum == gdbarch_tdep (current_gdbarch)->wb_regnum)
|
||||
saved_reg = cache->wd.wb;
|
||||
else if (regnum == gdbarch_ps_regnum (current_gdbarch))
|
||||
saved_reg = cache->ps;
|
||||
|
@ -1249,13 +1292,17 @@ xtensa_frame_prev_register (struct frame_info *next_frame,
|
|||
if (!cache->call0) /* Windowed ABI. */
|
||||
{
|
||||
/* Convert A-register numbers to AR-register numbers. */
|
||||
if (regnum >= A0_REGNUM && regnum <= A15_REGNUM)
|
||||
if (regnum >= gdbarch_tdep (current_gdbarch)->a0_base + 0
|
||||
&& regnum <= gdbarch_tdep (current_gdbarch)->a0_base + 15)
|
||||
regnum = AREG_NUMBER (regnum, cache->wd.wb);
|
||||
|
||||
/* Check if AR-register has been saved to stack. */
|
||||
if (regnum >= AR_BASE && regnum <= (AR_BASE + NUM_AREGS))
|
||||
if (regnum >= gdbarch_tdep (current_gdbarch)->ar_base
|
||||
&& regnum <= (gdbarch_tdep (current_gdbarch)->ar_base
|
||||
+ gdbarch_tdep (current_gdbarch)->num_aregs))
|
||||
{
|
||||
int areg = regnum - AR_BASE - (cache->wd.wb * 4);
|
||||
int areg = regnum - gdbarch_tdep (current_gdbarch)->ar_base
|
||||
- (cache->wd.wb * 4);
|
||||
|
||||
if (areg >= 0
|
||||
&& areg < XTENSA_NUM_SAVED_AREGS
|
||||
|
@ -1277,8 +1324,10 @@ xtensa_frame_prev_register (struct frame_info *next_frame,
|
|||
}
|
||||
else /* Call0 ABI. */
|
||||
{
|
||||
int reg = (regnum >= AR_BASE && regnum <= (AR_BASE + C0_NREGS))
|
||||
? regnum - AR_BASE : regnum;
|
||||
int reg = (regnum >= gdbarch_tdep (current_gdbarch)->ar_base
|
||||
&& regnum <= (gdbarch_tdep (current_gdbarch)->ar_base
|
||||
+ C0_NREGS))
|
||||
? regnum - gdbarch_tdep (current_gdbarch)->ar_base : regnum;
|
||||
|
||||
if (reg < C0_NREGS)
|
||||
{
|
||||
|
@ -1367,7 +1416,7 @@ xtensa_extract_return_value (struct type *type,
|
|||
|
||||
gdb_assert(len > 0);
|
||||
|
||||
if (CALL_ABI != CallAbiCall0Only)
|
||||
if (gdbarch_tdep (current_gdbarch)->call_abi != CallAbiCall0Only)
|
||||
{
|
||||
/* First, we have to find the caller window in the register file. */
|
||||
regcache_raw_read_unsigned (regcache,
|
||||
|
@ -1381,13 +1430,15 @@ xtensa_extract_return_value (struct type *type,
|
|||
|
||||
/* Get the register offset of the return
|
||||
register (A2) in the caller window. */
|
||||
regcache_raw_read_unsigned (regcache, WB_REGNUM, &wb);
|
||||
areg = AREG_NUMBER(A2_REGNUM + callsize, wb);
|
||||
regcache_raw_read_unsigned
|
||||
(regcache, gdbarch_tdep (current_gdbarch)->wb_regnum, &wb);
|
||||
areg = AREG_NUMBER(gdbarch_tdep (current_gdbarch)->a0_base + 2 + callsize,
|
||||
wb);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* No windowing hardware - Call0 ABI. */
|
||||
areg = A0_REGNUM + C0_ARGS;
|
||||
areg = gdbarch_tdep (current_gdbarch)->a0_base + 0 + C0_ARGS;
|
||||
}
|
||||
|
||||
DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len);
|
||||
|
@ -1419,9 +1470,10 @@ xtensa_store_return_value (struct type *type,
|
|||
|
||||
DEBUGTRACE ("xtensa_store_return_value (...)\n");
|
||||
|
||||
if (CALL_ABI != CallAbiCall0Only)
|
||||
if (gdbarch_tdep (current_gdbarch)->call_abi != CallAbiCall0Only)
|
||||
{
|
||||
regcache_raw_read_unsigned (regcache, WB_REGNUM, &wb);
|
||||
regcache_raw_read_unsigned
|
||||
(regcache, gdbarch_tdep (current_gdbarch)->wb_regnum, &wb);
|
||||
regcache_raw_read_unsigned (regcache,
|
||||
gdbarch_pc_regnum (current_gdbarch), &pc);
|
||||
callsize = extract_call_winsize (pc);
|
||||
|
@ -1430,14 +1482,15 @@ xtensa_store_return_value (struct type *type,
|
|||
internal_error (__FILE__, __LINE__,
|
||||
_("unimplemented for this length: %d"),
|
||||
TYPE_LENGTH (type));
|
||||
areg = AREG_NUMBER (A2_REGNUM + callsize, wb);
|
||||
areg = AREG_NUMBER
|
||||
(gdbarch_tdep (current_gdbarch)->a0_base + 2 + callsize, wb);
|
||||
|
||||
DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
|
||||
callsize, (int) wb);
|
||||
}
|
||||
else
|
||||
{
|
||||
areg = A0_REGNUM + C0_ARGS;
|
||||
areg = gdbarch_tdep (current_gdbarch)->a0_base + 0 + C0_ARGS;
|
||||
}
|
||||
|
||||
if (len < 4 && gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
|
||||
|
@ -1629,7 +1682,8 @@ xtensa_push_dummy_call (struct gdbarch *gdbarch,
|
|||
sp = align_down (sp - onstack_size, SP_ALIGNMENT);
|
||||
|
||||
/* Simulate MOVSP, if Windowed ABI. */
|
||||
if ((CALL_ABI != CallAbiCall0Only) && (sp != osp))
|
||||
if ((gdbarch_tdep (current_gdbarch)->call_abi != CallAbiCall0Only)
|
||||
&& (sp != osp))
|
||||
{
|
||||
read_memory (osp - 16, buf, 16);
|
||||
write_memory (sp - 16, buf, 16);
|
||||
|
@ -1704,12 +1758,13 @@ xtensa_push_dummy_call (struct gdbarch *gdbarch,
|
|||
The return address for the current function (in A0) is
|
||||
saved in the dummy frame, so we can savely overwrite A0 here. */
|
||||
|
||||
if (CALL_ABI != CallAbiCall0Only)
|
||||
if (gdbarch_tdep (current_gdbarch)->call_abi != CallAbiCall0Only)
|
||||
{
|
||||
ra = (bp_addr & 0x3fffffff) | 0x40000000;
|
||||
regcache_raw_read (regcache, gdbarch_ps_regnum (current_gdbarch), buf);
|
||||
ps = extract_unsigned_integer (buf, 4) & ~0x00030000;
|
||||
regcache_cooked_write_unsigned (regcache, A4_REGNUM, ra);
|
||||
regcache_cooked_write_unsigned
|
||||
(regcache, gdbarch_tdep (current_gdbarch)->a0_base + 4, ra);
|
||||
regcache_cooked_write_unsigned (regcache,
|
||||
gdbarch_ps_regnum (current_gdbarch),
|
||||
ps | 0x00010000);
|
||||
|
@ -1717,11 +1772,14 @@ xtensa_push_dummy_call (struct gdbarch *gdbarch,
|
|||
else
|
||||
{
|
||||
/* Simulate CALL0: write RA into A0 register. */
|
||||
regcache_cooked_write_unsigned (regcache, A0_REGNUM, bp_addr);
|
||||
regcache_cooked_write_unsigned
|
||||
(regcache, gdbarch_tdep (current_gdbarch)->a0_base + 0, bp_addr);
|
||||
}
|
||||
|
||||
/* Set new stack pointer and return it. */
|
||||
regcache_cooked_write_unsigned (regcache, A1_REGNUM, sp);
|
||||
regcache_cooked_write_unsigned (regcache,
|
||||
gdbarch_tdep (current_gdbarch)->a0_base + 1,
|
||||
sp);
|
||||
/* Make dummy frame ID unique by adding a constant. */
|
||||
return sp + SP_ALIGNMENT;
|
||||
}
|
||||
|
@ -1746,7 +1804,7 @@ xtensa_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
|
|||
|
||||
DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr);
|
||||
|
||||
if (ISA_USE_DENSITY_INSTRUCTIONS)
|
||||
if (gdbarch_tdep (current_gdbarch)->isa_use_density_instructions)
|
||||
{
|
||||
if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
|
||||
{
|
||||
|
@ -1916,8 +1974,9 @@ call0_track_op (xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
|
|||
/* 2 operands: dst, literal offset. */
|
||||
gdb_assert (nods == 2);
|
||||
/* litbase = xtensa_get_litbase (pc); can be also used. */
|
||||
litbase = (LITBASE_REGNUM == -1)
|
||||
? 0 : xtensa_read_register (LITBASE_REGNUM);
|
||||
litbase = (gdbarch_tdep (current_gdbarch)->litbase_regnum == -1)
|
||||
? 0 : xtensa_read_register
|
||||
(gdbarch_tdep (current_gdbarch)->litbase_regnum);
|
||||
litaddr = litbase & 1
|
||||
? (litbase & ~1) + (signed)odv[1]
|
||||
: (pc + 3 + (signed)odv[1]) & ~3;
|
||||
|
@ -2198,7 +2257,8 @@ call0_frame_cache (struct frame_info *next_frame,
|
|||
&cache->call0);
|
||||
}
|
||||
|
||||
sp = frame_unwind_register_unsigned (next_frame, A1_REGNUM);
|
||||
sp = frame_unwind_register_unsigned
|
||||
(next_frame, gdbarch_tdep (current_gdbarch)->a0_base + 1);
|
||||
fp = sp; /* Assume FP == SP until proven otherwise. */
|
||||
|
||||
/* Get the frame information and FP (if used) at the current PC.
|
||||
|
@ -2217,12 +2277,12 @@ call0_frame_cache (struct frame_info *next_frame,
|
|||
was derived from SP. Otherwise, it would be C0_FP. */
|
||||
fp_regnum = c0_hasfp ? C0_FP : C0_SP;
|
||||
c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs;
|
||||
fp_regnum += A0_BASE;
|
||||
fp_regnum += gdbarch_tdep (current_gdbarch)->a0_base;
|
||||
}
|
||||
else /* No data from the prologue analysis. */
|
||||
{
|
||||
c0_hasfp = 0;
|
||||
fp_regnum = A0_BASE + C0_SP;
|
||||
fp_regnum = gdbarch_tdep (current_gdbarch)->a0_base + C0_SP;
|
||||
c0_frmsz = 0;
|
||||
start_pc = pc;
|
||||
}
|
||||
|
@ -2277,8 +2337,10 @@ call0_frame_cache (struct frame_info *next_frame,
|
|||
i = C0_RA;
|
||||
if (i < C0_NREGS) /* Read from the next_frame. */
|
||||
{
|
||||
ra = frame_unwind_register_unsigned (next_frame,
|
||||
A0_REGNUM + cache->c0.c0_rt[i].fr_reg);
|
||||
ra = frame_unwind_register_unsigned
|
||||
(next_frame,
|
||||
gdbarch_tdep (current_gdbarch)->a0_base + 0
|
||||
+ cache->c0.c0_rt[i].fr_reg);
|
||||
}
|
||||
else ra = 0;
|
||||
}
|
||||
|
|
|
@ -105,7 +105,7 @@ typedef struct
|
|||
xtensa_elf_greg_t ar[0]; /* variable size (per config). */
|
||||
} xtensa_elf_gregset_t;
|
||||
|
||||
#define SIZEOF_GREGSET (sizeof (xtensa_elf_gregset_t) + NUM_AREGS * 4)
|
||||
#define SIZEOF_GREGSET (sizeof (xtensa_elf_gregset_t) + gdbarch_tdep (current_gdbarch)->num_aregs * 4)
|
||||
#define XTENSA_ELF_NGREG (SIZEOF_GREGSET / sizeof(xtensa_elf_greg_t))
|
||||
|
||||
|
||||
|
@ -229,63 +229,6 @@ struct gdbarch_tdep
|
|||
};
|
||||
|
||||
|
||||
/* Define macros to access some of the gdbarch entries. */
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||||
#define XTENSA_TARGET_FLAGS \
|
||||
(gdbarch_tdep (current_gdbarch)->target_flags)
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||||
#define SPILL_LOCATION \
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(gdbarch_tdep (current_gdbarch)->spill_location)
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#define SPILL_SIZE \
|
||||
(gdbarch_tdep (current_gdbarch)->spill_size)
|
||||
#define CALL_ABI \
|
||||
(gdbarch_tdep (current_gdbarch)->call_abi)
|
||||
#define ISA_USE_WINDOWED_REGISTERS \
|
||||
(gdbarch_tdep (current_gdbarch)->isa_use_windowed_registers)
|
||||
#define ISA_USE_DENSITY_INSTRUCTIONS \
|
||||
(gdbarch_tdep (current_gdbarch)->isa_use_density_instructions)
|
||||
#define ISA_USE_EXCEPTIONS \
|
||||
(gdbarch_tdep (current_gdbarch)->isa_use_exceptions)
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||||
#define ISA_USE_EXT_L32R \
|
||||
(gdbarch_tdep (current_gdbarch)->isa_use_ext_l32r)
|
||||
#define DEBUG_DATA_VADDR_TRAP_COUNT \
|
||||
(gdbarch_tdep (current_gdbarch)->debug_data_vaddr_trap_count)
|
||||
#define DEBUG_INST_VADDR_TRAP_COUNT \
|
||||
(gdbarch_tdep (current_gdbarch)->debug_inst_vaddr_trap_count)
|
||||
#define ISA_MAX_INSN_SIZE \
|
||||
(gdbarch_tdep (current_gdbarch)->isa_max_insn_size)
|
||||
#define DEBUG_NUM_IBREAKS \
|
||||
(gdbarch_tdep (current_gdbarch)->debug_num_ibreaks)
|
||||
#define DEBUG_NUM_DBREAKS \
|
||||
(gdbarch_tdep (current_gdbarch)->debug_num_dbreaks)
|
||||
|
||||
#define NUM_AREGS (gdbarch_tdep (current_gdbarch)->num_aregs)
|
||||
#define WB_REGNUM (gdbarch_tdep (current_gdbarch)->wb_regnum)
|
||||
#define WS_REGNUM (gdbarch_tdep (current_gdbarch)->ws_regnum)
|
||||
#define LBEG_REGNUM (gdbarch_tdep (current_gdbarch)->lbeg_regnum)
|
||||
#define LEND_REGNUM (gdbarch_tdep (current_gdbarch)->lend_regnum)
|
||||
#define LCOUNT_REGNUM (gdbarch_tdep (current_gdbarch)->lcount_regnum)
|
||||
#define SAR_REGNUM (gdbarch_tdep (current_gdbarch)->sar_regnum)
|
||||
#define REGMAP (gdbarch_tdep (current_gdbarch)->regmap)
|
||||
|
||||
#define LITBASE_REGNUM (gdbarch_tdep (current_gdbarch)->litbase_regnum)
|
||||
#define DEBUGCAUSE_REGNUM (gdbarch_tdep (current_gdbarch)->debugcause_regnum)
|
||||
#define EXCCAUSE_REGNUM (gdbarch_tdep (current_gdbarch)->exccause_regnum)
|
||||
#define EXCVADDR_REGNUM (gdbarch_tdep (current_gdbarch)->excvaddr_regnum)
|
||||
#define NUM_IBREAKS (gdbarch_tdep (current_gdbarch)->num_ibreaks)
|
||||
#define REGMAP_BYTES (gdbarch_tdep (current_gdbarch)->regmap_bytes)
|
||||
#define A0_BASE (gdbarch_tdep (current_gdbarch)->a0_base)
|
||||
#define AR_BASE (gdbarch_tdep (current_gdbarch)->ar_base)
|
||||
#define FP_ALIAS \
|
||||
(gdbarch_num_regs (current_gdbarch) \
|
||||
+ gdbarch_num_pseudo_regs (current_gdbarch))
|
||||
#define CALL_ABI (gdbarch_tdep (current_gdbarch)->call_abi)
|
||||
#define NUM_CONTEXTS (gdbarch_tdep (current_gdbarch)->num_contexts)
|
||||
|
||||
#define FP_LAYOUT (gdbarch_tdep (current_gdbarch)->fp_layout)
|
||||
#define FP_LAYOUT_BYTES (gdbarch_tdep (current_gdbarch)->fp_layout_bytes)
|
||||
#define GREGMAP (gdbarch_tdep (current_gdbarch)->gregmap)
|
||||
|
||||
#define AREGS_MASK (NUM_AREGS - 1)
|
||||
#define WB_MASK (AREGS_MASK >> 2)
|
||||
#define WB_SHIFT 2
|
||||
|
||||
/* We assign fixed numbers to the registers of the "current" window
|
||||
|
@ -293,20 +236,3 @@ struct gdbarch_tdep
|
|||
data structure to their corresponding register in the AR register
|
||||
file (see xtensa-tdep.c). */
|
||||
|
||||
#define A0_REGNUM (A0_BASE + 0)
|
||||
#define A1_REGNUM (A0_BASE + 1)
|
||||
#define A2_REGNUM (A0_BASE + 2)
|
||||
#define A3_REGNUM (A0_BASE + 3)
|
||||
#define A4_REGNUM (A0_BASE + 4)
|
||||
#define A5_REGNUM (A0_BASE + 5)
|
||||
#define A6_REGNUM (A0_BASE + 6)
|
||||
#define A7_REGNUM (A0_BASE + 7)
|
||||
#define A8_REGNUM (A0_BASE + 8)
|
||||
#define A9_REGNUM (A0_BASE + 9)
|
||||
#define A10_REGNUM (A0_BASE + 10)
|
||||
#define A11_REGNUM (A0_BASE + 11)
|
||||
#define A12_REGNUM (A0_BASE + 12)
|
||||
#define A13_REGNUM (A0_BASE + 13)
|
||||
#define A14_REGNUM (A0_BASE + 14)
|
||||
#define A15_REGNUM (A0_BASE + 15)
|
||||
|
||||
|
|
Loading…
Reference in New Issue