gas/
2008-01-15 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (md_assemble): Also zap movzx and movsx suffix for AT&T syntax. gas/testsuite/ 2008-01-15 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.s: Add more tests for movsx and movzx. * gas/i386/x86_64.s: Likewise. * gas/i386/inval.s: Remove tests for movsxw and movzxw. * gas/i386/x86-64-inval.s: Remove tests for movsxb, movsxw, movsxl, movzxb and movzxw. * gas/i386/i386.d: Updated. * gas/i386/inval.l: Likewise. * gas/i386/x86_64.d: Likewise. * gas/i386/x86-64-inval.l: Likewise. opcodes/ 2008-01-15 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax. * i386-tbl.h: Regenerated.
This commit is contained in:
H.J. Lu
parent
4ee521786f
commit
321fd21e2f
@ -1,3 +1,8 @@
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2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (md_assemble): Also zap movzx and movsx
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suffix for AT&T syntax.
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2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (match_reg_size): New.
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@ -2277,25 +2277,20 @@ md_assemble (line)
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if (!match_template ())
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return;
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if (intel_syntax)
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/* Zap movzx and movsx suffix. The suffix has been set from
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"word ptr" or "byte ptr" on the source operand in Intel syntax
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or extracted from mnemonic in AT&T syntax. But we'll use
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the destination register to choose the suffix for encoding. */
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if ((i.tm.base_opcode & ~9) == 0x0fb6)
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{
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/* Zap movzx and movsx suffix. The suffix may have been set from
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"word ptr" or "byte ptr" on the source operand, but we'll use
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the suffix later to choose the destination register. */
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if ((i.tm.base_opcode & ~9) == 0x0fb6)
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{
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if (i.reg_operands < 2
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&& !i.suffix
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&& (!i.tm.opcode_modifier.no_bsuf
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|| !i.tm.opcode_modifier.no_wsuf
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|| !i.tm.opcode_modifier.no_lsuf
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|| !i.tm.opcode_modifier.no_ssuf
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|| !i.tm.opcode_modifier.no_ldsuf
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|| !i.tm.opcode_modifier.no_qsuf))
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as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
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/* In Intel syntax, there must be a suffix. In AT&T syntax, if
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there is no suffix, the default will be byte extension. */
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if (i.reg_operands != 2
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&& !i.suffix
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&& intel_syntax)
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as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
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i.suffix = 0;
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}
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i.suffix = 0;
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}
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if (i.tm.opcode_modifier.fwait)
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@ -1,3 +1,18 @@
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2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/i386.s: Add more tests for movsx and movzx.
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* gas/i386/x86_64.s: Likewise.
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* gas/i386/inval.s: Remove tests for movsxw and movzxw.
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* gas/i386/x86-64-inval.s: Remove tests for movsxb, movsxw,
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movsxl, movzxb and movzxw.
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* gas/i386/i386.d: Updated.
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* gas/i386/inval.l: Likewise.
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* gas/i386/x86_64.d: Likewise.
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* gas/i386/x86-64-inval.l: Likewise.
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2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/i386.s: Add tests for movsx, movzx and movnti.
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@ -10,14 +10,25 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: df e0 fnstsw %ax
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[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
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[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
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[ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si
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[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
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[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi
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[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
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[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
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[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
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[ ]*[a-f0-9]+: 0f bf 10 movswl \(%eax\),%edx
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[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
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[ ]*[a-f0-9]+: 0f bf 10 movswl \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si
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[ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi
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[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi
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[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx
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[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx
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[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx
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[ ]*[a-f0-9]+: 0f b7 10 movzwl \(%eax\),%edx
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[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx
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[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx
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@ -29,9 +40,15 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: df e0 fnstsw %ax
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[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
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[ ]*[a-f0-9]+: 9b df e0 fstsw %ax
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[ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si
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[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
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[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi
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[ ]*[a-f0-9]+: 0f be 10 movsbl \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%eax\),%dx
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[ ]*[a-f0-9]+: 0f bf 10 movswl \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si
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[ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi
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[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi
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[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%eax\),%edx
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[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%eax\),%dx
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[ ]*[a-f0-9]+: 0f b7 10 movzwl \(%eax\),%edx
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@ -6,15 +6,26 @@
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fstsw
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fstsw %ax
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movsx %al, %si
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movsx %al, %esi
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movsx %ax, %esi
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movsx (%eax), %edx
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movsx (%eax), %dx
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movsxb (%eax), %dx
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movsxb (%eax), %edx
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movsxw (%eax), %edx
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movsbl (%eax), %edx
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movsbw (%eax), %dx
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movsbl (%eax), %edx
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movswl (%eax), %edx
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movzx %al, %si
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movzx %al, %esi
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movzx %ax, %esi
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movzx (%eax), %edx
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movzx (%eax), %dx
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movzxb (%eax), %dx
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movzxb (%eax), %edx
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movzxw (%eax), %edx
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movzb (%eax), %edx
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movzb (%eax), %dx
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movzbl (%eax), %edx
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@ -30,10 +41,16 @@
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fstsw
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fstsw ax
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movsx si,al
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movsx esi,al
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movsx esi,ax
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movsx edx,BYTE PTR [eax]
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movsx dx,BYTE PTR [eax]
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movsx edx,WORD PTR [eax]
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movzx si,al
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movzx esi,al
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movzx esi,ax
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movzx edx,BYTE PTR [eax]
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movzx dx,BYTE PTR [eax]
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movzx edx,WORD PTR [eax]
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@ -55,8 +55,9 @@
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.*:56: Error: .*
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.*:58: Error: .*
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.*:59: Error: .*
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.*:61: Error: .*
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.*:62: Error: .*
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.*:63: Error: .*
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.*:64: Error: .*
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.*:65: Error: .*
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.*:66: Error: .*
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.*:67: Error: .*
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@ -70,14 +71,11 @@
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.*:75: Error: .*
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.*:76: Error: .*
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.*:77: Error: .*
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.*:78: Error: .*
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.*:79: Error: .*
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.*:80: Error: .*
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.*:81: Error: .*
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.*:82: Error: .*
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.*:83: Error: .*
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.*:84: Error: .*
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.*:85: Error: .*
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.*:87: Error: .*
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GAS LISTING .*
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@ -141,33 +139,30 @@ GAS LISTING .*
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GAS LISTING .*
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[ ]*58[ ]+movsxw \(%eax\),%eax
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[ ]*59[ ]+movzxw \(%eax\),%eax
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[ ]*58[ ]+movnti %ax, \(%eax\)
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[ ]*59[ ]+movntiw %ax, \(%eax\)
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[ ]*60[ ]+
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[ ]*61[ ]+movnti %ax, \(%eax\)
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[ ]*62[ ]+movntiw %ax, \(%eax\)
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[ ]*63[ ]+
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[ ]*64[ ]+\.intel_syntax noprefix
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[ ]*65[ ]+cvtsi2ss xmm1,QWORD PTR \[eax\]
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[ ]*66[ ]+cvtsi2sd xmm1,QWORD PTR \[eax\]
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[ ]*67[ ]+cvtsi2ssq xmm1,QWORD PTR \[eax\]
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[ ]*68[ ]+cvtsi2sdq xmm1,QWORD PTR \[eax\]
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[ ]*69[ ]+movq xmm1, XMMWORD PTR \[esp\]
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[ ]*70[ ]+movq xmm1, DWORD PTR \[esp\]
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[ ]*71[ ]+movq xmm1, WORD PTR \[esp\]
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[ ]*72[ ]+movq xmm1, BYTE PTR \[esp\]
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[ ]*73[ ]+movq XMMWORD PTR \[esp\],xmm1
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[ ]*74[ ]+movq DWORD PTR \[esp\],xmm1
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[ ]*75[ ]+movq WORD PTR \[esp\],xmm1
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[ ]*76[ ]+movq BYTE PTR \[esp\],xmm1
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[ ]*77[ ]+fnstsw eax
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[ ]*78[ ]+fnstsw al
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[ ]*79[ ]+fstsw eax
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[ ]*80[ ]+fstsw al
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[ ]*81[ ]+
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[ ]*82[ ]+movsx ax, \[eax\]
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[ ]*83[ ]+movsx eax, \[eax\]
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[ ]*84[ ]+movzx ax, \[eax\]
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[ ]*85[ ]+movzx eax, \[eax\]
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[ ]*86[ ]+
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[ ]*87[ ]+movnti word ptr \[eax\], ax
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[ ]*61[ ]+\.intel_syntax noprefix
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[ ]*62[ ]+cvtsi2ss xmm1,QWORD PTR \[eax\]
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[ ]*63[ ]+cvtsi2sd xmm1,QWORD PTR \[eax\]
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[ ]*64[ ]+cvtsi2ssq xmm1,QWORD PTR \[eax\]
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[ ]*65[ ]+cvtsi2sdq xmm1,QWORD PTR \[eax\]
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[ ]*66[ ]+movq xmm1, XMMWORD PTR \[esp\]
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[ ]*67[ ]+movq xmm1, DWORD PTR \[esp\]
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[ ]*68[ ]+movq xmm1, WORD PTR \[esp\]
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[ ]*69[ ]+movq xmm1, BYTE PTR \[esp\]
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[ ]*70[ ]+movq XMMWORD PTR \[esp\],xmm1
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[ ]*71[ ]+movq DWORD PTR \[esp\],xmm1
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[ ]*72[ ]+movq WORD PTR \[esp\],xmm1
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[ ]*73[ ]+movq BYTE PTR \[esp\],xmm1
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[ ]*74[ ]+fnstsw eax
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[ ]*75[ ]+fnstsw al
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[ ]*76[ ]+fstsw eax
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[ ]*77[ ]+fstsw al
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[ ]*78[ ]+
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[ ]*79[ ]+movsx ax, \[eax\]
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[ ]*80[ ]+movsx eax, \[eax\]
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[ ]*81[ ]+movzx ax, \[eax\]
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[ ]*82[ ]+movzx eax, \[eax\]
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[ ]*83[ ]+
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[ ]*84[ ]+movnti word ptr \[eax\], ax
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@ -55,9 +55,6 @@ foo: jaw foo
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fstsw %eax
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fstsw %al
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movsxw (%eax),%eax
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movzxw (%eax),%eax
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movnti %ax, (%eax)
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movntiw %ax, (%eax)
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@ -58,8 +58,6 @@
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.*:59: Error: .*
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.*:60: Error: .*
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.*:61: Error: .*
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.*:62: Error: .*
|
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.*:63: Error: .*
|
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.*:64: Error: .*
|
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.*:65: Error: .*
|
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.*:66: Error: .*
|
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@ -67,6 +65,8 @@
|
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.*:68: Error: .*
|
||||
.*:69: Error: .*
|
||||
.*:70: Error: .*
|
||||
.*:71: Error: .*
|
||||
.*:72: Error: .*
|
||||
.*:73: Error: .*
|
||||
.*:74: Error: .*
|
||||
.*:75: Error: .*
|
||||
@ -80,15 +80,6 @@
|
||||
.*:83: Error: .*
|
||||
.*:84: Error: .*
|
||||
.*:85: Error: .*
|
||||
.*:86: Error: .*
|
||||
.*:87: Error: .*
|
||||
.*:88: Error: .*
|
||||
.*:89: Error: .*
|
||||
.*:90: Error: .*
|
||||
.*:91: Error: .*
|
||||
.*:92: Error: .*
|
||||
.*:93: Error: .*
|
||||
.*:94: Error: .*
|
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GAS LISTING .*
|
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|
||||
|
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@ -153,39 +144,30 @@ GAS LISTING .*
|
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|
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|
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[ ]*58[ ]+out %rax,\$8
|
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[ ]*59[ ]+movsxb \(%rax\),%eax
|
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[ ]*60[ ]+movsxb \(%rax\),%rax
|
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[ ]*61[ ]+movsxw \(%rax\),%eax
|
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[ ]*62[ ]+movsxw \(%rax\),%rax
|
||||
[ ]*63[ ]+movsxl \(%rax\),%rax
|
||||
[ ]*64[ ]+movzxb \(%rax\),%eax
|
||||
[ ]*65[ ]+movzxb \(%rax\),%rax
|
||||
[ ]*66[ ]+movzxw \(%rax\),%eax
|
||||
[ ]*67[ ]+movzxw \(%rax\),%rax
|
||||
[ ]*68[ ]+movzxl \(%rax\),%rax
|
||||
[ ]*69[ ]+movnti %ax, \(%rax\)
|
||||
[ ]*70[ ]+movntiw %ax, \(%rax\)
|
||||
[ ]*71[ ]+
|
||||
[ ]*72[ ]+\.intel_syntax noprefix
|
||||
[ ]*73[ ]+cmpxchg16b dword ptr \[rax\] \# Must be oword
|
||||
[ ]*74[ ]+movq xmm1, XMMWORD PTR \[rsp\]
|
||||
[ ]*75[ ]+movq xmm1, DWORD PTR \[rsp\]
|
||||
[ ]*76[ ]+movq xmm1, WORD PTR \[rsp\]
|
||||
[ ]*77[ ]+movq xmm1, BYTE PTR \[rsp\]
|
||||
[ ]*78[ ]+movq XMMWORD PTR \[rsp\],xmm1
|
||||
[ ]*79[ ]+movq DWORD PTR \[rsp\],xmm1
|
||||
[ ]*80[ ]+movq WORD PTR \[rsp\],xmm1
|
||||
[ ]*81[ ]+movq BYTE PTR \[rsp\],xmm1
|
||||
[ ]*82[ ]+fnstsw eax
|
||||
[ ]*83[ ]+fnstsw al
|
||||
[ ]*84[ ]+fstsw eax
|
||||
[ ]*85[ ]+fstsw al
|
||||
[ ]*86[ ]+in rax,8
|
||||
[ ]*87[ ]+out 8,rax
|
||||
[ ]*88[ ]+movsx ax, \[rax\]
|
||||
[ ]*89[ ]+movsx eax, \[rax\]
|
||||
[ ]*90[ ]+movsx rax, \[rax\]
|
||||
[ ]*91[ ]+movzx ax, \[rax\]
|
||||
[ ]*92[ ]+movzx eax, \[rax\]
|
||||
[ ]*93[ ]+movzx rax, \[rax\]
|
||||
[ ]*94[ ]+movnti word ptr \[rax\], ax
|
||||
[ ]*59[ ]+movzxl \(%rax\),%rax
|
||||
[ ]*60[ ]+movnti %ax, \(%rax\)
|
||||
[ ]*61[ ]+movntiw %ax, \(%rax\)
|
||||
[ ]*62[ ]+
|
||||
[ ]*63[ ]+\.intel_syntax noprefix
|
||||
[ ]*64[ ]+cmpxchg16b dword ptr \[rax\] \# Must be oword
|
||||
[ ]*65[ ]+movq xmm1, XMMWORD PTR \[rsp\]
|
||||
[ ]*66[ ]+movq xmm1, DWORD PTR \[rsp\]
|
||||
[ ]*67[ ]+movq xmm1, WORD PTR \[rsp\]
|
||||
[ ]*68[ ]+movq xmm1, BYTE PTR \[rsp\]
|
||||
[ ]*69[ ]+movq XMMWORD PTR \[rsp\],xmm1
|
||||
[ ]*70[ ]+movq DWORD PTR \[rsp\],xmm1
|
||||
[ ]*71[ ]+movq WORD PTR \[rsp\],xmm1
|
||||
[ ]*72[ ]+movq BYTE PTR \[rsp\],xmm1
|
||||
[ ]*73[ ]+fnstsw eax
|
||||
[ ]*74[ ]+fnstsw al
|
||||
[ ]*75[ ]+fstsw eax
|
||||
[ ]*76[ ]+fstsw al
|
||||
[ ]*77[ ]+in rax,8
|
||||
[ ]*78[ ]+out 8,rax
|
||||
[ ]*79[ ]+movsx ax, \[rax\]
|
||||
[ ]*80[ ]+movsx eax, \[rax\]
|
||||
[ ]*81[ ]+movsx rax, \[rax\]
|
||||
[ ]*82[ ]+movzx ax, \[rax\]
|
||||
[ ]*83[ ]+movzx eax, \[rax\]
|
||||
[ ]*84[ ]+movzx rax, \[rax\]
|
||||
[ ]*85[ ]+movnti word ptr \[rax\], ax
|
||||
|
||||
@ -56,15 +56,6 @@ foo: jcxz foo # No prefix exists to select CX as a counter
|
||||
fstsw %al
|
||||
in $8,%rax
|
||||
out %rax,$8
|
||||
movsxb (%rax),%eax
|
||||
movsxb (%rax),%rax
|
||||
movsxw (%rax),%eax
|
||||
movsxw (%rax),%rax
|
||||
movsxl (%rax),%rax
|
||||
movzxb (%rax),%eax
|
||||
movzxb (%rax),%rax
|
||||
movzxw (%rax),%eax
|
||||
movzxw (%rax),%rax
|
||||
movzxl (%rax),%rax
|
||||
movnti %ax, (%rax)
|
||||
movntiw %ax, (%rax)
|
||||
|
||||
@ -158,6 +158,12 @@ Disassembly of section .text:
|
||||
[ ]*[a-f0-9]+: 48 89 04 25 11 22 33 ff mov %rax,0xffffffffff332211
|
||||
[ ]*[a-f0-9]+: 48 0f c7 08 cmpxchg16b \(%rax\)
|
||||
[ ]*[a-f0-9]+: 48 0f c7 08 cmpxchg16b \(%rax\)
|
||||
[ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si
|
||||
[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
|
||||
[ ]*[a-f0-9]+: 48 0f be f0 movsbq %al,%rsi
|
||||
[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi
|
||||
[ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi
|
||||
[ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi
|
||||
[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx
|
||||
@ -166,6 +172,11 @@ Disassembly of section .text:
|
||||
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx
|
||||
[ ]*[a-f0-9]+: 0f bf 10 movswl \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 48 0f bf 10 movswq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si
|
||||
[ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi
|
||||
[ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi
|
||||
[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi
|
||||
[ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi
|
||||
[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx
|
||||
@ -177,11 +188,22 @@ Disassembly of section .text:
|
||||
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx
|
||||
[ ]*[a-f0-9]+: 0f b7 10 movzwl \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 48 0f b7 10 movzwq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 66 0f be f0 movsbw %al,%si
|
||||
[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi
|
||||
[ ]*[a-f0-9]+: 48 0f be f0 movsbq %al,%rsi
|
||||
[ ]*[a-f0-9]+: 0f bf f0 movswl %ax,%esi
|
||||
[ ]*[a-f0-9]+: 48 0f bf f0 movswq %ax,%rsi
|
||||
[ ]*[a-f0-9]+: 48 63 f0 movslq %eax,%rsi
|
||||
[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx
|
||||
[ ]*[a-f0-9]+: 0f bf 10 movswl \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 48 0f bf 10 movswq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 66 0f b6 f0 movzbw %al,%si
|
||||
[ ]*[a-f0-9]+: 0f b6 f0 movzbl %al,%esi
|
||||
[ ]*[a-f0-9]+: 48 0f b6 f0 movzbq %al,%rsi
|
||||
[ ]*[a-f0-9]+: 0f b7 f0 movzwl %ax,%esi
|
||||
[ ]*[a-f0-9]+: 48 0f b7 f0 movzwq %ax,%rsi
|
||||
[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx
|
||||
@ -202,10 +224,21 @@ Disassembly of section .text:
|
||||
[ ]*[a-f0-9]+: 66 0f be 00 movsbw \(%rax\),%ax
|
||||
[ ]*[a-f0-9]+: 0f be 00 movsbl \(%rax\),%eax
|
||||
[ ]*[a-f0-9]+: 48 0f be 00 movsbq \(%rax\),%rax
|
||||
[ ]*[a-f0-9]+: 66 0f be 10 movsbw \(%rax\),%dx
|
||||
[ ]*[a-f0-9]+: 0f be 10 movsbl \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 48 0f be 10 movsbq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 0f bf 10 movswl \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 48 0f bf 10 movswq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 48 63 10 movslq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 48 63 00 movslq \(%rax\),%rax
|
||||
[ ]*[a-f0-9]+: 66 0f b6 00 movzbw \(%rax\),%ax
|
||||
[ ]*[a-f0-9]+: 0f b6 00 movzbl \(%rax\),%eax
|
||||
[ ]*[a-f0-9]+: 48 0f b6 00 movzbq \(%rax\),%rax
|
||||
[ ]*[a-f0-9]+: 66 0f b6 10 movzbw \(%rax\),%dx
|
||||
[ ]*[a-f0-9]+: 0f b6 10 movzbl \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 48 0f b6 10 movzbq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 0f b7 10 movzwl \(%rax\),%edx
|
||||
[ ]*[a-f0-9]+: 48 0f b7 10 movzwq \(%rax\),%rdx
|
||||
[ ]*[a-f0-9]+: 0f c3 00 movnti %eax,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 0f c3 00 movnti %eax,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 48 0f c3 00 movnti %rax,\(%rax\)
|
||||
|
||||
@ -194,6 +194,12 @@ cmpxchg16b (%rax)
|
||||
cmpxchg16b oword ptr [rax]
|
||||
|
||||
.att_syntax
|
||||
movsx %al, %si
|
||||
movsx %al, %esi
|
||||
movsx %al, %rsi
|
||||
movsx %ax, %esi
|
||||
movsx %ax, %rsi
|
||||
movsx %eax, %rsi
|
||||
movsx (%rax), %edx
|
||||
movsx (%rax), %rdx
|
||||
movsx (%rax), %dx
|
||||
@ -203,6 +209,11 @@ cmpxchg16b oword ptr [rax]
|
||||
movswl (%rax), %edx
|
||||
movswq (%rax), %rdx
|
||||
|
||||
movzx %al, %si
|
||||
movzx %al, %esi
|
||||
movzx %al, %rsi
|
||||
movzx %ax, %esi
|
||||
movzx %ax, %rsi
|
||||
movzx (%rax), %edx
|
||||
movzx (%rax), %rdx
|
||||
movzx (%rax), %dx
|
||||
@ -216,12 +227,23 @@ cmpxchg16b oword ptr [rax]
|
||||
movzwq (%rax), %rdx
|
||||
|
||||
.intel_syntax noprefix
|
||||
movsx si,al
|
||||
movsx esi,al
|
||||
movsx rsi,al
|
||||
movsx esi,ax
|
||||
movsx rsi,ax
|
||||
movsx rsi,eax
|
||||
movsx edx,BYTE PTR [rax]
|
||||
movsx rdx,BYTE PTR [rax]
|
||||
movsx dx,BYTE PTR [rax]
|
||||
movsx edx,WORD PTR [rax]
|
||||
movsx rdx,WORD PTR [rax]
|
||||
|
||||
movzx si,al
|
||||
movzx esi,al
|
||||
movzx rsi,al
|
||||
movzx esi,ax
|
||||
movzx rsi,ax
|
||||
movzx edx,BYTE PTR [rax]
|
||||
movzx rdx,BYTE PTR [rax]
|
||||
movzx dx,BYTE PTR [rax]
|
||||
@ -249,10 +271,21 @@ cmpxchg16b oword ptr [rax]
|
||||
movsx (%rax),%ax
|
||||
movsx (%rax),%eax
|
||||
movsx (%rax),%rax
|
||||
movsxb (%rax), %dx
|
||||
movsxb (%rax), %edx
|
||||
movsxb (%rax), %rdx
|
||||
movsxw (%rax), %edx
|
||||
movsxw (%rax), %rdx
|
||||
movsxl (%rax), %rdx
|
||||
movsxd (%rax),%rax
|
||||
movzx (%rax),%ax
|
||||
movzx (%rax),%eax
|
||||
movzx (%rax),%rax
|
||||
movzxb (%rax), %dx
|
||||
movzxb (%rax), %edx
|
||||
movzxb (%rax), %rdx
|
||||
movzxw (%rax), %edx
|
||||
movzxw (%rax), %rdx
|
||||
|
||||
movnti %eax, (%rax)
|
||||
movntil %eax, (%rax)
|
||||
|
||||
@ -1,3 +1,8 @@
|
||||
2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
|
||||
* i386-tbl.h: Regenerated.
|
||||
|
||||
2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* i386-dis.c (Mx): New.
|
||||
|
||||
@ -64,6 +64,8 @@ movswq, 2, 0xfbf, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|
|
||||
movslq, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 }
|
||||
// Intel Syntax next 3 insns
|
||||
movsx, 2, 0xfbe, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg8|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
|
||||
movsx, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg16|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 }
|
||||
movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|ATTSyntax, { Reg32|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 }
|
||||
movsx, 2, 0xfbe, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg8|Byte|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
|
||||
movsx, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg16|Word|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 }
|
||||
movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|IntelSyntax, { Reg32|Dword|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 }
|
||||
@ -84,6 +86,7 @@ movzwq, 2, 0xfb7, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|
|
||||
// Intel Syntax next 2 insns (the 64-bit variants are not particulary
|
||||
// useful since the zero extend 32->64 is implicit, but we can encode them).
|
||||
movzx, 2, 0xfb6, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg8|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
|
||||
movzx, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg16|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 }
|
||||
movzx, 2, 0xfb6, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg8|Byte|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
|
||||
movzx, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Reg16|Word|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 }
|
||||
|
||||
|
||||
@ -358,6 +358,30 @@ const template i386_optab[] =
|
||||
{ { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0 } } } },
|
||||
{ "movsx", 2, 0xfbf, None, 2,
|
||||
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 0 },
|
||||
{ { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 0, 0 } },
|
||||
{ { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0 } } } },
|
||||
{ "movsx", 2, 0x63, None, 1,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1,
|
||||
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
|
||||
1, 0 },
|
||||
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 0, 0 } },
|
||||
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0 } } } },
|
||||
{ "movsx", 2, 0xfbe, None, 2,
|
||||
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
@ -490,6 +514,18 @@ const template i386_optab[] =
|
||||
{ { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0 } } } },
|
||||
{ "movzx", 2, 0xfb7, None, 2,
|
||||
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 0 },
|
||||
{ { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 0, 0 } },
|
||||
{ { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0 } } } },
|
||||
{ "movzx", 2, 0xfb6, None, 2,
|
||||
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
|
||||
Loading…
Reference in New Issue
Block a user