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[GAS][AARCH64]Add group relocations to create PC-relative offset. 

This is a patch to add the gas support for group relocations to create a
16, 32, 48, or 64 bit PC-relative offset inline.

The following relocations are added along with the test cases:
BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G3.

bfd/

2018-01-24  Renlin Li  <renlin.li@arm.com>

	* reloc.c: Add BFD_RELOC_AARCH64_MOVW_PREL_G0,
	BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, BFD_RELOC_AARCH64_MOVW_PREL_G1,
	BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, BFD_RELOC_AARCH64_MOVW_PREL_G2,
	BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, BFD_RELOC_AARCH64_MOVW_PREL_G3.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
	* elfnn-aarch64.c (elfNN_aarch64_howto_table): Add entries for
	BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
	BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
	BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
	BFD_RELOC_AARCH64_MOVW_PREL_G3.

gas/

2018-01-24  Renlin Li  <renlin.li@arm.com>

	* config/tc-aarch64.c (reloc_table): add entries for
	BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
	BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
	BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
	BFD_RELOC_AARCH64_MOVW_PREL_G3.
	(process_movw_reloc_info): Supports newly added MOVW_PREL relocations.
	(md_apply_fix): Likewise
	* testsuite/gas/aarch64/prel_g0.s: New.
	* testsuite/gas/aarch64/prel_g0.d: New.
	* testsuite/gas/aarch64/prel_g0_nc.s: New.
	* testsuite/gas/aarch64/prel_g0_nc.d: New.
	* testsuite/gas/aarch64/prel_g1.s: New.
	* testsuite/gas/aarch64/prel_g1.d: New.
	* testsuite/gas/aarch64/prel_g1_nc.s: New.
	* testsuite/gas/aarch64/prel_g1_nc.d: New.
	* testsuite/gas/aarch64/prel_g2.s: New.
	* testsuite/gas/aarch64/prel_g2.d: New.
	* testsuite/gas/aarch64/prel_g2_nc.s: New.
	* testsuite/gas/aarch64/prel_g2_nc.d: New.
	* testsuite/gas/aarch64/prel_g3.s: New.
	* testsuite/gas/aarch64/prel_g3.d: New.
This commit is contained in:
Renlin Li 2018-01-18 12:08:40 +00:00
parent cc40406d1d
commit 322474019d
21 changed files with 459 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
bfd/ChangeLog
View File

@ -1,3 +1,17 @@
2018-01-24 Renlin Li <renlin.li@arm.com>
* reloc.c: Add BFD_RELOC_AARCH64_MOVW_PREL_G0,
BFD_RELOC_AARCH64_MOVW_PREL_G0_NC, BFD_RELOC_AARCH64_MOVW_PREL_G1,
BFD_RELOC_AARCH64_MOVW_PREL_G1_NC, BFD_RELOC_AARCH64_MOVW_PREL_G2,
BFD_RELOC_AARCH64_MOVW_PREL_G2_NC, BFD_RELOC_AARCH64_MOVW_PREL_G3.
* elfnn-aarch64.c (elfNN_aarch64_howto_table): Add entries for
BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G3.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
2018-01-23 Maciej W. Rozycki <macro@mips.com>
* elfxx-mips.c (_bfd_mips_elf_final_link): Update a stale

30
bfd/bfd-in2.h
View File

@ -5957,6 +5957,36 @@ of a signed value. Changes instruction to MOVZ or MOVN depending on the
value's sign. */
BFD_RELOC_AARCH64_MOVW_G2_S,
/* AArch64 MOV[NZ] instruction with most significant bits 0 to 15
of a signed value. Changes instruction to MOVZ or MOVN depending on the
value's sign. */
BFD_RELOC_AARCH64_MOVW_PREL_G0,
/* AArch64 MOV[NZ] instruction with most significant bits 0 to 15
of a signed value. Changes instruction to MOVZ or MOVN depending on the
value's sign. */
BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
/* AArch64 MOVK instruction with most significant bits 16 to 31
of a signed value. */
BFD_RELOC_AARCH64_MOVW_PREL_G1,
/* AArch64 MOVK instruction with most significant bits 16 to 31
of a signed value. */
BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
/* AArch64 MOVK instruction with most significant bits 32 to 47
of a signed value. */
BFD_RELOC_AARCH64_MOVW_PREL_G2,
/* AArch64 MOVK instruction with most significant bits 32 to 47
of a signed value. */
BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
/* AArch64 MOVK instruction with most significant bits 47 to 63
of a signed value. */
BFD_RELOC_AARCH64_MOVW_PREL_G3,
/* AArch64 Load Literal instruction, holding a 19 bit pc-relative word
offset. The lowest two bits must be zero and are not stored in the
instruction, giving a 21 bit signed byte offset. */

108
bfd/elfnn-aarch64.c
View File

@ -617,6 +617,114 @@ static reloc_howto_type elfNN_aarch64_howto_table[] =
0xffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* Group relocations to create a 16, 32, 48 or 64 bit
PC relative address inline. */
/* MOV[NZ]: ((S+A-P) >> 0) & 0xffff */
HOWTO64 (AARCH64_R (MOVW_PREL_G0), /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
17, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
AARCH64_R_STR (MOVW_PREL_G0), /* name */
FALSE, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
TRUE), /* pcrel_offset */
/* MOVK: ((S+A-P) >> 0) & 0xffff [no overflow check] */
HOWTO64 (AARCH64_R (MOVW_PREL_G0_NC), /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
AARCH64_R_STR (MOVW_PREL_G0_NC), /* name */
FALSE, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
TRUE), /* pcrel_offset */
/* MOV[NZ]: ((S+A-P) >> 16) & 0xffff */
HOWTO64 (AARCH64_R (MOVW_PREL_G1), /* type */
16, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
17, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
AARCH64_R_STR (MOVW_PREL_G1), /* name */
FALSE, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
TRUE), /* pcrel_offset */
/* MOVK: ((S+A-P) >> 16) & 0xffff [no overflow check] */
HOWTO64 (AARCH64_R (MOVW_PREL_G1_NC), /* type */
16, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
AARCH64_R_STR (MOVW_PREL_G1_NC), /* name */
FALSE, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
TRUE), /* pcrel_offset */
/* MOV[NZ]: ((S+A-P) >> 32) & 0xffff */
HOWTO64 (AARCH64_R (MOVW_PREL_G2), /* type */
32, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
17, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_signed, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
AARCH64_R_STR (MOVW_PREL_G2), /* name */
FALSE, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
TRUE), /* pcrel_offset */
/* MOVK: ((S+A-P) >> 32) & 0xffff [no overflow check] */
HOWTO64 (AARCH64_R (MOVW_PREL_G2_NC), /* type */
32, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
AARCH64_R_STR (MOVW_PREL_G2_NC), /* name */
FALSE, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
TRUE), /* pcrel_offset */
/* MOV[NZ]: ((S+A-P) >> 48) & 0xffff */
HOWTO64 (AARCH64_R (MOVW_PREL_G3), /* type */
48, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
16, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
AARCH64_R_STR (MOVW_PREL_G3), /* name */
FALSE, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
TRUE), /* pcrel_offset */
/* Relocations to generate 19, 21 and 33 bit PC-relative load/store
addresses: PG(x) is (x & ~0xfff). */

7
bfd/libbfd.h
View File

@ -2887,6 +2887,13 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_AARCH64_MOVW_G0_S",
"BFD_RELOC_AARCH64_MOVW_G1_S",
"BFD_RELOC_AARCH64_MOVW_G2_S",
"BFD_RELOC_AARCH64_MOVW_PREL_G0",
"BFD_RELOC_AARCH64_MOVW_PREL_G0_NC",
"BFD_RELOC_AARCH64_MOVW_PREL_G1",
"BFD_RELOC_AARCH64_MOVW_PREL_G1_NC",
"BFD_RELOC_AARCH64_MOVW_PREL_G2",
"BFD_RELOC_AARCH64_MOVW_PREL_G2_NC",
"BFD_RELOC_AARCH64_MOVW_PREL_G3",
"BFD_RELOC_AARCH64_LD_LO19_PCREL",
"BFD_RELOC_AARCH64_ADR_LO21_PCREL",
"BFD_RELOC_AARCH64_ADR_HI21_PCREL",

37
bfd/reloc.c
View File

@ -7070,6 +7070,43 @@ ENUMDOC
AArch64 MOV[NZ] instruction with most significant bits 32 to 47
of a signed value. Changes instruction to MOVZ or MOVN depending on the
value's sign.
ENUM
BFD_RELOC_AARCH64_MOVW_PREL_G0
ENUMDOC
AArch64 MOV[NZ] instruction with most significant bits 0 to 15
of a signed value. Changes instruction to MOVZ or MOVN depending on the
value's sign.
ENUM
BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
ENUMDOC
AArch64 MOV[NZ] instruction with most significant bits 0 to 15
of a signed value. Changes instruction to MOVZ or MOVN depending on the
value's sign.
ENUM
BFD_RELOC_AARCH64_MOVW_PREL_G1
ENUMDOC
AArch64 MOVK instruction with most significant bits 16 to 31
of a signed value.
ENUM
BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
ENUMDOC
AArch64 MOVK instruction with most significant bits 16 to 31
of a signed value.
ENUM
BFD_RELOC_AARCH64_MOVW_PREL_G2
ENUMDOC
AArch64 MOVK instruction with most significant bits 32 to 47
of a signed value.
ENUM
BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
ENUMDOC
AArch64 MOVK instruction with most significant bits 32 to 47
of a signed value.
ENUM
BFD_RELOC_AARCH64_MOVW_PREL_G3
ENUMDOC
AArch64 MOVK instruction with most significant bits 47 to 63
of a signed value.
ENUM
BFD_RELOC_AARCH64_LD_LO19_PCREL
ENUMDOC

24
gas/ChangeLog
View File

@ -1,3 +1,27 @@
2018-01-24 Renlin Li <renlin.li@arm.com>
* config/tc-aarch64.c (reloc_table): add entries for
BFD_RELOC_AARCH64_MOVW_PREL_G0, BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G1, BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G2, BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
BFD_RELOC_AARCH64_MOVW_PREL_G3.
(process_movw_reloc_info): Supports newly added MOVW_PREL relocations.
(md_apply_fix): Likewise
* testsuite/gas/aarch64/prel_g0.s: New.
* testsuite/gas/aarch64/prel_g0.d: New.
* testsuite/gas/aarch64/prel_g0_nc.s: New.
* testsuite/gas/aarch64/prel_g0_nc.d: New.
* testsuite/gas/aarch64/prel_g1.s: New.
* testsuite/gas/aarch64/prel_g1.d: New.
* testsuite/gas/aarch64/prel_g1_nc.s: New.
* testsuite/gas/aarch64/prel_g1_nc.d: New.
* testsuite/gas/aarch64/prel_g2.s: New.
* testsuite/gas/aarch64/prel_g2.d: New.
* testsuite/gas/aarch64/prel_g2_nc.s: New.
* testsuite/gas/aarch64/prel_g2_nc.d: New.
* testsuite/gas/aarch64/prel_g3.s: New.
* testsuite/gas/aarch64/prel_g3.d: New.
2018-01-23 Maciej W. Rozycki <macro@mips.com>
* configure.ac: Also set `mips_default_abi' to N32_ABI for

84
gas/config/tc-aarch64.c
View File

@ -2577,6 +2577,69 @@ static struct reloc_table_entry reloc_table[] = {
0,
0},
/* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
{"prel_g0", 1,
0, /* adr_type */
0,
BFD_RELOC_AARCH64_MOVW_PREL_G0,
0,
0,
0},
/* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
{"prel_g0_nc", 1,
0, /* adr_type */
0,
BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
0,
0,
0},
/* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
{"prel_g1", 1,
0, /* adr_type */
0,
BFD_RELOC_AARCH64_MOVW_PREL_G1,
0,
0,
0},
/* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
{"prel_g1_nc", 1,
0, /* adr_type */
0,
BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
0,
0,
0},
/* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
{"prel_g2", 1,
0, /* adr_type */
0,
BFD_RELOC_AARCH64_MOVW_PREL_G2,
0,
0,
0},
/* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
{"prel_g2_nc", 1,
0, /* adr_type */
0,
BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
0,
0,
0},
/* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
{"prel_g3", 1,
0, /* adr_type */
0,
BFD_RELOC_AARCH64_MOVW_PREL_G3,
0,
0,
0},
/* Get to the page containing GOT entry for a symbol. */
{"got", 1,
0, /* adr_type */
@ -5079,6 +5142,10 @@ process_movw_reloc_info (void)
case BFD_RELOC_AARCH64_MOVW_G0_S:
case BFD_RELOC_AARCH64_MOVW_G1_S:
case BFD_RELOC_AARCH64_MOVW_G2_S:
case BFD_RELOC_AARCH64_MOVW_PREL_G0:
case BFD_RELOC_AARCH64_MOVW_PREL_G1:
case BFD_RELOC_AARCH64_MOVW_PREL_G2:
case BFD_RELOC_AARCH64_MOVW_PREL_G3:
case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
@ -5096,6 +5163,8 @@ process_movw_reloc_info (void)
case BFD_RELOC_AARCH64_MOVW_G0_NC:
case BFD_RELOC_AARCH64_MOVW_G0_S:
case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC:
case BFD_RELOC_AARCH64_MOVW_PREL_G0:
case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC:
case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC:
case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC:
@ -5109,6 +5178,8 @@ process_movw_reloc_info (void)
case BFD_RELOC_AARCH64_MOVW_G1_NC:
case BFD_RELOC_AARCH64_MOVW_G1_S:
case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
case BFD_RELOC_AARCH64_MOVW_PREL_G1:
case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC:
case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1:
@ -5121,6 +5192,8 @@ process_movw_reloc_info (void)
case BFD_RELOC_AARCH64_MOVW_G2:
case BFD_RELOC_AARCH64_MOVW_G2_NC:
case BFD_RELOC_AARCH64_MOVW_G2_S:
case BFD_RELOC_AARCH64_MOVW_PREL_G2:
case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC:
case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
if (is32)
@ -5133,6 +5206,7 @@ process_movw_reloc_info (void)
shift = 32;
break;
case BFD_RELOC_AARCH64_MOVW_G3:
case BFD_RELOC_AARCH64_MOVW_PREL_G3:
if (is32)
{
set_fatal_syntax_error
@ -7608,12 +7682,16 @@ md_apply_fix (fixS * fixP, valueT * valP, segT seg)
case BFD_RELOC_AARCH64_MOVW_G0_NC:
case BFD_RELOC_AARCH64_MOVW_G0_S:
case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC:
case BFD_RELOC_AARCH64_MOVW_PREL_G0:
case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC:
scale = 0;
goto movw_common;
case BFD_RELOC_AARCH64_MOVW_G1:
case BFD_RELOC_AARCH64_MOVW_G1_NC:
case BFD_RELOC_AARCH64_MOVW_G1_S:
case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
case BFD_RELOC_AARCH64_MOVW_PREL_G1:
case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC:
scale = 16;
goto movw_common;
case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
@ -7635,9 +7713,12 @@ md_apply_fix (fixS * fixP, valueT * valP, segT seg)
case BFD_RELOC_AARCH64_MOVW_G2:
case BFD_RELOC_AARCH64_MOVW_G2_NC:
case BFD_RELOC_AARCH64_MOVW_G2_S:
case BFD_RELOC_AARCH64_MOVW_PREL_G2:
case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC:
scale = 32;
goto movw_common;
case BFD_RELOC_AARCH64_MOVW_G3:
case BFD_RELOC_AARCH64_MOVW_PREL_G3:
scale = 48;
movw_common:
if (fixP->fx_done || !seg->use_rela_p)
@ -7669,6 +7750,9 @@ md_apply_fix (fixS * fixP, valueT * valP, segT seg)
case BFD_RELOC_AARCH64_MOVW_G0_S:
case BFD_RELOC_AARCH64_MOVW_G1_S:
case BFD_RELOC_AARCH64_MOVW_G2_S:
case BFD_RELOC_AARCH64_MOVW_PREL_G0:
case BFD_RELOC_AARCH64_MOVW_PREL_G1:
case BFD_RELOC_AARCH64_MOVW_PREL_G2:
/* NOTE: We can only come here with movz or movn. */
if (signed_overflow (value, scale + 16))
as_bad_where (fixP->fx_file, fixP->fx_line,

13
gas/testsuite/gas/aarch64/reloc-prel_g0.d Normal file
View File

@ -0,0 +1,13 @@
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 8a000000 and x0, x0, x0
4: 92400000 and x0, x0, #0x1
8: d2800004 mov x4, #0x0 // #0
8: R_AARCH64_MOVW_PREL_G0 tempy
c: d2800011 mov x17, #0x0 // #0
c: R_AARCH64_MOVW_PREL_G0 tempy2

7
gas/testsuite/gas/aarch64/reloc-prel_g0.s Normal file
View File

@ -0,0 +1,7 @@
.comm gempy,4,4
.text
and x0,x0,x0
and x0,x0,#0x1
movz x4, :prel_g0:tempy
movz x17, :prel_g0:tempy2

15
gas/testsuite/gas/aarch64/reloc-prel_g0_nc.d Normal file
View File

@ -0,0 +1,15 @@
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 8a000000 and x0, x0, x0
4: 92400000 and x0, x0, #0x1
8: f2800004 movk x4, #0x0
8: R_AARCH64_MOVW_PREL_G0_NC tempy
c: f2800007 movk x7, #0x0
c: R_AARCH64_MOVW_PREL_G0_NC tempy2
10: f2800011 movk x17, #0x0
10: R_AARCH64_MOVW_PREL_G0_NC tempy3

8
gas/testsuite/gas/aarch64/reloc-prel_g0_nc.s Normal file
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@ -0,0 +1,8 @@
.comm gempy,4,4
.text
and x0,x0,x0
and x0,x0,#0x1
movk x4, :prel_g0_nc:tempy
movk x7, :prel_g0_nc:tempy2
movk x17, :prel_g0_nc:tempy3

13
gas/testsuite/gas/aarch64/reloc-prel_g1.d Normal file
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@ -0,0 +1,13 @@
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 8a000000 and x0, x0, x0
4: 92400000 and x0, x0, #0x1
8: d2a00004 movz x4, #0x0, lsl #16
8: R_AARCH64_MOVW_PREL_G1 tempy
c: d2a00011 movz x17, #0x0, lsl #16
c: R_AARCH64_MOVW_PREL_G1 tempy2

7
gas/testsuite/gas/aarch64/reloc-prel_g1.s Normal file
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@ -0,0 +1,7 @@
.comm gempy,4,4
.text
and x0,x0,x0
and x0,x0,#0x1
movz x4, :prel_g1:tempy
movz x17, :prel_g1:tempy2

15
gas/testsuite/gas/aarch64/reloc-prel_g1_nc.d Normal file
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@ -0,0 +1,15 @@
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 8a000000 and x0, x0, x0
4: 92400000 and x0, x0, #0x1
8: f2a00004 movk x4, #0x0, lsl #16
8: R_AARCH64_MOVW_PREL_G1_NC tempy
c: f2a00007 movk x7, #0x0, lsl #16
c: R_AARCH64_MOVW_PREL_G1_NC tempy2
10: f2a00011 movk x17, #0x0, lsl #16
10: R_AARCH64_MOVW_PREL_G1_NC tempy3

8
gas/testsuite/gas/aarch64/reloc-prel_g1_nc.s Normal file
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@ -0,0 +1,8 @@
.comm gempy,4,4
.text
and x0,x0,x0
and x0,x0,#0x1
movk x4, :prel_g1_nc:tempy
movk x7, :prel_g1_nc:tempy2
movk x17, :prel_g1_nc:tempy3

15
gas/testsuite/gas/aarch64/reloc-prel_g2.d Normal file
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@ -0,0 +1,15 @@
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 8a000000 and x0, x0, x0
4: 92400000 and x0, x0, #0x1
8: d2c00004 movz x4, #0x0, lsl #32
8: R_AARCH64_MOVW_PREL_G2 tempy
c: d2c00007 movz x7, #0x0, lsl #32
c: R_AARCH64_MOVW_PREL_G2 tempy2
10: d2c00011 movz x17, #0x0, lsl #32
10: R_AARCH64_MOVW_PREL_G2 tempy3

8
gas/testsuite/gas/aarch64/reloc-prel_g2.s Normal file
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@ -0,0 +1,8 @@
.comm gempy,4,4
.text
and x0,x0,x0
and x0,x0,#0x1
movz x4, :prel_g2:tempy
movz x7, :prel_g2:tempy2
movz x17, :prel_g2:tempy3

15
gas/testsuite/gas/aarch64/reloc-prel_g2_nc.d Normal file
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@ -0,0 +1,15 @@
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 8a000000 and x0, x0, x0
4: 92400000 and x0, x0, #0x1
8: f2c00004 movk x4, #0x0, lsl #32
8: R_AARCH64_MOVW_PREL_G2_NC tempy
c: f2c00007 movk x7, #0x0, lsl #32
c: R_AARCH64_MOVW_PREL_G2_NC tempy2
10: f2c00011 movk x17, #0x0, lsl #32
10: R_AARCH64_MOVW_PREL_G2_NC tempy3

8
gas/testsuite/gas/aarch64/reloc-prel_g2_nc.s Normal file
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@ -0,0 +1,8 @@
.comm gempy,4,4
.text
and x0,x0,x0
and x0,x0,#0x1
movk x4, :prel_g2_nc:tempy
movk x7, :prel_g2_nc:tempy2
movk x17, :prel_g2_nc:tempy3

15
gas/testsuite/gas/aarch64/reloc-prel_g3.d Normal file
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@ -0,0 +1,15 @@
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 8a000000 and x0, x0, x0
4: 92400000 and x0, x0, #0x1
8: d2e00004 movz x4, #0x0, lsl #48
8: R_AARCH64_MOVW_PREL_G3 tempy
c: d2e00007 movz x7, #0x0, lsl #48
c: R_AARCH64_MOVW_PREL_G3 tempy2
10: d2e00011 movz x17, #0x0, lsl #48
10: R_AARCH64_MOVW_PREL_G3 tempy3

8
gas/testsuite/gas/aarch64/reloc-prel_g3.s Normal file
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@ -0,0 +1,8 @@
.comm gempy,4,4
.text
and x0,x0,x0
and x0,x0,#0x1
movz x4, :prel_g3:tempy
movz x7, :prel_g3:tempy2
movz x17, :prel_g3:tempy3