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Enable Intel WBNOINVD instruction. 

Intel has disclosed a set of new instructions for Icelake processor.
The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

This patch enables Intel WBNOINVD instruction.

gas/
	* config/tc-i386.c (cpu_arch): Add .wbnoinvd.
	* doc/c-i386.texi: Document .wbnoinvd.
	* testsuite/gas/i386/i386.exp: Add WBNOINVD tests.
	* testsuite/gas/i386/wbnoinvd-intel.d: New test.
	* testsuite/gas/i386/wbnoinvd.d: Likewise.
	* testsuite/gas/i386/wbnoinvd.s: Likewise.
	* testsuite/gas/i386/x86-64-wbnoinvd-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-wbnoinvd.d: Likewise.
	* testsuite/gas/i386/x86-64-wbnoinvd.s: Likewise.
opcodes/
	* i386-dis.c (enum): Add PREFIX_0F09.
	* i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
	(cpu_flags): Add CpuWBNOINVD.
	* i386-opc.h (enum): Add CpuWBNOINVD.
	(i386_cpu_flags): Add cpuwbnoinvd.
	* i386-opc.tbl: Add WBNOINVD instruction.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
This commit is contained in:
Igor Tsimbalist 2018-01-23 19:39:05 +03:00
parent b4f6242e95
commit 3233d7d074
17 changed files with 5609 additions and 5483 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
gas/ChangeLog
View File

@ -1,3 +1,15 @@
2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* config/tc-i386.c (cpu_arch): Add .wbnoinvd.
* doc/c-i386.texi: Document .wbnoinvd.
* testsuite/gas/i386/i386.exp: Add WBNOINVD tests.
* testsuite/gas/i386/wbnoinvd-intel.d: New test.
* testsuite/gas/i386/wbnoinvd.d: Likewise.
* testsuite/gas/i386/wbnoinvd.s: Likewise.
* testsuite/gas/i386/x86-64-wbnoinvd-intel.d: Likewise.
* testsuite/gas/i386/x86-64-wbnoinvd.d: Likewise.
* testsuite/gas/i386/x86-64-wbnoinvd.s: Likewise.
2018-01-23 Maciej W. Rozycki <macro@mips.com>
* config/tc-mips.c (md_show_usage): Correctly indicate the

2
gas/config/tc-i386.c
View File

@ -1007,6 +1007,8 @@ static const arch_entry cpu_arch[] =
CPU_VAES_FLAGS, 0 },
{ STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
CPU_VPCLMULQDQ_FLAGS, 0 },
{ STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
CPU_WBNOINVD_FLAGS, 0 },
};
static const noarch_entry cpu_noarch[] =

2
gas/doc/c-i386.texi
View File

@ -229,6 +229,7 @@ accept various extension mnemonics. For example,
@code{clflush},
@code{mwaitx},
@code{clzero},
@code{wbnoinvd},
@code{lwp},
@code{fma4},
@code{xop},
@ -1240,6 +1241,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
@item @samp{.avx512_bitalg}
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt}
@item @samp{.wbnoinvd}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}

4
gas/testsuite/gas/i386/i386.exp
View File

@ -413,6 +413,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "vaes-intel"
run_dump_test "vpclmulqdq"
run_dump_test "vpclmulqdq-intel"
run_dump_test "wbnoinvd"
run_dump_test "wbnoinvd-intel"
run_list_test "avx512vl-1" "-al"
run_list_test "avx512vl-2" "-al"
run_dump_test "fpu-bad"
@ -880,6 +882,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
run_dump_test "x86-64-vaes-intel"
run_dump_test "x86-64-vpclmulqdq"
run_dump_test "x86-64-vpclmulqdq-intel"
run_dump_test "x86-64-wbnoinvd"
run_dump_test "x86-64-wbnoinvd-intel"
run_dump_test "x86-64-fence-as-lock-add-yes"
run_dump_test "x86-64-fence-as-lock-add-no"
run_dump_test "x86-64-pr20141"

11
gas/testsuite/gas/i386/wbnoinvd-intel.d Normal file
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@ -0,0 +1,11 @@
#objdump: -dwMintel
#name: i386 WBNOINVD (Intel disassembly)
#source: wbnoinvd.s
.*: +file format .*
Disassembly of section .text:
0+ <_start>:
[ ]*[a-f0-9]+:[ ]*f3 0f 09[ ]*wbnoinvd[ ]*
#pass

11
gas/testsuite/gas/i386/wbnoinvd.d Normal file
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@ -0,0 +1,11 @@
#objdump: -dw
#name: i386 WBNOINVD insn
.*: +file format .*
Disassembly of section .text:
0+ <_start>:
[ ]*[a-f0-9]+:[ ]*f3 0f 09[ ]*wbnoinvd[ ]*
#pass

5
gas/testsuite/gas/i386/wbnoinvd.s Normal file
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@ -0,0 +1,5 @@
# Check 32bit WBNOINVD instructions.
.text
_start:
wbnoinvd

11
gas/testsuite/gas/i386/x86-64-wbnoinvd-intel.d Normal file
View File

@ -0,0 +1,11 @@
#objdump: -dwMintel
#name: i386 WBNOINVD (Intel disassembly)
#source: wbnoinvd.s
.*: +file format .*
Disassembly of section .text:
0+ <_start>:
[ ]*[a-f0-9]+:[ ]*f3 0f 09[ ]*wbnoinvd[ ]*
#pass

11
gas/testsuite/gas/i386/x86-64-wbnoinvd.d Normal file
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@ -0,0 +1,11 @@
#objdump: -dw
#name: i386 WBNOINVD insn
.*: +file format .*
Disassembly of section .text:
0+ <_start>:
[ ]*[a-f0-9]+:[ ]*f3 0f 09[ ]*wbnoinvd[ ]*
#pass

5
gas/testsuite/gas/i386/x86-64-wbnoinvd.s Normal file
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@ -0,0 +1,5 @@
# Check 64bit WBNOINVD instructions.
.text
_start:
wbnoinvd

11
opcodes/ChangeLog
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@ -1,3 +1,14 @@
2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* i386-dis.c (enum): Add PREFIX_0F09.
* i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
(cpu_flags): Add CpuWBNOINVD.
* i386-opc.h (enum): Add CpuWBNOINVD.
(i386_cpu_flags): Add cpuwbnoinvd.
* i386-opc.tbl: Add WBNOINVD instruction.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
2018-01-17 Jim Wilson <jimw@sifive.com>
* riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.

9
opcodes/i386-dis.c
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@ -956,6 +956,7 @@ enum
PREFIX_MOD_0_0F01_REG_5,
PREFIX_MOD_3_0F01_REG_5_RM_0,
PREFIX_MOD_3_0F01_REG_5_RM_2,
PREFIX_0F09,
PREFIX_0F10,
PREFIX_0F11,
PREFIX_0F12,
@ -2869,7 +2870,7 @@ static const struct dis386 dis386_twobyte[] = {
{ "sysret%LP", { XX }, 0 },
/* 08 */
{ "invd", { XX }, 0 },
{ "wbinvd", { XX }, 0 },
{ PREFIX_TABLE (PREFIX_0F09) },
{ Bad_Opcode },
{ "ud2", { XX }, 0 },
{ Bad_Opcode },
@ -3840,6 +3841,12 @@ static const struct dis386 prefix_table[][4] = {
{ "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
},
/* PREFIX_0F09 */
{
{ "wbinvd", { XX }, 0 },
{ "wbnoinvd", { XX }, 0 },
},
/* PREFIX_0F10 */
{
{ "movups", { XM, EXx }, PREFIX_OPCODE },

3
opcodes/i386-gen.c
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@ -279,6 +279,8 @@ static initializer cpu_flag_init[] =
"CpuVAES" },
{ "CPU_VPCLMULQDQ_FLAGS",
"CpuVPCLMULQDQ" },
{ "CPU_WBNOINVD_FLAGS",
"CpuWBNOINVD" },
{ "CPU_ANY_X87_FLAGS",
"CPU_ANY_287_FLAGS|Cpu8087" },
{ "CPU_ANY_287_FLAGS",
@ -569,6 +571,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuGFNI),
BITFIELD (CpuVAES),
BITFIELD (CpuVPCLMULQDQ),
BITFIELD (CpuWBNOINVD),
BITFIELD (CpuRegMMX),
BITFIELD (CpuRegXMM),
BITFIELD (CpuRegYMM),

414
opcodes/i386-init.h
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File diff suppressed because it is too large Load Diff

3
opcodes/i386-opc.h
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@ -223,6 +223,8 @@ enum
CpuVAES,
/* VPCLMULQDQ instructions required */
CpuVPCLMULQDQ,
/* WBNOINVD instructions required */
CpuWBNOINVD,
/* MMX register support required */
CpuRegMMX,
/* XMM register support required */
@ -352,6 +354,7 @@ typedef union i386_cpu_flags
unsigned int cpugfni:1;
unsigned int cpuvaes:1;
unsigned int cpuvpclmulqdq:1;
unsigned int cpuwbnoinvd:1;
unsigned int cpuregmmx:1;
unsigned int cpuregxmm:1;
unsigned int cpuregymm:1;

6
opcodes/i386-opc.tbl
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@ -6133,3 +6133,9 @@ endbr32, 0, 0xf30f1efb, None, 3, CpuIBT, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_s
notrack, 0, 0x3e, None, 1, CpuIBT, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
// CET instructions end.
// WBNOINVD instruction.
wbnoinvd, 0, 0xf30f09, None, 2, CpuWBNOINVD, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
// WBNOINVD instruction end.

10572
opcodes/i386-tbl.h
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