Add --enable-special command line switch.
This commit is contained in:
Nick Clifton
parent
ab26b0497a
commit
32c2be7633
@ -1,3 +1,11 @@
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start-sanitize-m32rx
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Tue May 12 13:34:12 1998 Nick Clifton <nickc@cygnus.com>
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* config/tc-m32r.c: Add command line switch to support special
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M32Rx instructions.
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* doc/c-m32r.texi: Document new command line switch.
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end-sanitize-m32rx
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Tue May 12 12:03:44 1998 Richard Henderson <rth@cygnus.com>
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* config/tc-d30v.c (cur_mul32_p, prev_mul32_p): Make static.
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@ -75,10 +75,14 @@ static int m32r_relax;
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static char * m32r_cpu_desc;
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/* start-sanitize-m32rx */
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/* Non-zero if -m32rx has been specified, in which case support for the
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/* Non-zero if --m32rx has been specified, in which case support for the
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extended M32RX instruction set should be enabled. */
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static int enable_m32rx = 0;
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/* Non-zero if --enable-special has been specified, in which case support for
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the special M32RX instruction set should be enabled. */
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static int enable_special = 0;
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/* Non-zero if the programmer should be warned when an explicit parallel
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instruction might have constraint violations. */
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static int warn_explicit_parallel_conflicts = 1;
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@ -153,12 +157,14 @@ struct option md_longopts[] =
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#define OPTION_NO_WARN (OPTION_MD_BASE + 2)
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{"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN},
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{"Wnp", no_argument, NULL, OPTION_NO_WARN},
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#define OPTION_SPECIAL (OPTION_MD_BASE + 3)
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{"enable-special", no_argument, NULL, OPTION_SPECIAL},
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/* end-sanitize-m32rx */
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#if 0 /* not supported yet */
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#define OPTION_RELAX (OPTION_MD_BASE + 3)
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#define OPTION_RELAX (OPTION_MD_BASE + 4)
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{"relax", no_argument, NULL, OPTION_RELAX},
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#define OPTION_CPU_DESC (OPTION_MD_BASE + 4)
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#define OPTION_CPU_DESC (OPTION_MD_BASE + 5)
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{"cpu-desc", required_argument, NULL, OPTION_CPU_DESC},
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#endif
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@ -189,6 +195,11 @@ md_parse_option (c, arg)
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case OPTION_NO_WARN:
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warn_explicit_parallel_conflicts = 0;
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break;
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case OPTION_SPECIAL:
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allow_m32rx (1);
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enable_special = 1;
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break;
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/* end-sanitize-m32rx */
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#if 0 /* not supported yet */
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@ -213,6 +224,8 @@ md_show_usage (stream)
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fprintf (stream, _("M32R/X specific command line options:\n"));
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fprintf (stream, _("\
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--m32rx support the extended m32rx instruction set\n"));
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fprintf (stream, _("\
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--enable-special support the special m32rx instructions\n"));
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fprintf (stream, _("\
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-O try to combine instructions in parallel\n"));
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@ -701,14 +714,24 @@ assemble_parallel_insn (str, str2)
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return;
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}
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if (! enable_m32rx
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if (! enable_special
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&& CGEN_INSN_ATTR (first.insn, CGEN_INSN_SPECIAL))
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{
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/* xgettext:c-format */
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as_bad (_("unknown instruction '%s'"), str);
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return;
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}
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else if (! enable_m32rx
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/* FIXME: Need standard macro to perform this test. */
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&& CGEN_INSN_ATTR (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
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{
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/* xgettext:c-format */
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as_bad (_("instruction '%s' is for the M32RX only"), str);
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return;
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}
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/* Check to see if this is an allowable parallel insn. */
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if (CGEN_INSN_ATTR (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
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{
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@ -752,9 +775,18 @@ assemble_parallel_insn (str, str2)
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}
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/* Check it. */
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if (! enable_m32rx
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if (! enable_special
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&& CGEN_INSN_ATTR (second.insn, CGEN_INSN_SPECIAL))
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{
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/* xgettext:c-format */
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as_bad (_("unknown instruction '%s'"), str);
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return;
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}
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else if (! enable_m32rx
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&& CGEN_INSN_ATTR (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
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{
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/* xgettext:c-format */
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as_bad (_("instruction '%s' is for the M32RX only"), str);
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return;
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}
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@ -771,6 +803,7 @@ assemble_parallel_insn (str, str2)
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if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP
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&& CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP)
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{
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/* xgettext:c-format */
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as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2);
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return;
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}
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@ -796,9 +829,11 @@ assemble_parallel_insn (str, str2)
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if (warn_explicit_parallel_conflicts)
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{
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if (first_writes_to_seconds_operands (& first, & second, false))
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/* xgettext:c-format */
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as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2);
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if (first_writes_to_seconds_operands (& second, & first, false))
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/* xgettext:c-format */
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as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2);
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}
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@ -887,8 +922,18 @@ md_assemble (str)
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}
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/* start-sanitize-m32rx */
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if (! enable_m32rx && CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
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if (! enable_special
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&& CGEN_INSN_ATTR (insn.insn, CGEN_INSN_SPECIAL))
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{
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/* xgettext:c-format */
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as_bad (_("unknown instruction '%s'"), str);
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return;
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}
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else if (! enable_m32rx
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&& CGEN_INSN_ATTR (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
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{
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/* xgettext:c-format */
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as_bad (_("instruction '%s' is for the M32RX only"), str);
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return;
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}
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@ -40,6 +40,13 @@ to the M32RX microprocessor, which adds some more instructions to the
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basic M32R instruction set, and some additional parameters to some of
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the original instructions.
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@item --enable-special
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@cindex @samp{--enable-special} option, M32RX
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@cindex architecture options, M32RX
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@cindex M32R architecture options
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This option is the equivalent of the @emph{--m32rx} option, except that
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it also allows the special M32RX instructions to be assembled as well.
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@item --warn-explicit-parallel-conflicts
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@cindex @samp{--warn-explicit-parallel-conflicts} option, M32RX
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Instructs @code{@value{AS}} to produce warning messages when
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@ -52,11 +59,21 @@ different result from @samp{mv r1, r2 \n mv r3, r1} since the former
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moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1
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and r3.
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@item --Wp
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@cindex @samp{--Wp} option, M32RX
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This is a shorter synonym for the @emph{--warn-explicit-parallel-conflicts}
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option.
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@item --no-warn-explicit-parallel-conflicts
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@cindex @samp{--no-warn-explicit-parallel-conflicts} option, M32RX
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Instructs @code{@value{AS}} not to produce warning messages when
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questionable parallel instructions are encountered.
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@item --Wnp
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@cindex @samp{--Wnp} option, M32RX
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This is a shorter synonym for the @emph{--no-warn-explicit-parallel-conflicts}
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option.
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@end table
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@node M32R-Warnings
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@ -94,6 +111,10 @@ which is only supported by the M32Rx processor, and the @samp{--m32rx}
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command line flag has not been specified to allow assembly of such
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instructions.
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@item unknown instruction @samp{...}
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This message is produced when the assembler encounters an instruction
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which it doe snot recognise.
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@item only the NOP instruction can be issued in parallel on the m32r
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This message is produced when the assembler encounters a parallel
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instruction which does not involve a NOP instruction and the
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@ -117,6 +138,7 @@ For example these code fragments will produce this message:
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@samp{jl r0 || mv r14, r1}
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@samp{st r2, @@-r1 || mv r1, r3}
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@samp{mv r1, r2 || ld r0, @@r1+}
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@samp{cmp r1, r2 || addx r3, r4} (Both write to the condition bit)
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@end table
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@c end-sanitize-m32rx
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