gas/
2006-02-27 H.J. Lu <hongjiu.lu@intel.com> * gas/config/tc-i386.c (output_insn): Support Intel Merom New Instructions. * gas/config/tc-i386.h (CpuMNI): New. (CpuUnknownFlags): Add CpuMNI. gas/testsuite/ 2006-02-27 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Add merom and x86-64-merom. * gas/i386/merom.d: New file. * gas/i386/merom.s: Likewise. * gas/i386/x86-64-merom.d: Likewise. * gas/i386/x86-64-merom.s: Likewise. include/opcode/ 2006-02-27 H.J. Lu <hongjiu.lu@intel.com> * i386.h (i386_optab): Support Intel Merom New Instructions. opcodes/ 2006-02-27 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by Intel Merom New Instructions. (THREE_BYTE_0): Likewise. (THREE_BYTE_1): Likewise. (three_byte_table): Likewise. (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use THREE_BYTE_1 for entry 0x3a. (twobyte_has_modrm): Updated. (twobyte_uses_SSE_prefix): Likewise. (print_insn): Handle 3-byte opcodes used by Intel Merom New Instructions.
This commit is contained in:
H.J. Lu
parent
22edb2f164
commit
331d2d0d9c
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@ -1,3 +1,11 @@
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2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
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* gas/config/tc-i386.c (output_insn): Support Intel Merom New
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Instructions.
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* gas/config/tc-i386.h (CpuMNI): New.
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(CpuUnknownFlags): Add CpuMNI.
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2006-02-24 David S. Miller <davem@sunset.davemloft.net>
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* config/tc-sparc.c (priv_reg_table): Add entry for "gl".
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@ -3474,23 +3474,31 @@ output_insn ()
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/* Output normal instructions here. */
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char *p;
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unsigned char *q;
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unsigned int prefix;
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/* All opcodes on i386 have either 1 or 2 bytes. We may use one
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more higher byte to specify a prefix the instruction
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requires. */
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if ((i.tm.base_opcode & 0xff0000) != 0)
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/* All opcodes on i386 have either 1 or 2 bytes. Merom New
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Instructions have 3 bytes. We may use one more higher byte
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to specify a prefix the instruction requires. */
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if ((i.tm.cpu_flags & CpuMNI) != 0)
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{
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if (i.tm.base_opcode & 0xff000000)
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{
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prefix = (i.tm.base_opcode >> 24) & 0xff;
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goto check_prefix;
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}
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}
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else if ((i.tm.base_opcode & 0xff0000) != 0)
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{
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prefix = (i.tm.base_opcode >> 16) & 0xff;
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if ((i.tm.cpu_flags & CpuPadLock) != 0)
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{
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unsigned int prefix;
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prefix = (i.tm.base_opcode >> 16) & 0xff;
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check_prefix:
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if (prefix != REPE_PREFIX_OPCODE
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|| i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
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add_prefix (prefix);
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}
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else
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add_prefix ((i.tm.base_opcode >> 16) & 0xff);
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add_prefix (prefix);
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}
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/* The prefix bytes. */
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@ -3512,7 +3520,13 @@ output_insn ()
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}
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else
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{
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p = frag_more (2);
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if ((i.tm.cpu_flags & CpuMNI) != 0)
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{
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p = frag_more (3);
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*p++ = (i.tm.base_opcode >> 16) & 0xff;
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}
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else
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p = frag_more (2);
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/* Put out high byte first: can't use md_number_to_chars! */
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*p++ = (i.tm.base_opcode >> 8) & 0xff;
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@ -184,6 +184,7 @@ typedef struct
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#define CpuPadLock 0x40000 /* VIA PadLock required */
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#define CpuSVME 0x80000 /* AMD Secure Virtual Machine Ext-s required */
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#define CpuVMX 0x100000 /* VMX Instructions required */
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#define CpuMNI 0x200000 /* Merom New Instructions required */
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/* These flags are set by gas depending on the flag_code. */
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#define Cpu64 0x4000000 /* 64bit support required */
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@ -192,7 +193,7 @@ typedef struct
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/* The default value for unknown CPUs - enable all features to avoid problems. */
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#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
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|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI|CpuVMX \
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|Cpu3dnow|Cpu3dnowA|CpuK6|CpuAthlon|CpuPadLock|CpuSVME)
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|Cpu3dnow|Cpu3dnowA|CpuK6|CpuAthlon|CpuPadLock|CpuSVME|CpuMNI)
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/* the bits in opcode_modifier are used to generate the final opcode from
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the base_opcode. These bits also are used to detect alternate forms of
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@ -1,3 +1,12 @@
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2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/i386.exp: Add merom and x86-64-merom.
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* gas/i386/merom.d: New file.
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* gas/i386/merom.s: Likewise.
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* gas/i386/x86-64-merom.d: Likewise.
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* gas/i386/x86-64-merom.s: Likewise.
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2006-02-24 David S. Miller <davem@sunset.davemloft.net>
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* gas/sparc/rdhpr.s: New test.
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@ -68,6 +68,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "crx"
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run_list_test "cr-err" ""
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run_dump_test "svme"
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run_dump_test "merom"
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# These tests require support for 8 and 16 bit relocs,
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# so we only run them for ELF and COFF targets.
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@ -136,6 +137,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_dump_test "x86-64-crx-suffix"
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run_dump_test "x86-64-drx"
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run_dump_test "x86-64-drx-suffix"
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run_dump_test "x86-64-merom"
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if { ![istarget "*-*-aix*"]
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&& ![istarget "*-*-beos*"]
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@ -0,0 +1,73 @@
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#objdump: -dw
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#name: i386 merom
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.*: +file format .*
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Disassembly of section .text:
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0+000 <foo>:
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0: 0f 38 01 01[ ]+phaddw \(%ecx\),%mm0
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4: 0f 38 01 c1[ ]+phaddw %mm1,%mm0
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8: 66 0f 38 01 01[ ]+phaddw \(%ecx\),%xmm0
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d: 66 0f 38 01 c1[ ]+phaddw %xmm1,%xmm0
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12: 0f 38 02 01[ ]+phaddd \(%ecx\),%mm0
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16: 0f 38 02 c1[ ]+phaddd %mm1,%mm0
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1a: 66 0f 38 02 01[ ]+phaddd \(%ecx\),%xmm0
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1f: 66 0f 38 02 c1[ ]+phaddd %xmm1,%xmm0
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24: 0f 38 03 01[ ]+phaddsw \(%ecx\),%mm0
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28: 0f 38 03 c1[ ]+phaddsw %mm1,%mm0
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2c: 66 0f 38 03 01[ ]+phaddsw \(%ecx\),%xmm0
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31: 66 0f 38 03 c1[ ]+phaddsw %xmm1,%xmm0
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36: 0f 38 05 01[ ]+phsubw \(%ecx\),%mm0
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3a: 0f 38 05 c1[ ]+phsubw %mm1,%mm0
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3e: 66 0f 38 05 01[ ]+phsubw \(%ecx\),%xmm0
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43: 66 0f 38 05 c1[ ]+phsubw %xmm1,%xmm0
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48: 0f 38 06 01[ ]+phsubd \(%ecx\),%mm0
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4c: 0f 38 06 c1[ ]+phsubd %mm1,%mm0
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50: 66 0f 38 06 01[ ]+phsubd \(%ecx\),%xmm0
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55: 66 0f 38 06 c1[ ]+phsubd %xmm1,%xmm0
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5a: 0f 38 07 01[ ]+phsubsw \(%ecx\),%mm0
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5e: 0f 38 07 c1[ ]+phsubsw %mm1,%mm0
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62: 66 0f 38 07 01[ ]+phsubsw \(%ecx\),%xmm0
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67: 66 0f 38 07 c1[ ]+phsubsw %xmm1,%xmm0
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6c: 0f 38 04 01[ ]+pmaddubsw \(%ecx\),%mm0
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70: 0f 38 04 c1[ ]+pmaddubsw %mm1,%mm0
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74: 66 0f 38 04 01[ ]+pmaddubsw \(%ecx\),%xmm0
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79: 66 0f 38 04 c1[ ]+pmaddubsw %xmm1,%xmm0
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7e: 0f 38 0b 01[ ]+pmulhrsw \(%ecx\),%mm0
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82: 0f 38 0b c1[ ]+pmulhrsw %mm1,%mm0
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86: 66 0f 38 0b 01[ ]+pmulhrsw \(%ecx\),%xmm0
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8b: 66 0f 38 0b c1[ ]+pmulhrsw %xmm1,%xmm0
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90: 0f 38 00 01[ ]+pshufb \(%ecx\),%mm0
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94: 0f 38 00 c1[ ]+pshufb %mm1,%mm0
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98: 66 0f 38 00 01[ ]+pshufb \(%ecx\),%xmm0
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9d: 66 0f 38 00 c1[ ]+pshufb %xmm1,%xmm0
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a2: 0f 38 08 01[ ]+psignb \(%ecx\),%mm0
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a6: 0f 38 08 c1[ ]+psignb %mm1,%mm0
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aa: 66 0f 38 08 01[ ]+psignb \(%ecx\),%xmm0
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af: 66 0f 38 08 c1[ ]+psignb %xmm1,%xmm0
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b4: 0f 38 09 01[ ]+psignw \(%ecx\),%mm0
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b8: 0f 38 09 c1[ ]+psignw %mm1,%mm0
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bc: 66 0f 38 09 01[ ]+psignw \(%ecx\),%xmm0
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c1: 66 0f 38 09 c1[ ]+psignw %xmm1,%xmm0
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c6: 0f 38 0a 01[ ]+psignd \(%ecx\),%mm0
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ca: 0f 38 0a c1[ ]+psignd %mm1,%mm0
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ce: 66 0f 38 0a 01[ ]+psignd \(%ecx\),%xmm0
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d3: 66 0f 38 0a c1[ ]+psignd %xmm1,%xmm0
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d8: 0f 3a 0f 01 02[ ]+palignr \$0x2,\(%ecx\),%mm0
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dd: 0f 3a 0f c1 02[ ]+palignr \$0x2,%mm1,%mm0
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e2: 66 0f 3a 0f 01 02[ ]+palignr \$0x2,\(%ecx\),%xmm0
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e8: 66 0f 3a 0f c1 02[ ]+palignr \$0x2,%xmm1,%xmm0
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ee: 0f 38 1c 01[ ]+pabsb \(%ecx\),%mm0
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f2: 0f 38 1c c1[ ]+pabsb %mm1,%mm0
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f6: 66 0f 38 1c 01[ ]+pabsb \(%ecx\),%xmm0
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fb: 66 0f 38 1c c1[ ]+pabsb %xmm1,%xmm0
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100: 0f 38 1d 01[ ]+pabsw \(%ecx\),%mm0
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104: 0f 38 1d c1[ ]+pabsw %mm1,%mm0
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108: 66 0f 38 1d 01[ ]+pabsw \(%ecx\),%xmm0
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10d: 66 0f 38 1d c1[ ]+pabsw %xmm1,%xmm0
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112: 0f 38 1e 01[ ]+pabsd \(%ecx\),%mm0
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116: 0f 38 1e c1[ ]+pabsd %mm1,%mm0
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11a: 66 0f 38 1e 01[ ]+pabsd \(%ecx\),%xmm0
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11f: 66 0f 38 1e c1[ ]+pabsd %xmm1,%xmm0
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...
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@ -0,0 +1,70 @@
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#Merom New Instructions
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.text
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foo:
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phaddw (%ecx),%mm0
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phaddw %mm1,%mm0
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phaddw (%ecx),%xmm0
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phaddw %xmm1,%xmm0
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phaddd (%ecx),%mm0
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phaddd %mm1,%mm0
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phaddd (%ecx),%xmm0
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phaddd %xmm1,%xmm0
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phaddsw (%ecx),%mm0
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phaddsw %mm1,%mm0
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phaddsw (%ecx),%xmm0
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phaddsw %xmm1,%xmm0
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phsubw (%ecx),%mm0
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phsubw %mm1,%mm0
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phsubw (%ecx),%xmm0
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phsubw %xmm1,%xmm0
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phsubd (%ecx),%mm0
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phsubd %mm1,%mm0
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phsubd (%ecx),%xmm0
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phsubd %xmm1,%xmm0
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phsubsw (%ecx),%mm0
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phsubsw %mm1,%mm0
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phsubsw (%ecx),%xmm0
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phsubsw %xmm1,%xmm0
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pmaddubsw (%ecx),%mm0
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pmaddubsw %mm1,%mm0
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pmaddubsw (%ecx),%xmm0
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pmaddubsw %xmm1,%xmm0
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pmulhrsw (%ecx),%mm0
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pmulhrsw %mm1,%mm0
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pmulhrsw (%ecx),%xmm0
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pmulhrsw %xmm1,%xmm0
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pshufb (%ecx),%mm0
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pshufb %mm1,%mm0
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pshufb (%ecx),%xmm0
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pshufb %xmm1,%xmm0
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psignb (%ecx),%mm0
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psignb %mm1,%mm0
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psignb (%ecx),%xmm0
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psignb %xmm1,%xmm0
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psignw (%ecx),%mm0
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psignw %mm1,%mm0
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psignw (%ecx),%xmm0
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psignw %xmm1,%xmm0
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psignd (%ecx),%mm0
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psignd %mm1,%mm0
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psignd (%ecx),%xmm0
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psignd %xmm1,%xmm0
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palignr $0x2,(%ecx),%mm0
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palignr $0x2,%mm1,%mm0
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palignr $0x2,(%ecx),%xmm0
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palignr $0x2,%xmm1,%xmm0
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pabsb (%ecx),%mm0
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pabsb %mm1,%mm0
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pabsb (%ecx),%xmm0
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pabsb %xmm1,%xmm0
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pabsw (%ecx),%mm0
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pabsw %mm1,%mm0
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pabsw (%ecx),%xmm0
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pabsw %xmm1,%xmm0
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pabsd (%ecx),%mm0
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pabsd %mm1,%mm0
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pabsd (%ecx),%xmm0
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pabsd %xmm1,%xmm0
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.p2align 4,0
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@ -0,0 +1,73 @@
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#objdump: -dw
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#name: x86-64 merom
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.*: +file format .*
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Disassembly of section .text:
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0+000 <foo>:
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0: 0f 38 01 01[ ]+phaddw \(%rcx\),%mm0
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4: 0f 38 01 c1[ ]+phaddw %mm1,%mm0
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8: 66 0f 38 01 01[ ]+phaddw \(%rcx\),%xmm0
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d: 66 0f 38 01 c1[ ]+phaddw %xmm1,%xmm0
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12: 0f 38 02 01[ ]+phaddd \(%rcx\),%mm0
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16: 0f 38 02 c1[ ]+phaddd %mm1,%mm0
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1a: 66 0f 38 02 01[ ]+phaddd \(%rcx\),%xmm0
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1f: 66 0f 38 02 c1[ ]+phaddd %xmm1,%xmm0
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24: 0f 38 03 01[ ]+phaddsw \(%rcx\),%mm0
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28: 0f 38 03 c1[ ]+phaddsw %mm1,%mm0
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2c: 66 0f 38 03 01[ ]+phaddsw \(%rcx\),%xmm0
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31: 66 0f 38 03 c1[ ]+phaddsw %xmm1,%xmm0
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36: 0f 38 05 01[ ]+phsubw \(%rcx\),%mm0
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3a: 0f 38 05 c1[ ]+phsubw %mm1,%mm0
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3e: 66 0f 38 05 01[ ]+phsubw \(%rcx\),%xmm0
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43: 66 0f 38 05 c1[ ]+phsubw %xmm1,%xmm0
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48: 0f 38 06 01[ ]+phsubd \(%rcx\),%mm0
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4c: 0f 38 06 c1[ ]+phsubd %mm1,%mm0
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50: 66 0f 38 06 01[ ]+phsubd \(%rcx\),%xmm0
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55: 66 0f 38 06 c1[ ]+phsubd %xmm1,%xmm0
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5a: 0f 38 07 01[ ]+phsubsw \(%rcx\),%mm0
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5e: 0f 38 07 c1[ ]+phsubsw %mm1,%mm0
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62: 66 0f 38 07 01[ ]+phsubsw \(%rcx\),%xmm0
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67: 66 0f 38 07 c1[ ]+phsubsw %xmm1,%xmm0
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6c: 0f 38 04 01[ ]+pmaddubsw \(%rcx\),%mm0
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70: 0f 38 04 c1[ ]+pmaddubsw %mm1,%mm0
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74: 66 0f 38 04 01[ ]+pmaddubsw \(%rcx\),%xmm0
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79: 66 0f 38 04 c1[ ]+pmaddubsw %xmm1,%xmm0
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7e: 0f 38 0b 01[ ]+pmulhrsw \(%rcx\),%mm0
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82: 0f 38 0b c1[ ]+pmulhrsw %mm1,%mm0
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86: 66 0f 38 0b 01[ ]+pmulhrsw \(%rcx\),%xmm0
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8b: 66 0f 38 0b c1[ ]+pmulhrsw %xmm1,%xmm0
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90: 0f 38 00 01[ ]+pshufb \(%rcx\),%mm0
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94: 0f 38 00 c1[ ]+pshufb %mm1,%mm0
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98: 66 0f 38 00 01[ ]+pshufb \(%rcx\),%xmm0
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9d: 66 0f 38 00 c1[ ]+pshufb %xmm1,%xmm0
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a2: 0f 38 08 01[ ]+psignb \(%rcx\),%mm0
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a6: 0f 38 08 c1[ ]+psignb %mm1,%mm0
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aa: 66 0f 38 08 01[ ]+psignb \(%rcx\),%xmm0
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af: 66 0f 38 08 c1[ ]+psignb %xmm1,%xmm0
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b4: 0f 38 09 01[ ]+psignw \(%rcx\),%mm0
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b8: 0f 38 09 c1[ ]+psignw %mm1,%mm0
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bc: 66 0f 38 09 01[ ]+psignw \(%rcx\),%xmm0
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c1: 66 0f 38 09 c1[ ]+psignw %xmm1,%xmm0
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c6: 0f 38 0a 01[ ]+psignd \(%rcx\),%mm0
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ca: 0f 38 0a c1[ ]+psignd %mm1,%mm0
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ce: 66 0f 38 0a 01[ ]+psignd \(%rcx\),%xmm0
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d3: 66 0f 38 0a c1[ ]+psignd %xmm1,%xmm0
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d8: 0f 3a 0f 01 02[ ]+palignr \$0x2,\(%rcx\),%mm0
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dd: 0f 3a 0f c1 02[ ]+palignr \$0x2,%mm1,%mm0
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e2: 66 0f 3a 0f 01 02[ ]+palignr \$0x2,\(%rcx\),%xmm0
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e8: 66 0f 3a 0f c1 02[ ]+palignr \$0x2,%xmm1,%xmm0
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ee: 0f 38 1c 01[ ]+pabsb \(%rcx\),%mm0
|
||||
f2: 0f 38 1c c1[ ]+pabsb %mm1,%mm0
|
||||
f6: 66 0f 38 1c 01[ ]+pabsb \(%rcx\),%xmm0
|
||||
fb: 66 0f 38 1c c1[ ]+pabsb %xmm1,%xmm0
|
||||
100: 0f 38 1d 01[ ]+pabsw \(%rcx\),%mm0
|
||||
104: 0f 38 1d c1[ ]+pabsw %mm1,%mm0
|
||||
108: 66 0f 38 1d 01[ ]+pabsw \(%rcx\),%xmm0
|
||||
10d: 66 0f 38 1d c1[ ]+pabsw %xmm1,%xmm0
|
||||
112: 0f 38 1e 01[ ]+pabsd \(%rcx\),%mm0
|
||||
116: 0f 38 1e c1[ ]+pabsd %mm1,%mm0
|
||||
11a: 66 0f 38 1e 01[ ]+pabsd \(%rcx\),%xmm0
|
||||
11f: 66 0f 38 1e c1[ ]+pabsd %xmm1,%xmm0
|
||||
...
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
#Merom New Instructions
|
||||
|
||||
.text
|
||||
foo:
|
||||
phaddw (%rcx),%mm0
|
||||
phaddw %mm1,%mm0
|
||||
phaddw (%rcx),%xmm0
|
||||
phaddw %xmm1,%xmm0
|
||||
phaddd (%rcx),%mm0
|
||||
phaddd %mm1,%mm0
|
||||
phaddd (%rcx),%xmm0
|
||||
phaddd %xmm1,%xmm0
|
||||
phaddsw (%rcx),%mm0
|
||||
phaddsw %mm1,%mm0
|
||||
phaddsw (%rcx),%xmm0
|
||||
phaddsw %xmm1,%xmm0
|
||||
phsubw (%rcx),%mm0
|
||||
phsubw %mm1,%mm0
|
||||
phsubw (%rcx),%xmm0
|
||||
phsubw %xmm1,%xmm0
|
||||
phsubd (%rcx),%mm0
|
||||
phsubd %mm1,%mm0
|
||||
phsubd (%rcx),%xmm0
|
||||
phsubd %xmm1,%xmm0
|
||||
phsubsw (%rcx),%mm0
|
||||
phsubsw %mm1,%mm0
|
||||
phsubsw (%rcx),%xmm0
|
||||
phsubsw %xmm1,%xmm0
|
||||
pmaddubsw (%rcx),%mm0
|
||||
pmaddubsw %mm1,%mm0
|
||||
pmaddubsw (%rcx),%xmm0
|
||||
pmaddubsw %xmm1,%xmm0
|
||||
pmulhrsw (%rcx),%mm0
|
||||
pmulhrsw %mm1,%mm0
|
||||
pmulhrsw (%rcx),%xmm0
|
||||
pmulhrsw %xmm1,%xmm0
|
||||
pshufb (%rcx),%mm0
|
||||
pshufb %mm1,%mm0
|
||||
pshufb (%rcx),%xmm0
|
||||
pshufb %xmm1,%xmm0
|
||||
psignb (%rcx),%mm0
|
||||
psignb %mm1,%mm0
|
||||
psignb (%rcx),%xmm0
|
||||
psignb %xmm1,%xmm0
|
||||
psignw (%rcx),%mm0
|
||||
psignw %mm1,%mm0
|
||||
psignw (%rcx),%xmm0
|
||||
psignw %xmm1,%xmm0
|
||||
psignd (%rcx),%mm0
|
||||
psignd %mm1,%mm0
|
||||
psignd (%rcx),%xmm0
|
||||
psignd %xmm1,%xmm0
|
||||
palignr $0x2,(%rcx),%mm0
|
||||
palignr $0x2,%mm1,%mm0
|
||||
palignr $0x2,(%rcx),%xmm0
|
||||
palignr $0x2,%xmm1,%xmm0
|
||||
pabsb (%rcx),%mm0
|
||||
pabsb %mm1,%mm0
|
||||
pabsb (%rcx),%xmm0
|
||||
pabsb %xmm1,%xmm0
|
||||
pabsw (%rcx),%mm0
|
||||
pabsw %mm1,%mm0
|
||||
pabsw (%rcx),%xmm0
|
||||
pabsw %xmm1,%xmm0
|
||||
pabsd (%rcx),%mm0
|
||||
pabsd %mm1,%mm0
|
||||
pabsd (%rcx),%xmm0
|
||||
pabsd %xmm1,%xmm0
|
||||
|
||||
.p2align 4,0
|
||||
|
|
@ -1,3 +1,7 @@
|
|||
2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* i386.h (i386_optab): Support Intel Merom New Instructions.
|
||||
|
||||
2006-02-24 Paul Brook <paul@codesourcery.com>
|
||||
|
||||
* arm.h: Add V7 feature bits.
|
||||
|
|
|
|||
|
|
@ -1379,6 +1379,41 @@ static const template i386_optab[] =
|
|||
{"vmxoff", 0, 0x0f01, 0xc4, CpuVMX, NoSuf|ImmExt, { 0, 0, 0} },
|
||||
{"vmxon", 1, 0xf30fc7, 6, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64, { LLongMem, 0, 0} },
|
||||
|
||||
/* Merom New Instructions. */
|
||||
|
||||
{"phaddw", 2, 0x0f3801,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"phaddw", 2, 0x660f3801,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
{"phaddd", 2, 0x0f3802,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"phaddd", 2, 0x660f3802,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
{"phaddsw", 2, 0x0f3803,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"phaddsw", 2, 0x660f3803,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
{"phsubw", 2, 0x0f3805,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"phsubw", 2, 0x660f3805,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
{"phsubd", 2, 0x0f3806,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"phsubd", 2, 0x660f3806,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
{"phsubsw", 2, 0x0f3807,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"phsubsw", 2, 0x660f3807,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
{"pmaddubsw", 2, 0x0f3804,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pmaddubsw", 2, 0x660f3804,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
{"pmulhrsw", 2, 0x0f380b,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pmulhrsw", 2, 0x660f380b,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
{"pshufb", 2, 0x0f3800,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pshufb", 2, 0x660f3800,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
{"psignb", 2, 0x0f3808,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"psignb", 2, 0x660f3808,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
{"psignw", 2, 0x0f3809,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"psignw", 2, 0x660f3809,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
{"psignd", 2, 0x0f380a,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"psignd", 2, 0x660f380a,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
{"palignr", 3, 0x0f3a0f,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX|LongMem, RegMMX } },
|
||||
{"palignr", 3, 0x660f3a0f,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
|
||||
{"pabsb", 2, 0x0f381c,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pabsb", 2, 0x660f381c,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
{"pabsw", 2, 0x0f381d,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pabsw", 2, 0x660f381d,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
{"pabsd", 2, 0x0f381e,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
|
||||
{"pabsd", 2, 0x660f381e,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
|
||||
|
||||
/* AMD 3DNow! instructions. */
|
||||
|
||||
{"prefetch", 1, 0x0f0d, 0, Cpu3dnow, NoSuf|IgnoreSize|Modrm, { ByteMem, 0, 0 } },
|
||||
|
|
|
|||
|
|
@ -1,3 +1,17 @@
|
|||
2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
|
||||
Intel Merom New Instructions.
|
||||
(THREE_BYTE_0): Likewise.
|
||||
(THREE_BYTE_1): Likewise.
|
||||
(three_byte_table): Likewise.
|
||||
(dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
|
||||
THREE_BYTE_1 for entry 0x3a.
|
||||
(twobyte_has_modrm): Updated.
|
||||
(twobyte_uses_SSE_prefix): Likewise.
|
||||
(print_insn): Handle 3-byte opcodes used by Intel Merom New
|
||||
Instructions.
|
||||
|
||||
2006-02-24 David S. Miller <davem@sunset.davemloft.net>
|
||||
|
||||
* sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
|
||||
|
|
|
|||
|
|
@ -388,6 +388,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
|
|||
#define USE_GROUPS 2
|
||||
#define USE_PREFIX_USER_TABLE 3
|
||||
#define X86_64_SPECIAL 4
|
||||
#define IS_3BYTE_OPCODE 5
|
||||
|
||||
#define FLOAT NULL, NULL, FLOATCODE, NULL, 0, NULL, 0
|
||||
|
||||
|
|
@ -453,6 +454,9 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
|
|||
|
||||
#define X86_64_0 NULL, NULL, X86_64_SPECIAL, NULL, 0, NULL, 0
|
||||
|
||||
#define THREE_BYTE_0 NULL, NULL, IS_3BYTE_OPCODE, NULL, 0, NULL, 0
|
||||
#define THREE_BYTE_1 NULL, NULL, IS_3BYTE_OPCODE, NULL, 1, NULL, 0
|
||||
|
||||
typedef void (*op_rtn) (int bytemode, int sizeflag);
|
||||
|
||||
struct dis386 {
|
||||
|
|
@ -858,9 +862,9 @@ static const struct dis386 dis386_twobyte[] = {
|
|||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
/* 38 */
|
||||
{ THREE_BYTE_0 },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ THREE_BYTE_1 },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
|
|
@ -1113,7 +1117,7 @@ static const unsigned char twobyte_has_modrm[256] = {
|
|||
/* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
|
||||
/* 10 */ 1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0, /* 1f */
|
||||
/* 20 */ 1,1,1,1,1,0,1,0,1,1,1,1,1,1,1,1, /* 2f */
|
||||
/* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */
|
||||
/* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
|
||||
/* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
|
||||
/* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
|
||||
/* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
|
||||
|
|
@ -1136,7 +1140,7 @@ static const unsigned char twobyte_uses_SSE_prefix[256] = {
|
|||
/* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
|
||||
/* 10 */ 1,1,1,0,0,0,1,0,0,0,0,0,0,0,0,0, /* 1f */
|
||||
/* 20 */ 0,0,0,0,0,0,0,0,0,0,1,0,1,1,0,0, /* 2f */
|
||||
/* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */
|
||||
/* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
|
||||
/* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
|
||||
/* 50 */ 0,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* 5f */
|
||||
/* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,1, /* 6f */
|
||||
|
|
@ -1749,6 +1753,79 @@ static const struct dis386 x86_64_table[][2] = {
|
|||
},
|
||||
};
|
||||
|
||||
static const struct dis386 three_byte_table[][32] = {
|
||||
/* THREE_BYTE_0 */
|
||||
{
|
||||
{ "pshufb", MX, EM, XX },
|
||||
{ "phaddw", MX, EM, XX },
|
||||
{ "phaddd", MX, EM, XX },
|
||||
{ "phaddsw", MX, EM, XX },
|
||||
{ "pmaddubsw", MX, EM, XX },
|
||||
{ "phsubw", MX, EM, XX },
|
||||
{ "phsubd", MX, EM, XX },
|
||||
{ "phsubsw", MX, EM, XX },
|
||||
{ "psignb", MX, EM, XX },
|
||||
{ "psignw", MX, EM, XX },
|
||||
{ "psignd", MX, EM, XX },
|
||||
{ "pmulhrsw", MX, EM, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "pabsb", MX, EM, XX },
|
||||
{ "pabsw", MX, EM, XX },
|
||||
{ "pabsd", MX, EM, XX },
|
||||
{ "(bad)", XX, XX, XX }
|
||||
},
|
||||
/* THREE_BYTE_1 */
|
||||
{
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "palignr", MX, EM, Ib },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX },
|
||||
{ "(bad)", XX, XX, XX }
|
||||
},
|
||||
};
|
||||
|
||||
#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
|
||||
|
||||
static void
|
||||
|
|
@ -2206,7 +2283,15 @@ print_insn (bfd_vma pc, disassemble_info *info)
|
|||
}
|
||||
}
|
||||
|
||||
if (need_modrm)
|
||||
if (dp->name == NULL && dp->bytemode1 == IS_3BYTE_OPCODE)
|
||||
{
|
||||
FETCH_DATA (info, codep + 2);
|
||||
dp = &three_byte_table[dp->bytemode2][*codep++];
|
||||
mod = (*codep >> 6) & 3;
|
||||
reg = (*codep >> 3) & 7;
|
||||
rm = *codep & 7;
|
||||
}
|
||||
else if (need_modrm)
|
||||
{
|
||||
FETCH_DATA (info, codep + 1);
|
||||
mod = (*codep >> 6) & 3;
|
||||
|
|
|
|||
Loading…
Reference in New Issue