RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2
This matches the ISA specification. This also adds two tests: one to make sure the assembler rejects invalid 'c.lui's, and one to make sure we only relax valid 'c.lui's. bfd/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * elfnn-riscv.c (_bfd_riscv_relax_lui): Don't relax to c.lui when rd is x0. include/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * opcode/riscv.h (VALID_RVC_LUI_IMM): c.lui can't load the immediate 0. gas/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * testsuite/gas/riscv/c-lui-fail.d: New testcase. gas/testsuite/gas/riscv/c-lui-fail.l: Likewise. gas/testsuite/gas/riscv/c-lui-fail.s: Likewise. gas/testsuite/gas/riscv/riscv.exp: Likewise. ld/ChangeLog 2017-10-24 Andrew Waterman <andrew@sifive.com> * ld/testsuite/ld-riscv-elf/c-lui.d: New testcase. ld/testsuite/ld-riscv-elf/c-lui.s: Likewise. ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: New test suite.
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@ -1,3 +1,8 @@
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2017-10-24 Andrew Waterman <andrew@sifive.com>
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* elfnn-riscv.c (_bfd_riscv_relax_lui): Don't relax to c.lui
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when rd is x0.
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2017-10-24 Renlin Li <renlin.li@arm.com>
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PR ld/21703
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@ -2988,9 +2988,10 @@ _bfd_riscv_relax_lui (bfd *abfd,
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&& VALID_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (symval))
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&& VALID_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (symval + ELF_MAXPAGESIZE)))
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{
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/* Replace LUI with C.LUI if legal (i.e., rd != x2/sp). */
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/* Replace LUI with C.LUI if legal (i.e., rd != x0 and rd != x2/sp). */
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bfd_vma lui = bfd_get_32 (abfd, contents + rel->r_offset);
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if (((lui >> OP_SH_RD) & OP_MASK_RD) == X_SP)
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unsigned rd = ((unsigned)lui >> OP_SH_RD) & OP_MASK_RD;
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if (rd == 0 || rd == X_SP)
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return TRUE;
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lui = (lui & (OP_MASK_RD << OP_SH_RD)) | MATCH_C_LUI;
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@ -1,3 +1,10 @@
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2017-10-24 Andrew Waterman <andrew@sifive.com>
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* testsuite/gas/riscv/c-lui-fail.d: New testcase.
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gas/testsuite/gas/riscv/c-lui-fail.l: Likewise.
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gas/testsuite/gas/riscv/c-lui-fail.s: Likewise.
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gas/testsuite/gas/riscv/riscv.exp: Likewise.
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2017-10-24 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (md_pseudo_table): Add .code64 directive
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@ -0,0 +1,3 @@
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#as: -march=rv32ic
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#source: c-lui-fail.s
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#error-output: c-lui-fail.l
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@ -0,0 +1,2 @@
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.*: Assembler messages:
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.*: Error: illegal operands `c.lui x1,0'
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@ -0,0 +1,2 @@
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target:
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c.lui x1, 0
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@ -21,4 +21,5 @@
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if [istarget riscv*-*-*] {
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run_dump_test "t_insns"
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run_dump_test "fmv.x"
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run_dump_test "c-lui-fail"
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}
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@ -1,3 +1,8 @@
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2017-10-24 Andrew Waterman <andrew@sifive.com>
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* opcode/riscv.h (VALID_RVC_LUI_IMM): c.lui can't load the
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immediate 0.
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2017-10-12 James Bowman <james.bowman@ftdichip.com>
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* elf/ft32.h: Add R_FT32_15.
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@ -141,7 +141,7 @@ static const char * const riscv_pred_succ[16] =
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#define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))
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#define VALID_UJTYPE_IMM(x) (EXTRACT_UJTYPE_IMM(ENCODE_UJTYPE_IMM(x)) == (x))
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#define VALID_RVC_IMM(x) (EXTRACT_RVC_IMM(ENCODE_RVC_IMM(x)) == (x))
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#define VALID_RVC_LUI_IMM(x) (EXTRACT_RVC_LUI_IMM(ENCODE_RVC_LUI_IMM(x)) == (x))
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#define VALID_RVC_LUI_IMM(x) (ENCODE_RVC_LUI_IMM(x) != 0 && EXTRACT_RVC_LUI_IMM(ENCODE_RVC_LUI_IMM(x)) == (x))
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#define VALID_RVC_SIMM3(x) (EXTRACT_RVC_SIMM3(ENCODE_RVC_SIMM3(x)) == (x))
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#define VALID_RVC_ADDI4SPN_IMM(x) (EXTRACT_RVC_ADDI4SPN_IMM(ENCODE_RVC_ADDI4SPN_IMM(x)) == (x))
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#define VALID_RVC_ADDI16SP_IMM(x) (EXTRACT_RVC_ADDI16SP_IMM(ENCODE_RVC_ADDI16SP_IMM(x)) == (x))
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@ -1,3 +1,9 @@
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2017-10-24 Andrew Waterman <andrew@sifive.com>
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* ld/testsuite/ld-riscv-elf/c-lui.d: New testcase.
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ld/testsuite/ld-riscv-elf/c-lui.s: Likewise.
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ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: New test suite.
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2017-10-24 Renlin Li <renlin.li@arm.com>
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PR ld/21703
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#name: lui to c.lui relaxation
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#source: c-lui.s
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#as: -march=rv32ic
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#ld: -shared -melf32lriscv
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#objdump: -d -M no-aliases,numeric
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.*: file format .*
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Disassembly of section \.text:
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.* <.text>:
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.*: 6085 c.lui x1,0x1
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.*: 000000b7 lui x1,0x0
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.*: 00001037 lui x0,0x1
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.*: 00001137 lui x2,0x1
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#pass
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.text
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lui x1, 1
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lui x1, 0
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lui x0, 1
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lui x2, 1
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@ -0,0 +1,24 @@
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# Expect script for RISC-V ELF linker tests
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# Copyright (C) 2017 Free Software Foundation, Inc.
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#
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# This file is part of the GNU Binutils.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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# MA 02110-1301, USA.
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#
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if [is_target "riscv-*-*"] {
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run_dump_test "c-lui"
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}
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