RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2

This matches the ISA specification.  This also adds two tests: one to
make sure the assembler rejects invalid 'c.lui's, and one to make sure
we only relax valid 'c.lui's.

bfd/ChangeLog

2017-10-24  Andrew Waterman  <andrew@sifive.com>

        * elfnn-riscv.c (_bfd_riscv_relax_lui): Don't relax to c.lui
        when rd is x0.

include/ChangeLog

2017-10-24  Andrew Waterman  <andrew@sifive.com>

        * opcode/riscv.h (VALID_RVC_LUI_IMM): c.lui can't load the
        immediate 0.

gas/ChangeLog

2017-10-24  Andrew Waterman  <andrew@sifive.com>

        * testsuite/gas/riscv/c-lui-fail.d: New testcase.
        gas/testsuite/gas/riscv/c-lui-fail.l: Likewise.
        gas/testsuite/gas/riscv/c-lui-fail.s: Likewise.
        gas/testsuite/gas/riscv/riscv.exp: Likewise.

ld/ChangeLog

2017-10-24  Andrew Waterman  <andrew@sifive.com>

        * ld/testsuite/ld-riscv-elf/c-lui.d: New testcase.
        ld/testsuite/ld-riscv-elf/c-lui.s: Likewise.
        ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: New test suite.
This commit is contained in:
Andrew Waterman 2017-09-23 18:04:16 -07:00 committed by Palmer Dabbelt
parent 3779bbe01b
commit 3342be5dab
13 changed files with 81 additions and 3 deletions

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@ -1,3 +1,8 @@
2017-10-24 Andrew Waterman <andrew@sifive.com>
* elfnn-riscv.c (_bfd_riscv_relax_lui): Don't relax to c.lui
when rd is x0.
2017-10-24 Renlin Li <renlin.li@arm.com>
PR ld/21703

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@ -2988,9 +2988,10 @@ _bfd_riscv_relax_lui (bfd *abfd,
&& VALID_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (symval))
&& VALID_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (symval + ELF_MAXPAGESIZE)))
{
/* Replace LUI with C.LUI if legal (i.e., rd != x2/sp). */
/* Replace LUI with C.LUI if legal (i.e., rd != x0 and rd != x2/sp). */
bfd_vma lui = bfd_get_32 (abfd, contents + rel->r_offset);
if (((lui >> OP_SH_RD) & OP_MASK_RD) == X_SP)
unsigned rd = ((unsigned)lui >> OP_SH_RD) & OP_MASK_RD;
if (rd == 0 || rd == X_SP)
return TRUE;
lui = (lui & (OP_MASK_RD << OP_SH_RD)) | MATCH_C_LUI;

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@ -1,3 +1,10 @@
2017-10-24 Andrew Waterman <andrew@sifive.com>
* testsuite/gas/riscv/c-lui-fail.d: New testcase.
gas/testsuite/gas/riscv/c-lui-fail.l: Likewise.
gas/testsuite/gas/riscv/c-lui-fail.s: Likewise.
gas/testsuite/gas/riscv/riscv.exp: Likewise.
2017-10-24 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (md_pseudo_table): Add .code64 directive

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@ -0,0 +1,3 @@
#as: -march=rv32ic
#source: c-lui-fail.s
#error-output: c-lui-fail.l

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@ -0,0 +1,2 @@
.*: Assembler messages:
.*: Error: illegal operands `c.lui x1,0'

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@ -0,0 +1,2 @@
target:
c.lui x1, 0

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@ -21,4 +21,5 @@
if [istarget riscv*-*-*] {
run_dump_test "t_insns"
run_dump_test "fmv.x"
run_dump_test "c-lui-fail"
}

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@ -1,3 +1,8 @@
2017-10-24 Andrew Waterman <andrew@sifive.com>
* opcode/riscv.h (VALID_RVC_LUI_IMM): c.lui can't load the
immediate 0.
2017-10-12 James Bowman <james.bowman@ftdichip.com>
* elf/ft32.h: Add R_FT32_15.

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@ -141,7 +141,7 @@ static const char * const riscv_pred_succ[16] =
#define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))
#define VALID_UJTYPE_IMM(x) (EXTRACT_UJTYPE_IMM(ENCODE_UJTYPE_IMM(x)) == (x))
#define VALID_RVC_IMM(x) (EXTRACT_RVC_IMM(ENCODE_RVC_IMM(x)) == (x))
#define VALID_RVC_LUI_IMM(x) (EXTRACT_RVC_LUI_IMM(ENCODE_RVC_LUI_IMM(x)) == (x))
#define VALID_RVC_LUI_IMM(x) (ENCODE_RVC_LUI_IMM(x) != 0 && EXTRACT_RVC_LUI_IMM(ENCODE_RVC_LUI_IMM(x)) == (x))
#define VALID_RVC_SIMM3(x) (EXTRACT_RVC_SIMM3(ENCODE_RVC_SIMM3(x)) == (x))
#define VALID_RVC_ADDI4SPN_IMM(x) (EXTRACT_RVC_ADDI4SPN_IMM(ENCODE_RVC_ADDI4SPN_IMM(x)) == (x))
#define VALID_RVC_ADDI16SP_IMM(x) (EXTRACT_RVC_ADDI16SP_IMM(ENCODE_RVC_ADDI16SP_IMM(x)) == (x))

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@ -1,3 +1,9 @@
2017-10-24 Andrew Waterman <andrew@sifive.com>
* ld/testsuite/ld-riscv-elf/c-lui.d: New testcase.
ld/testsuite/ld-riscv-elf/c-lui.s: Likewise.
ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: New test suite.
2017-10-24 Renlin Li <renlin.li@arm.com>
PR ld/21703

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@ -0,0 +1,17 @@
#name: lui to c.lui relaxation
#source: c-lui.s
#as: -march=rv32ic
#ld: -shared -melf32lriscv
#objdump: -d -M no-aliases,numeric
.*: file format .*
Disassembly of section \.text:
.* <.text>:
.*: 6085 c.lui x1,0x1
.*: 000000b7 lui x1,0x0
.*: 00001037 lui x0,0x1
.*: 00001137 lui x2,0x1
#pass

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@ -0,0 +1,5 @@
.text
lui x1, 1
lui x1, 0
lui x0, 1
lui x2, 1

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@ -0,0 +1,24 @@
# Expect script for RISC-V ELF linker tests
# Copyright (C) 2017 Free Software Foundation, Inc.
#
# This file is part of the GNU Binutils.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
# MA 02110-1301, USA.
#
if [is_target "riscv-*-*"] {
run_dump_test "c-lui"
}