Make sure NOPS are inserted between 32-bit multiply and load or 16-bit multiply; Compile cleanly with -Wall; Add -n/-N options
This commit is contained in:
Michael Meissner
parent
7a880bf32d
commit
343b2ab8c1
@ -1,3 +1,41 @@
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start-sanitize-d30v
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Wed Dec 17 15:29:03 1997 Michael Meissner <meissner@cygnus.com>
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* config/tc-d30v.c (md_shortopts): Add 'n' and 'N' options.
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(exec_type_enum): Enumeration giving all of the exec types.
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(warn_nops): New static variable to give nop warning level.
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({cur,prev}_mul32_p): New static variable to keep track of whether
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the current/previous instruction is a 32-bit multiply.
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(Optimizing): Make static.
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(NOP{2,_LEFT,_RIGHT}): Macros for word of nops and left/right
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nops.
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(d30v_insert_operand): Delete declaration of unused function.
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(write_2_short): Make exec_type argument enum, not int.
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(parallel_ok): Ditto.
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(check_range): Delete unused variable(s).
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(build_insn): Ditto.
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(find_format): Ditto.
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(md_apply_fix3): Ditto.
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(md_show_usage): Document -n and -N.
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(md_parse_option): Parse -n and -N.
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(write_1_short): If -n, warn about adding a nop. Use
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NOP_{LEFT,RIGHT}.
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(write_2_short): Use enumeration values instead of hard coded
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integers. Reset exec_type for default operations. For explicit
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parallel operations, call parallel_ok to make sure everything is
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ok. If writing out a parallel operation, and the previous
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instruction was a 32-bit multiply, indicate current instruction
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is.
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(parallel_ok): Allow add/tx ... to be done in parallel with
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another add/tx ... assuming the gpr registers don't overlap.
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(md_assemble): Use exec type enumeration values, not hard coded
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ints. Check for loads or 16-bit multiplies following in the next
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cycle after a 32-bit multiply. Add nops if that is the case.
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(do_assemble): Copy prev_mul32_p to cur_mul32_p, and set
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cur_mul32_p if current instruction is a 32-bit multiply.
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(find_format): Change spacing and layout.
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end-sanitize-d30v
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start-sanitize-tic80
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Tue Dec 16 16:55:45 1997 Fred Fish <fnf@cygnus.com>
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@ -28,15 +28,27 @@
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const char comment_chars[] = ";";
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const char line_comment_chars[] = "#";
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const char line_separator_chars[] = "";
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const char *md_shortopts = "O";
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const char *md_shortopts = "OnN";
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const char EXP_CHARS[] = "eE";
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const char FLT_CHARS[] = "dD";
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int Optimizing = 0;
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#define NOP_MULTIPLY 1
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#define NOP_ALL 2
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static int warn_nops = 0;
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static int Optimizing = 0;
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#define FORCE_SHORT 1
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#define FORCE_LONG 2
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/* EXEC types. */
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typedef enum _exec_type
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{
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EXEC_UNKNOWN, /* no order specified */
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EXEC_PARALLEL, /* done in parallel */
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EXEC_SEQ, /* sequential */
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EXEC_REVSEQ /* reverse sequential */
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} exec_type_enum;
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/* fixups */
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#define MAX_INSN_FIXUPS (5)
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struct d30v_fixup
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@ -58,6 +70,15 @@ typedef struct _fixups
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static Fixups FixUps[2];
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static Fixups *fixups;
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/* Whether current and previous instruction is a word multiply. */
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int cur_mul32_p = 0;
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int prev_mul32_p = 0;
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/* Two nops */
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#define NOP_LEFT ((long long)NOP << 32)
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#define NOP_RIGHT ((long long)NOP)
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#define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT)
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/* local functions */
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static int reg_name_search PARAMS ((char *name));
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static int register_name PARAMS ((expressionS *expressionP));
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@ -71,13 +92,11 @@ static long long build_insn PARAMS ((struct d30v_insn *opcode, expressionS *oper
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static void write_long PARAMS ((struct d30v_insn *opcode, long long insn, Fixups *fx));
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static void write_1_short PARAMS ((struct d30v_insn *opcode, long long insn, Fixups *fx));
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static int write_2_short PARAMS ((struct d30v_insn *opcode1, long long insn1,
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struct d30v_insn *opcode2, long long insn2, int exec_type, Fixups *fx));
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struct d30v_insn *opcode2, long long insn2, exec_type_enum exec_type, Fixups *fx));
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static long long do_assemble PARAMS ((char *str, struct d30v_insn *opcode));
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static unsigned long d30v_insert_operand PARAMS (( unsigned long insn, int op_type,
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offsetT value, int left, fixS *fix));
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static int parallel_ok PARAMS ((struct d30v_insn *opcode1, unsigned long insn1,
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struct d30v_insn *opcode2, unsigned long insn2,
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int exec_type));
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exec_type_enum exec_type));
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static void d30v_number_to_chars PARAMS ((char *buf, long long value, int nbytes));
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static void check_size PARAMS ((long value, int bits, char *file, int line));
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@ -167,7 +186,7 @@ check_range (num, bits, flags)
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int bits;
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int flags;
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{
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long min, max, bit1;
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long min, max;
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int retval=0;
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/* don't bother checking 32-bit values */
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@ -196,8 +215,10 @@ void
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md_show_usage (stream)
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FILE *stream;
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{
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fprintf(stream, "D30V options:\n\
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-O optimize. Will do some operations in parallel.\n");
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fprintf(stream, "\nD30V options:\n\
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-O Make adjacent short instructions parallel if possible.\n\
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-n Warn about all NOPs inserted by the assembler.\n\
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-N Warn about NOPs inserted after word multiplies.\n");
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}
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int
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@ -207,10 +228,22 @@ md_parse_option (c, arg)
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{
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switch (c)
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{
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case 'O':
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/* Optimize. Will attempt to parallelize operations */
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case 'O':
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Optimizing = 1;
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break;
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/* Warn about all NOPS that the assembler inserts. */
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case 'n':
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warn_nops = NOP_ALL;
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break;
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/* Warn about the NOPS that the assembler inserts because of the
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multiply hazard. */
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case 'N':
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warn_nops = NOP_MULTIPLY;
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break;
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default:
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return 0;
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}
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@ -465,7 +498,7 @@ build_insn (opcode, opers)
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struct d30v_insn *opcode;
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expressionS *opers;
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{
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int i, length, bits, shift, flags, format;
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int i, length, bits, shift, flags;
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unsigned int number, id=0;
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long long insn;
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struct d30v_opcode *op = opcode->op;
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@ -593,13 +626,16 @@ write_1_short (opcode, insn, fx)
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char *f = frag_more(8);
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int i, where;
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if (warn_nops == NOP_ALL)
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as_warn ("NOP inserted");
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/* the other container needs to be NOP */
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/* according to 4.3.1: for FM=00, sub-instructions performed only
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by IU cannot be encoded in L-container. */
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if (opcode->op->unit == IU)
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insn |= FM00 | ((long long)NOP << 32); /* right container */
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insn |= FM00 | NOP_LEFT; /* right container */
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else
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insn = FM00 | (insn << 32) | (long long)NOP; /* left container */
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insn = FM00 | (insn << 32) | NOP_RIGHT; /* left container */
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d30v_number_to_chars (f, insn, 8);
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@ -625,14 +661,14 @@ static int
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write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
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struct d30v_insn *opcode1, *opcode2;
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long long insn1, insn2;
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int exec_type;
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exec_type_enum exec_type;
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Fixups *fx;
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{
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long long insn;
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long long insn = NOP2;
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char *f;
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int i,j, where;
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if(exec_type != 1 && (opcode1->op->flags_used == FLAG_JSR))
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if(exec_type != EXEC_PARALLEL && (opcode1->op->flags_used == FLAG_JSR))
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{
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/* subroutines must be called from 32-bit boundaries */
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/* so the return address will be correct */
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@ -642,10 +678,11 @@ write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
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switch (exec_type)
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{
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case 0: /* order not specified */
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if ( Optimizing && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
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case EXEC_UNKNOWN: /* order not specified */
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if (Optimizing && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
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{
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/* parallel */
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exec_type = EXEC_PARALLEL;
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if (opcode1->op->unit == IU)
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insn = FM00 | (insn2 << 32) | insn1;
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else if (opcode2->op->unit == MU)
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@ -656,20 +693,25 @@ write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
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fx = fx->next;
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}
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}
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else if (opcode1->op->unit == IU)
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else if (opcode1->op->unit == IU)
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{
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/* reverse sequential */
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insn = FM10 | (insn2 << 32) | insn1;
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exec_type = EXEC_REVSEQ;
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}
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else
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{
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/* sequential */
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insn = FM01 | (insn1 << 32) | insn2;
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fx = fx->next;
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fx = fx->next;
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exec_type = EXEC_SEQ;
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}
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break;
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case 1: /* parallel */
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if (opcode1->op->unit == IU)
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case EXEC_PARALLEL: /* parallel */
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if (! parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
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as_fatal ("Instructions may not be executed in parallel");
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else if (opcode1->op->unit == IU)
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{
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if (opcode2->op->unit == IU)
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as_fatal ("Two IU instructions may not be executed in parallel");
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@ -689,18 +731,21 @@ write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
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fx = fx->next;
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}
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break;
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case 2: /* sequential */
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case EXEC_SEQ: /* sequential */
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if (opcode1->op->unit == IU)
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as_fatal ("IU instruction may not be in the left container");
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insn = FM01 | (insn1 << 32) | insn2;
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fx = fx->next;
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break;
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case 3: /* reverse sequential */
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case EXEC_REVSEQ: /* reverse sequential */
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if (opcode2->op->unit == MU)
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as_fatal ("MU instruction may not be in the right container");
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insn = FM10 | (insn1 << 32) | insn2;
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fx = fx->next;
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break;
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default:
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as_fatal("unknown execution type passed to write_2_short()");
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}
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@ -709,6 +754,12 @@ write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
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f = frag_more(8);
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d30v_number_to_chars (f, insn, 8);
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/* If the previous instruction was a 32-bit multiply but it is put into a
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parallel container, mark the current instruction as being a 32-bit
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multiply. */
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if (prev_mul32_p && exec_type == EXEC_PARALLEL)
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cur_mul32_p = 1;
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for (j=0; j<2; j++)
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{
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for (i=0; i < fx->fc; i++)
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@ -738,22 +789,23 @@ static int
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parallel_ok (op1, insn1, op2, insn2, exec_type)
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struct d30v_insn *op1, *op2;
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unsigned long insn1, insn2;
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int exec_type;
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exec_type_enum exec_type;
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{
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int i, j, shift, regno, bits, ecc;
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unsigned long flags, mask, flags_set1, flags_set2, flags_used1, flags_used2;
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unsigned long ins, mod_reg[2][3], used_reg[2][3];
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unsigned long ins, mod_reg[2][3], used_reg[2][3], flag_reg[2];
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struct d30v_format *f;
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struct d30v_opcode *op;
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int reverse_p;
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/* section 4.3: both instructions must not be IU or MU only */
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if ((op1->op->unit == IU && op2->op->unit == IU)
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|| (op1->op->unit == MU && op2->op->unit == MU))
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return 0;
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/* first instruction must not be a jump to safely optimize */
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if (op1->op->flags_used & (FLAG_JMP | FLAG_JSR))
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/* first instruction must not be a jump to safely optimize, unless this
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is an explicit parallel operation. */
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if (exec_type != EXEC_PARALLEL
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&& (op1->op->flags_used & (FLAG_JMP | FLAG_JSR)))
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return 0;
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/* If one instruction is /TX or /XT and the other is /FX or /XF respectively,
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@ -785,6 +837,7 @@ parallel_ok (op1, insn1, op2, insn2, exec_type)
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ecc = op2->ecc;
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ins = insn2;
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}
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flag_reg[j] = 0;
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mod_reg[j][0] = mod_reg[j][1] = 0;
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mod_reg[j][2] = (op->flags_set & FLAG_ALL);
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used_reg[j][0] = used_reg[j][1] = 0;
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@ -799,17 +852,17 @@ parallel_ok (op1, insn1, op2, insn2, exec_type)
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{
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case ECC_TX:
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case ECC_FX:
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used_reg[j][2] |= FLAG_0;
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used_reg[j][2] |= flag_reg[j] = FLAG_0;
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break;
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case ECC_XT:
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case ECC_XF:
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used_reg[j][2] |= FLAG_1;
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used_reg[j][2] |= flag_reg[j] = FLAG_1;
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break;
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case ECC_TT:
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case ECC_TF:
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used_reg[j][2] |= (FLAG_0 | FLAG_1);
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used_reg[j][2] |= flag_reg[j] = (FLAG_0 | FLAG_1);
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break;
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}
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@ -935,7 +988,8 @@ parallel_ok (op1, insn1, op2, insn2, exec_type)
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subb. */
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if (mod_reg[0][2] == FLAG_CVVA && mod_reg[1][2] == FLAG_CVVA
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&& used_reg[0][2] == 0 && used_reg[1][2] == 0
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&& (used_reg[0][2] & ~flag_reg[0]) == 0
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&& (used_reg[1][2] & ~flag_reg[1]) == 0
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&& op1->op->unit == EITHER && op2->op->unit == EITHER)
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{
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mod_reg[0][2] = mod_reg[1][2] = 0;
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@ -958,8 +1012,7 @@ parallel_ok (op1, insn1, op2, insn2, exec_type)
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/* This is the main entry point for the machine-dependent assembler. str points to a
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machine-dependent instruction. This function is supposed to emit the frags/bytes
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it assembles to. For the D30V, it mostly handles the special VLIW parsing and packing
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and leaves the difficult stuff to do_assemble().
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*/
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and leaves the difficult stuff to do_assemble(). */
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static long long prev_insn = -1;
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static struct d30v_insn prev_opcode;
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@ -972,29 +1025,29 @@ md_assemble (str)
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{
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struct d30v_insn opcode;
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long long insn;
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int extype=0; /* execution type; parallel, etc */
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static int etype=0; /* saved extype. used for multiline instructions */
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exec_type_enum extype = EXEC_UNKNOWN; /* execution type; parallel, etc */
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static exec_type_enum etype = EXEC_UNKNOWN; /* saved extype. used for multiline instructions */
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char *str2;
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if ( (prev_insn != -1) && prev_seg && ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
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d30v_cleanup();
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if (etype == 0)
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if (etype == EXEC_UNKNOWN)
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{
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/* look for the special multiple instruction separators */
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str2 = strstr (str, "||");
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if (str2)
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extype = 1;
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extype = EXEC_PARALLEL;
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else
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{
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str2 = strstr (str, "->");
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if (str2)
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extype = 2;
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extype = EXEC_SEQ;
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else
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{
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str2 = strstr (str, "<-");
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if (str2)
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extype = 3;
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extype = EXEC_REVSEQ;
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}
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}
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/* str2 points to the separator, if one */
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@ -1034,6 +1087,43 @@ md_assemble (str)
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etype = 0;
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}
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/* Word multiply instructions must not be followed by either a load or a
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16-bit multiply instruction in the next cycle. */
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if (prev_mul32_p && (opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16)))
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{
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/* However, load and multiply should able to be combined in a parallel
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operation, so check for that first. */
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if (prev_insn != -1
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&& (opcode.op->flags_used & FLAG_MEM)
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&& opcode.form->form < LONG
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&& (extype == EXEC_PARALLEL || (Optimizing && extype == EXEC_UNKNOWN))
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&& parallel_ok (&prev_opcode, (long)prev_insn,
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&opcode, (long)insn, extype)
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&& write_2_short (&prev_opcode, (long)prev_insn,
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&opcode, (long)insn, extype, fixups) == 0)
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{
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/* no instructions saved */
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prev_insn = -1;
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return;
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}
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/* Can't parallelize, flush current instruction and emit a word of NOPS */
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else
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{
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char *f;
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d30v_cleanup();
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||||
|
||||
f = frag_more(8);
|
||||
d30v_number_to_chars (f, NOP2, 8);
|
||||
if (warn_nops == NOP_ALL || warn_nops == NOP_MULTIPLY)
|
||||
as_warn ("word of NOPs added between word multiply and %s",
|
||||
((opcode.op->flags_used & FLAG_MEM)
|
||||
? "load"
|
||||
: "16-bit multiply"));
|
||||
}
|
||||
}
|
||||
|
||||
/* if this is a long instruction, write it and any previous short instruction */
|
||||
if (opcode.form->form >= LONG)
|
||||
{
|
||||
@ -1044,19 +1134,20 @@ md_assemble (str)
|
||||
prev_insn = -1;
|
||||
return;
|
||||
}
|
||||
|
||||
if ( (prev_insn != -1) &&
|
||||
(write_2_short (&prev_opcode, (long)prev_insn, &opcode, (long)insn, extype, fixups) == 0))
|
||||
|
||||
if ((prev_insn != -1) &&
|
||||
(write_2_short (&prev_opcode, (long)prev_insn, &opcode, (long)insn, extype, fixups) == 0))
|
||||
{
|
||||
/* no instructions saved */
|
||||
prev_insn = -1;
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
if (extype)
|
||||
as_fatal("Unable to mix instructions as specified");
|
||||
/* save off last instruction so it may be packed on next pass */
|
||||
memcpy( &prev_opcode, &opcode, sizeof(prev_opcode));
|
||||
memcpy(&prev_opcode, &opcode, sizeof(prev_opcode));
|
||||
prev_insn = insn;
|
||||
prev_seg = now_seg;
|
||||
prev_subseg = now_subseg;
|
||||
@ -1134,7 +1225,7 @@ do_assemble (str, opcode)
|
||||
else
|
||||
p = 3;
|
||||
|
||||
for(i=1; *str && strncmp(*str,&name[p],2); i++, *str++)
|
||||
for(i=1; *str && strncmp(*str,&name[p],2); i++, str++)
|
||||
;
|
||||
|
||||
/* cmpu only supports some condition codes */
|
||||
@ -1192,6 +1283,14 @@ do_assemble (str, opcode)
|
||||
input_line_pointer = save;
|
||||
|
||||
insn = build_insn (opcode, myops);
|
||||
|
||||
/* Propigate multiply status */
|
||||
if (insn != -1)
|
||||
{
|
||||
prev_mul32_p = cur_mul32_p;
|
||||
cur_mul32_p = (opcode->op->flags_used & FLAG_MUL32) != 0;
|
||||
}
|
||||
|
||||
return (insn);
|
||||
}
|
||||
|
||||
@ -1209,12 +1308,11 @@ find_format (opcode, myops, fsize, cmp_hack)
|
||||
{
|
||||
int numops, match, index, i=0, j, k;
|
||||
struct d30v_format *fm;
|
||||
struct d30v_operand *op;
|
||||
|
||||
/* get all the operands and save them as expressions */
|
||||
numops = get_operands (myops, cmp_hack);
|
||||
|
||||
while (index = opcode->format[i++])
|
||||
while ((index = opcode->format[i++]) != 0)
|
||||
{
|
||||
if ((fsize == FORCE_SHORT) && (index >= LONG))
|
||||
continue;
|
||||
@ -1240,20 +1338,21 @@ find_format (opcode, myops, fsize, cmp_hack)
|
||||
match = 0;
|
||||
else if (flags & OPERAND_REG)
|
||||
{
|
||||
if ((X_op != O_register) ||
|
||||
((flags & OPERAND_ACC) && !(num & OPERAND_ACC)) ||
|
||||
((flags & OPERAND_FLAG) && !(num & OPERAND_FLAG)) ||
|
||||
(flags & OPERAND_CONTROL && !(num & OPERAND_CONTROL | num & OPERAND_FLAG)))
|
||||
if ((X_op != O_register)
|
||||
|| ((flags & OPERAND_ACC) && !(num & OPERAND_ACC))
|
||||
|| ((flags & OPERAND_FLAG) && !(num & OPERAND_FLAG))
|
||||
|| ((flags & OPERAND_CONTROL)
|
||||
&& !(num & (OPERAND_CONTROL | OPERAND_FLAG))))
|
||||
{
|
||||
match = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
if (((flags & OPERAND_MINUS) && ((X_op != O_absent) || (num != OPERAND_MINUS))) ||
|
||||
((flags & OPERAND_PLUS) && ((X_op != O_absent) || (num != OPERAND_PLUS))) ||
|
||||
((flags & OPERAND_ATMINUS) && ((X_op != O_absent) || (num != OPERAND_ATMINUS))) ||
|
||||
((flags & OPERAND_ATPAR) && ((X_op != O_absent) || (num != OPERAND_ATPAR))) ||
|
||||
((flags & OPERAND_ATSIGN) && ((X_op != O_absent) || (num != OPERAND_ATSIGN))))
|
||||
else
|
||||
if (((flags & OPERAND_MINUS) && ((X_op != O_absent) || (num != OPERAND_MINUS)))
|
||||
|| ((flags & OPERAND_PLUS) && ((X_op != O_absent) || (num != OPERAND_PLUS)))
|
||||
|| ((flags & OPERAND_ATMINUS) && ((X_op != O_absent) || (num != OPERAND_ATMINUS)))
|
||||
|| ((flags & OPERAND_ATPAR) && ((X_op != O_absent) || (num != OPERAND_ATPAR)))
|
||||
|| ((flags & OPERAND_ATSIGN) && ((X_op != O_absent) || (num != OPERAND_ATSIGN))))
|
||||
{
|
||||
match=0;
|
||||
}
|
||||
@ -1362,8 +1461,6 @@ md_apply_fix3 (fixp, valuep, seg)
|
||||
char *where;
|
||||
unsigned long insn, insn2;
|
||||
long value;
|
||||
int op_type;
|
||||
int left=0;
|
||||
|
||||
if (fixp->fx_addsy == (symbolS *) NULL)
|
||||
{
|
||||
@ -1402,6 +1499,7 @@ md_apply_fix3 (fixp, valuep, seg)
|
||||
insn |= value & 0x3F;
|
||||
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
|
||||
break;
|
||||
|
||||
case BFD_RELOC_D30V_9_PCREL:
|
||||
if (fixp->fx_where & 0x7)
|
||||
{
|
||||
@ -1414,11 +1512,13 @@ md_apply_fix3 (fixp, valuep, seg)
|
||||
insn |= ((value >> 3) & 0x3F) << 12;
|
||||
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
|
||||
break;
|
||||
|
||||
case BFD_RELOC_D30V_15:
|
||||
check_size (value, 15, fixp->fx_file, fixp->fx_line);
|
||||
insn |= (value >> 3) & 0xFFF;
|
||||
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
|
||||
break;
|
||||
|
||||
case BFD_RELOC_D30V_15_PCREL:
|
||||
if (fixp->fx_where & 0x7)
|
||||
{
|
||||
@ -1431,11 +1531,13 @@ md_apply_fix3 (fixp, valuep, seg)
|
||||
insn |= (value >> 3) & 0xFFF;
|
||||
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
|
||||
break;
|
||||
|
||||
case BFD_RELOC_D30V_21:
|
||||
check_size (value, 21, fixp->fx_file, fixp->fx_line);
|
||||
insn |= (value >> 3) & 0x3FFFF;
|
||||
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
|
||||
break;
|
||||
|
||||
case BFD_RELOC_D30V_21_PCREL:
|
||||
if (fixp->fx_where & 0x7)
|
||||
{
|
||||
@ -1448,25 +1550,29 @@ md_apply_fix3 (fixp, valuep, seg)
|
||||
insn |= (value >> 3) & 0x3FFFF;
|
||||
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
|
||||
break;
|
||||
|
||||
case BFD_RELOC_D30V_32:
|
||||
insn2 = bfd_getb32 ((unsigned char *) where + 4);
|
||||
insn |= (value >> 26) & 0x3F; /* top 6 bits */
|
||||
insn2 |= ((value & 0x03FC0000) << 2); /* next 8 bits */
|
||||
insn |= (value >> 26) & 0x3F; /* top 6 bits */
|
||||
insn2 |= ((value & 0x03FC0000) << 2); /* next 8 bits */
|
||||
insn2 |= value & 0x0003FFFF; /* bottom 18 bits */
|
||||
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
|
||||
bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4);
|
||||
break;
|
||||
|
||||
case BFD_RELOC_D30V_32_PCREL:
|
||||
insn2 = bfd_getb32 ((unsigned char *) where + 4);
|
||||
insn |= (value >> 26) & 0x3F; /* top 6 bits */
|
||||
insn2 |= ((value & 0x03FC0000) << 2); /* next 8 bits */
|
||||
insn |= (value >> 26) & 0x3F; /* top 6 bits */
|
||||
insn2 |= ((value & 0x03FC0000) << 2); /* next 8 bits */
|
||||
insn2 |= value & 0x0003FFFF; /* bottom 18 bits */
|
||||
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
|
||||
bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4);
|
||||
break;
|
||||
|
||||
case BFD_RELOC_32:
|
||||
bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
|
||||
break;
|
||||
|
||||
default:
|
||||
as_fatal ("line %d: unknown relocation type: 0x%x",fixp->fx_line,fixp->fx_r_type);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user