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2007-07-29  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (check_long_reg): Allow cvtss2si to convert
	DWORD memory to Reg64 in Intel synax.
	(check_qword_reg): Allow cvtsd2si to convert QWORD memory to
	Reg32 in Intel syntax.

gas/testsuite/

2007-07-29  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/simd.s: Add tests for cvtss2si/cvtsd2si in Intel
	mode.
	* gas/i386/x86-64-simd.s: Likewise.

	* gas/i386/simd-intel.d: Updated.
	* gas/i386/simd.d: Likewise.
	* gas/i386/x86-64-simd-intel.d: Likewise.
	* gas/i386/x86-64-simd.d: Likewise.
This commit is contained in:
H.J. Lu 2007-07-29 18:27:59 +00:00
parent 48f2ff543d
commit 34828aad95
9 changed files with 71 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
gas/ChangeLog
View File

@ -1,3 +1,10 @@
2007-07-29 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (check_long_reg): Allow cvtss2si to convert
DWORD memory to Reg64 in Intel synax.
(check_qword_reg): Allow cvtsd2si to convert QWORD memory to
Reg32 in Intel syntax.
2007-07-25 Sterling Augustine <sterling@tensilica.com>
* config/tc-xtensa.c (xtensa_extui_opcode): New.

41
gas/config/tc-i386.c
View File

@ -3164,10 +3164,21 @@ check_long_reg (void)
else if ((i.types[op] & Reg64) != 0
&& (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
{
as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
register_prefix, i.op[op].regs->reg_name,
i.suffix);
return 0;
if (intel_syntax
&& i.tm.base_opcode == 0xf30f2d
&& (i.types[0] & RegXMM) == 0)
{
/* cvtss2si converts DWORD memory to Reg64. We want
REX byte. */
i.suffix = QWORD_MNEM_SUFFIX;
}
else
{
as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
register_prefix, i.op[op].regs->reg_name,
i.suffix);
return 0;
}
}
return 1;
}
@ -3191,16 +3202,26 @@ check_qword_reg (void)
return 0;
}
/* Warn if the e prefix on a general reg is missing. */
else if (((i.types[op] & Reg16) != 0
|| (i.types[op] & Reg32) != 0)
else if ((i.types[op] & (Reg16 | Reg32)) != 0
&& (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
{
/* Prohibit these changes in the 64bit mode, since the
lowering is more complicated. */
as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
register_prefix, i.op[op].regs->reg_name,
i.suffix);
return 0;
if (intel_syntax
&& i.tm.base_opcode == 0xf20f2d
&& (i.types[0] & RegXMM) == 0)
{
/* cvtsd2si converts QWORD memory to Reg32. We don't want
REX byte. */
i.suffix = LONG_MNEM_SUFFIX;
}
else
{
as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
register_prefix, i.op[op].regs->reg_name,
i.suffix);
return 0;
}
}
return 1;
}

11
gas/testsuite/ChangeLog
View File

@ -1,3 +1,14 @@
2007-07-29 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/simd.s: Add tests for cvtss2si/cvtsd2si in Intel
mode.
* gas/i386/x86-64-simd.s: Likewise.
* gas/i386/simd-intel.d: Updated.
* gas/i386/simd.d: Likewise.
* gas/i386/x86-64-simd-intel.d: Likewise.
* gas/i386/x86-64-simd.d: Likewise.
2007-07-28 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/4835

2
gas/testsuite/gas/i386/simd-intel.d
View File

@ -70,4 +70,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f3 0f 51 00 sqrtss xmm0,DWORD PTR \[eax\]
[ ]*[a-f0-9]+: f2 0f 5c 00 subsd xmm0,QWORD PTR \[eax\]
[ ]*[a-f0-9]+: f3 0f 5c 00 subss xmm0,DWORD PTR \[eax\]
[ ]*[a-f0-9]+: f3 0f 2d 00 cvtss2si eax,DWORD PTR \[eax\]
[ ]*[a-f0-9]+: f2 0f 2d 00 cvtsd2si eax,QWORD PTR \[eax\]
#pass

2
gas/testsuite/gas/i386/simd.d
View File

@ -69,4 +69,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f3 0f 51 00 sqrtss \(%eax\),%xmm0
[ ]*[a-f0-9]+: f2 0f 5c 00 subsd \(%eax\),%xmm0
[ ]*[a-f0-9]+: f3 0f 5c 00 subss \(%eax\),%xmm0
[ ]*[a-f0-9]+: f3 0f 2d 00 cvtss2si \(%eax\),%eax
[ ]*[a-f0-9]+: f2 0f 2d 00 cvtsd2si \(%eax\),%eax
#pass

4
gas/testsuite/gas/i386/simd.s
View File

@ -63,3 +63,7 @@ _start:
sqrtss (%eax),%xmm0
subsd (%eax),%xmm0
subss (%eax),%xmm0
.intel_syntax noprefix
cvtss2si eax,DWORD PTR [eax]
cvtsd2si eax,QWORD PTR [eax]

4
gas/testsuite/gas/i386/x86-64-simd-intel.d
View File

@ -74,4 +74,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f3 0f 51 00 sqrtss xmm0,DWORD PTR \[rax\]
[ ]*[a-f0-9]+: f2 0f 5c 00 subsd xmm0,QWORD PTR \[rax\]
[ ]*[a-f0-9]+: f3 0f 5c 00 subss xmm0,DWORD PTR \[rax\]
[ ]*[a-f0-9]+: f3 0f 2d 00 cvtss2si eax,DWORD PTR \[rax\]
[ ]*[a-f0-9]+: f3 48 0f 2d 00 cvtss2si rax,DWORD PTR \[rax\]
[ ]*[a-f0-9]+: f2 0f 2d 00 cvtsd2si eax,QWORD PTR \[rax\]
[ ]*[a-f0-9]+: f2 48 0f 2d 00 cvtsd2si rax,QWORD PTR \[rax\]
#pass

4
gas/testsuite/gas/i386/x86-64-simd.d
View File

@ -73,4 +73,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f3 0f 51 00 sqrtss \(%rax\),%xmm0
[ ]*[a-f0-9]+: f2 0f 5c 00 subsd \(%rax\),%xmm0
[ ]*[a-f0-9]+: f3 0f 5c 00 subss \(%rax\),%xmm0
[ ]*[a-f0-9]+: f3 0f 2d 00 cvtss2si \(%rax\),%eax
[ ]*[a-f0-9]+: f3 48 0f 2d 00 cvtss2siq \(%rax\),%rax
[ ]*[a-f0-9]+: f2 0f 2d 00 cvtsd2si \(%rax\),%eax
[ ]*[a-f0-9]+: f2 48 0f 2d 00 cvtsd2siq \(%rax\),%rax
#pass

6
gas/testsuite/gas/i386/x86-64-simd.s
View File

@ -67,3 +67,9 @@ _start:
sqrtss (%rax),%xmm0
subsd (%rax),%xmm0
subss (%rax),%xmm0
.intel_syntax noprefix
cvtss2si eax,DWORD PTR [rax]
cvtss2si rax,DWORD PTR [rax]
cvtsd2si eax,QWORD PTR [rax]
cvtsd2si rax,QWORD PTR [rax]