Index: opcodes
* mep-asm.c: Regenerate. * mep-desc.c: Regenerate. * mep-desc.h: Regenerate. * mep-dis.c: Regenerate. * mep-ibld.c: Regenerate. * mep-opc.c: Regenerate. * mep-opc.h: Regenerate. Index: gas * config/tc-mep.c (md_begin): Check coprocessor type. (md_check_parallel64_scheduling): Use memset to initialize the buffer. (md_check_parallel32_scheduling): Likewise. (slot_ok): New. (mep_check_ivc2_scheduling): New. (mep_check_parallel_scheduling): Call it. (mep_process_saved_insns): Add IVC2 slot support. (md_assemble): Likewise.
This commit is contained in:
parent
4e38f72c0f
commit
3526b6802e
@ -1,3 +1,14 @@
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2009-04-29 DJ Delorie <dj@redhat.com>
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* config/tc-mep.c (md_begin): Check coprocessor type.
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(md_check_parallel64_scheduling): Use memset to initialize the buffer.
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(md_check_parallel32_scheduling): Likewise.
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(slot_ok): New.
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(mep_check_ivc2_scheduling): New.
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(mep_check_parallel_scheduling): Call it.
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(mep_process_saved_insns): Add IVC2 slot support.
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(md_assemble): Likewise.
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2009-04-30 Nick Clifton <nickc@redhat.com>
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* config/obj-elf.c (obj_elf_type): Add support for a
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@ -57,6 +57,7 @@ static int mode = CORE; /* Start in core mode. */
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static int pluspresent = 0;
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static int allow_disabled_registers = 0;
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static int library_flag = 0;
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static int mep_cop = EF_MEP_COP_NONE;
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/* We're going to need to store all of the instructions along with
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their fixups so that we can parallelization grouping rules. */
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@ -465,6 +466,8 @@ md_begin ()
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else
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MEP_OMASK = (MEP_OMASK & ~optbitset) | optbits;
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mep_cop = mep_config_map[mep_config_index].cpu_flag & EF_MEP_COP_MASK;
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/* Set the machine number and endian. */
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gas_cgen_cpu_desc = mep_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
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CGEN_CPU_OPEN_ENDIAN,
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@ -769,11 +772,9 @@ mep_check_parallel64_scheduling (void)
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{
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char *errmsg;
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mep_insn insn;
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int i;
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/* Initialize the insn buffer. */
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for (i = 0; i < 64; i++)
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insn.buffer[i] = '\0';
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memset (insn.buffer, 0, sizeof(insn.buffer));
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/* We have a coprocessor insn. At this point in time there
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are is 32-bit core nop. There is only a 16-bit core
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@ -834,11 +835,9 @@ mep_check_parallel64_scheduling (void)
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{
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char * errmsg;
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mep_insn insn;
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int i;
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/* Initialize the insn buffer */
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for (i = 0; i < 64; i++)
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insn.buffer[i] = '\0';
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memset (insn.buffer, 0, sizeof(insn.buffer));
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/* We have a core insn. We have to handle all possible nop
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lengths. If a coprocessor doesn't have a nop of a certain
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@ -888,6 +887,238 @@ mep_check_parallel64_scheduling (void)
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}
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}
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#ifdef MEP_IVC2_SUPPORTED
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/* IVC2 packing is different than other VLIW coprocessors. Many of
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the COP insns can be placed in any of three different types of
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slots, and each bundle can hold up to three insns - zero or one
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core insns and one or two IVC2 insns. The insns in CGEN are tagged
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with which slots they're allowed in, and we have to decide based on
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that whether or not the user had given us a possible bundling. */
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static int
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slot_ok (int idx, int slot)
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{
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const CGEN_INSN *insn = saved_insns[idx].insn;
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return CGEN_ATTR_CGEN_INSN_SLOTS_VALUE (CGEN_INSN_ATTRS (insn)) & (1 << slot);
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}
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static void
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mep_check_ivc2_scheduling (void)
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{
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/* VLIW modes:
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V1 [-----core-----][--------p0s-------][------------p1------------]
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V2 [-------------core-------------]xxxx[------------p1------------]
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V3 1111[--p0--]0111[--------p0--------][------------p1------------]
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*/
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int slots[5]; /* Indexed off the SLOTS_ATTR enum. */
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int corelength;
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int i;
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bfd_byte temp[4];
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bfd_byte *f;
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int e = target_big_endian ? 0 : 1;
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/* If there are no insns saved, that's ok. Just return. This will
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happen when mep_process_saved_insns is called when the end of the
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source file is reached and there are no insns left to be processed. */
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if (num_insns_saved == 0)
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return;
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for (i=0; i<5; i++)
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slots[i] = -1;
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if (slot_ok (0, SLOTS_CORE))
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{
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slots[SLOTS_CORE] = 0;
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corelength = CGEN_FIELDS_BITSIZE (& saved_insns[0].fields);
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}
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else
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corelength = 0;
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if (corelength == 16)
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{
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/* V1 mode: we need a P0S slot and a P1 slot. */
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switch (num_insns_saved)
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{
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case 1:
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/* No other insns, fill with NOPs. */
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break;
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case 2:
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if (slot_ok (1, SLOTS_P1))
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slots[SLOTS_P1] = 1;
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else if (slot_ok (1, SLOTS_P0S))
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slots[SLOTS_P0S] = 1;
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else
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as_bad ("cannot pack %s with a 16-bit insn",
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CGEN_INSN_NAME (saved_insns[1].insn));
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break;
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case 3:
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if (slot_ok (1, SLOTS_P0S)
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&& slot_ok (2, SLOTS_P1))
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{
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slots[SLOTS_P0S] = 1;
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slots[SLOTS_P1] = 2;
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}
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else if (slot_ok (1, SLOTS_P1)
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&& slot_ok (2, SLOTS_P0S))
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{
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slots[SLOTS_P1] = 1;
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slots[SLOTS_P0S] = 2;
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}
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else
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as_bad ("cannot pack %s and %s together with a 16-bit insn",
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CGEN_INSN_NAME (saved_insns[1].insn),
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CGEN_INSN_NAME (saved_insns[2].insn));
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break;
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default:
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as_bad ("too many IVC2 insns to pack with a 16-bit core insn");
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break;
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}
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}
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else if (corelength == 32)
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{
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/* V2 mode: we need a P1 slot. */
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switch (num_insns_saved)
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{
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case 1:
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/* No other insns, fill with NOPs. */
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break;
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case 2:
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/* The other insn must allow P1. */
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if (!slot_ok (1, SLOTS_P1))
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as_bad ("cannot pack %s into slot P1",
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CGEN_INSN_NAME (saved_insns[1].insn));
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else
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slots[SLOTS_P1] = 1;
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break;
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default:
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as_bad ("too many IVC2 insns to pack with a 32-bit core insn");
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break;
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}
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}
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else if (corelength == 0)
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{
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/* V3 mode: we need a P0 slot and a P1 slot, or a P0S+P1 with a
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core NOP. */
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switch (num_insns_saved)
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{
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case 1:
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if (slot_ok (0, SLOTS_P0))
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slots[SLOTS_P0] = 0;
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else if (slot_ok (0, SLOTS_P1))
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slots[SLOTS_P1] = 0;
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else if (slot_ok (0, SLOTS_P0S))
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slots[SLOTS_P0S] = 0;
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else
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as_bad ("unable to pack %s by itself?",
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CGEN_INSN_NAME (saved_insns[0].insn));
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break;
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case 2:
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if (slot_ok (0, SLOTS_P0)
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&& slot_ok (1, SLOTS_P1))
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{
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slots[SLOTS_P0] = 0;
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slots[SLOTS_P1] = 1;
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}
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else if (slot_ok (0, SLOTS_P1)
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&& slot_ok (1, SLOTS_P0))
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{
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slots[SLOTS_P1] = 0;
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slots[SLOTS_P0] = 1;
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}
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else if (slot_ok (0, SLOTS_P0S)
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&& slot_ok (1, SLOTS_P1))
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{
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slots[SLOTS_P0S] = 0;
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slots[SLOTS_P1] = 1;
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}
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else if (slot_ok (0, SLOTS_P1)
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&& slot_ok (1, SLOTS_P0S))
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{
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slots[SLOTS_P1] = 0;
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slots[SLOTS_P0S] = 1;
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}
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else
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as_bad ("cannot pack %s and %s together",
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CGEN_INSN_NAME (saved_insns[0].insn),
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CGEN_INSN_NAME (saved_insns[1].insn));
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break;
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default:
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as_bad ("too many IVC2 insns to pack together");
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break;
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}
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}
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/* The core insn needs to be done normally so that fixups,
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relaxation, etc are done. Other IVC2 insns need only be resolved
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to bit patterns; there are no relocations for them. */
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if (slots[SLOTS_CORE] != -1)
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{
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gas_cgen_restore_fixups (0);
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gas_cgen_finish_insn (saved_insns[0].insn, saved_insns[0].buffer,
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CGEN_FIELDS_BITSIZE (& saved_insns[0].fields),
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1, NULL);
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}
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/* Allocate whatever bytes remain in our insn word. Adjust the
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pointer to point (as if it were) to the beginning of the whole
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word, so that we don't have to adjust for it elsewhere. */
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f = (bfd_byte *) frag_more (8 - corelength / 8);
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/* Unused slots are filled with NOPs, which happen to be all zeros. */
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memset (f, 0, 8 - corelength / 8);
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f -= corelength / 8;
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for (i=1; i<5; i++)
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{
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mep_insn *m;
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if (slots[i] == -1)
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continue;
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m = & saved_insns[slots[i]];
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#if CGEN_INT_INSN_P
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cgen_put_insn_value (gas_cgen_cpu_desc, (unsigned char *) temp, 32,
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m->buffer[0]);
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#else
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memcpy (temp, m->buffer, byte_len);
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#endif
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switch (i)
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{
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case SLOTS_P0S:
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f[2^e] = temp[1^e];
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f[3^e] = temp[2^e];
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f[4^e] |= temp[3^e] & 0xf0;
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break;
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case SLOTS_P0:
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f[0^e] = 0xf0 | temp[0^e] >> 4;
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f[1^e] = temp[0^e] << 4 | 0x07;
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f[2^e] = temp[1^e];
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f[3^e] = temp[2^e];
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f[4^e] |= temp[3^e] & 0xf0;
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break;
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case SLOTS_P1:
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f[4^e] |= temp[0^e] >> 4;
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f[5^e] = temp[0^e] << 4 | temp[1^e] >> 4;
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f[6^e] = temp[1^e] << 4 | temp[2^e] >> 4;
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f[7^e] = temp[2^e] << 4 | temp[3^e] >> 4;
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break;
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default:
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break;
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}
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}
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}
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#endif /* MEP_IVC2_SUPPORTED */
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/* The scheduling functions are just filters for invalid combinations.
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If there is a violation, they terminate assembly. Otherise they
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just fall through. Succesful combinations cause no side effects
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@ -898,7 +1129,12 @@ mep_check_parallel_scheduling (void)
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{
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/* This is where we will eventually read the config information
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and choose which scheduling checking function to call. */
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if (MEP_VLIW64)
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#ifdef MEP_IVC2_SUPPORTED
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if (mep_cop == EF_MEP_COP_IVC2)
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mep_check_ivc2_scheduling ();
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else
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#endif /* MEP_IVC2_SUPPORTED */
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if (MEP_VLIW64)
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mep_check_parallel64_scheduling ();
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else
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mep_check_parallel32_scheduling ();
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@ -908,21 +1144,31 @@ static void
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mep_process_saved_insns (void)
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{
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int i;
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unsigned j;
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gas_cgen_save_fixups (MAX_SAVED_FIXUP_CHAINS - 1);
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/* We have to check for valid scheduling here. */
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mep_check_parallel_scheduling ();
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/* If the last call didn't cause assembly to terminate, we have
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a valid vliw insn/insn pair saved. Restore this instructions'
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fixups and process the insns. */
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for (i = 0;i<num_insns_saved;i++)
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/* IVC2 has to pack instructions in a funny way, so it does it
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itself. */
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if (mep_cop != EF_MEP_COP_IVC2)
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{
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gas_cgen_restore_fixups (i);
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gas_cgen_finish_insn (saved_insns[i].insn, saved_insns[i].buffer,
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CGEN_FIELDS_BITSIZE (& saved_insns[i].fields),
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1, NULL);
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/* If the last call didn't cause assembly to terminate, we have
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a valid vliw insn/insn pair saved. Restore this instructions'
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fixups and process the insns. */
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for (i = 0;i<num_insns_saved;i++)
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{
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gas_cgen_restore_fixups (i);
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gas_cgen_finish_insn (saved_insns[i].insn, saved_insns[i].buffer,
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CGEN_FIELDS_BITSIZE (& saved_insns[i].fields),
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1, NULL);
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printf("insn[%d] =", i);
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for (j=0; j<sizeof(saved_insns[i].buffer); j++)
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printf(" %02x", saved_insns[i].buffer[j]);
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printf("\n");
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}
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}
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gas_cgen_restore_fixups (MAX_SAVED_FIXUP_CHAINS - 1);
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@ -984,8 +1230,25 @@ md_assemble (char * str)
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for (i=0; i < CGEN_MAX_INSN_SIZE; i++)
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insn.buffer[i]='\0';
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/* Can't tell core / copro insns apart at parse time! */
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cgen_bitset_union (isas, & MEP_COP_ISA, isas);
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/* IVC2 has two sets of coprocessor opcodes, one for CORE mode
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and one for VLIW mode. They have the same names. To specify
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which one we want, we use the COP isas - the 32 bit ISA is
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for the core instructions (which are always 32 bits), and the
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other ISAs are for the VLIW ones (which always pack into 64
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bit insns). We use other attributes to determine slotting
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later. */
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if (mep_cop == EF_MEP_COP_IVC2)
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{
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cgen_bitset_union (isas, & MEP_COP16_ISA, isas);
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cgen_bitset_union (isas, & MEP_COP48_ISA, isas);
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cgen_bitset_union (isas, & MEP_COP64_ISA, isas);
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}
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else
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{
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/* Can't tell core / copro insns apart at parse time! */
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cgen_bitset_union (isas, & MEP_COP_ISA, isas);
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}
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/* Assemble the insn so we can examine its attributes. */
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insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, str,
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@ -1068,6 +1331,10 @@ md_assemble (char * str)
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/* Only single instructions are assembled in core mode. */
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mep_insn insn;
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/* See comment in the VLIW clause above about this. */
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if (mep_cop & EF_MEP_COP_IVC2)
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cgen_bitset_union (isas, & MEP_COP32_ISA, isas);
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/* If a leading '+' was present, issue an error.
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That's not allowed in core mode. */
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if (pluspresent)
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@ -1,3 +1,13 @@
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2009-04-30 DJ Delorie <dj@redhat.com>
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* mep-asm.c: Regenerate.
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* mep-desc.c: Regenerate.
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* mep-desc.h: Regenerate.
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* mep-dis.c: Regenerate.
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* mep-ibld.c: Regenerate.
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* mep-opc.c: Regenerate.
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* mep-opc.h: Regenerate.
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2009-04-17 DJ Delorie <dj@redhat.com
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* mep-desc.c: Regenerate.
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|
@ -85,6 +85,32 @@ parse_csrn (CGEN_CPU_DESC cd, const char **strp,
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}
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/* begin-cop-ip-parse-handlers */
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static const char *
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parse_ivc2_cr (CGEN_CPU_DESC,
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const char **,
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CGEN_KEYWORD *,
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long *) ATTRIBUTE_UNUSED;
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static const char *
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parse_ivc2_cr (CGEN_CPU_DESC cd,
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const char **strp,
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CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED,
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long *field)
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{
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return cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr_ivc2, field);
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}
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static const char *
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parse_ivc2_ccr (CGEN_CPU_DESC,
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const char **,
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CGEN_KEYWORD *,
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long *) ATTRIBUTE_UNUSED;
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static const char *
|
||||
parse_ivc2_ccr (CGEN_CPU_DESC cd,
|
||||
const char **strp,
|
||||
CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED,
|
||||
long *field)
|
||||
{
|
||||
return cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, field);
|
||||
}
|
||||
/* end-cop-ip-parse-handlers */
|
||||
|
||||
const char *
|
||||
@ -840,6 +866,24 @@ mep_cgen_parse_operand (CGEN_CPU_DESC cd,
|
||||
case MEP_OPERAND_CRNX64 :
|
||||
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr64, & fields->f_crnx);
|
||||
break;
|
||||
case MEP_OPERAND_CROC :
|
||||
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr64, & fields->f_ivc2_5u7);
|
||||
break;
|
||||
case MEP_OPERAND_CROP :
|
||||
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr64, & fields->f_ivc2_5u23);
|
||||
break;
|
||||
case MEP_OPERAND_CRPC :
|
||||
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr64, & fields->f_ivc2_5u26);
|
||||
break;
|
||||
case MEP_OPERAND_CRPP :
|
||||
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr64, & fields->f_ivc2_5u18);
|
||||
break;
|
||||
case MEP_OPERAND_CRQC :
|
||||
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr64, & fields->f_ivc2_5u21);
|
||||
break;
|
||||
case MEP_OPERAND_CRQP :
|
||||
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr64, & fields->f_ivc2_5u13);
|
||||
break;
|
||||
case MEP_OPERAND_CSRN :
|
||||
errmsg = parse_csrn (cd, strp, & mep_cgen_opval_h_csr, & fields->f_csrn);
|
||||
break;
|
||||
@ -861,6 +905,90 @@ mep_cgen_parse_operand (CGEN_CPU_DESC cd,
|
||||
case MEP_OPERAND_HI :
|
||||
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk);
|
||||
break;
|
||||
case MEP_OPERAND_IMM16P0 :
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM16P0, (unsigned long *) (& fields->f_ivc2_imm16p0));
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P12 :
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM3P12, (unsigned long *) (& fields->f_ivc2_3u12));
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P25 :
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM3P25, (unsigned long *) (& fields->f_ivc2_3u25));
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P4 :
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM3P4, (unsigned long *) (& fields->f_ivc2_3u4));
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P5 :
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM3P5, (unsigned long *) (& fields->f_ivc2_3u5));
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P9 :
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM3P9, (unsigned long *) (& fields->f_ivc2_3u9));
|
||||
break;
|
||||
case MEP_OPERAND_IMM4P10 :
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM4P10, (unsigned long *) (& fields->f_ivc2_4u10));
|
||||
break;
|
||||
case MEP_OPERAND_IMM4P4 :
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM4P4, (unsigned long *) (& fields->f_ivc2_4u4));
|
||||
break;
|
||||
case MEP_OPERAND_IMM4P8 :
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM4P8, (unsigned long *) (& fields->f_ivc2_4u8));
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P23 :
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM5P23, (unsigned long *) (& fields->f_ivc2_5u23));
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P3 :
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM5P3, (unsigned long *) (& fields->f_ivc2_5u3));
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P7 :
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM5P7, (unsigned long *) (& fields->f_ivc2_5u7));
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P8 :
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM5P8, (unsigned long *) (& fields->f_ivc2_5u8));
|
||||
break;
|
||||
case MEP_OPERAND_IMM6P2 :
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM6P2, (unsigned long *) (& fields->f_ivc2_6u2));
|
||||
break;
|
||||
case MEP_OPERAND_IMM6P6 :
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM6P6, (unsigned long *) (& fields->f_ivc2_6u6));
|
||||
break;
|
||||
case MEP_OPERAND_IMM8P0 :
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM8P0, (unsigned long *) (& fields->f_ivc2_8u0));
|
||||
break;
|
||||
case MEP_OPERAND_IMM8P20 :
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM8P20, (unsigned long *) (& fields->f_ivc2_8u20));
|
||||
break;
|
||||
case MEP_OPERAND_IMM8P4 :
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IMM8P4, (unsigned long *) (& fields->f_ivc2_8u4));
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_2 :
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IVC_X_0_2, (unsigned long *) (& fields->f_ivc2_2u0));
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_3 :
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IVC_X_0_3, (unsigned long *) (& fields->f_ivc2_3u0));
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_4 :
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IVC_X_0_4, (unsigned long *) (& fields->f_ivc2_4u0));
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_5 :
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IVC_X_0_5, (unsigned long *) (& fields->f_ivc2_5u0));
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_6_1 :
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IVC_X_6_1, (unsigned long *) (& fields->f_ivc2_1u6));
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_6_2 :
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IVC_X_6_2, (unsigned long *) (& fields->f_ivc2_2u6));
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_6_3 :
|
||||
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IVC_X_6_3, (unsigned long *) (& fields->f_ivc2_3u6));
|
||||
break;
|
||||
case MEP_OPERAND_IVC2CCRN :
|
||||
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr, & fields->f_ivc2_ccrn);
|
||||
break;
|
||||
case MEP_OPERAND_IVC2CRN :
|
||||
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr64, & fields->f_ivc2_crnx);
|
||||
break;
|
||||
case MEP_OPERAND_IVC2RM :
|
||||
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_ivc2_crm);
|
||||
break;
|
||||
case MEP_OPERAND_LO :
|
||||
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk);
|
||||
break;
|
||||
@ -972,12 +1100,21 @@ mep_cgen_parse_operand (CGEN_CPU_DESC cd,
|
||||
case MEP_OPERAND_SIMM16 :
|
||||
errmsg = parse_signed16 (cd, strp, MEP_OPERAND_SIMM16, (long *) (& fields->f_16s16));
|
||||
break;
|
||||
case MEP_OPERAND_SIMM16P0 :
|
||||
errmsg = cgen_parse_signed_integer (cd, strp, MEP_OPERAND_SIMM16P0, (long *) (& fields->f_ivc2_simm16p0));
|
||||
break;
|
||||
case MEP_OPERAND_SIMM6 :
|
||||
errmsg = cgen_parse_signed_integer (cd, strp, MEP_OPERAND_SIMM6, (long *) (& fields->f_6s8));
|
||||
break;
|
||||
case MEP_OPERAND_SIMM8 :
|
||||
errmsg = cgen_parse_signed_integer (cd, strp, MEP_OPERAND_SIMM8, (long *) (& fields->f_8s8));
|
||||
break;
|
||||
case MEP_OPERAND_SIMM8P0 :
|
||||
errmsg = cgen_parse_signed_integer (cd, strp, MEP_OPERAND_SIMM8P0, (long *) (& fields->f_ivc2_8s0));
|
||||
break;
|
||||
case MEP_OPERAND_SIMM8P4 :
|
||||
errmsg = cgen_parse_signed_integer (cd, strp, MEP_OPERAND_SIMM8P4, (long *) (& fields->f_ivc2_8s4));
|
||||
break;
|
||||
case MEP_OPERAND_SP :
|
||||
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & junk);
|
||||
break;
|
||||
|
4584
opcodes/mep-desc.c
4584
opcodes/mep-desc.c
File diff suppressed because it is too large
Load Diff
@ -51,7 +51,7 @@ This file is part of the GNU Binutils and/or GDB, the GNU debugger.
|
||||
#define CGEN_INT_INSN_P 1
|
||||
|
||||
/* Maximum number of syntax elements in an instruction. */
|
||||
#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 18
|
||||
#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 22
|
||||
|
||||
/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
|
||||
e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
|
||||
@ -59,7 +59,7 @@ This file is part of the GNU Binutils and/or GDB, the GNU debugger.
|
||||
#define CGEN_MNEMONIC_OPERANDS
|
||||
|
||||
/* Maximum number of fields in an instruction. */
|
||||
#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 9
|
||||
#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 10
|
||||
|
||||
/* Enums. */
|
||||
|
||||
@ -81,7 +81,8 @@ typedef enum mach_attr {
|
||||
|
||||
/* Enum declaration for instruction set selection. */
|
||||
typedef enum isa_attr {
|
||||
ISA_MEP, ISA_EXT_CORE1, ISA_MAX
|
||||
ISA_MEP, ISA_EXT_CORE1, ISA_EXT_COP1_16, ISA_EXT_COP1_32
|
||||
, ISA_EXT_COP1_48, ISA_EXT_COP1_64, ISA_MAX
|
||||
} ISA_ATTR;
|
||||
|
||||
/* Enum declaration for datatype to use for C intrinsics mapping. */
|
||||
@ -96,6 +97,12 @@ typedef enum config_attr {
|
||||
CONFIG_NONE, CONFIG_DEFAULT
|
||||
} CONFIG_ATTR;
|
||||
|
||||
/* Enum declaration for slots for which this opcode is valid - c3, p0s, p0, p1. */
|
||||
typedef enum slots_attr {
|
||||
SLOTS_CORE, SLOTS_C3, SLOTS_P0S, SLOTS_P0
|
||||
, SLOTS_P1
|
||||
} SLOTS_ATTR;
|
||||
|
||||
/* Number of architecture variants. */
|
||||
#define MAX_ISAS ((int) ISA_MAX)
|
||||
#define MAX_MACHS ((int) MACH_MAX)
|
||||
@ -151,7 +158,20 @@ typedef enum ifield_type {
|
||||
, MEP_F_CCRN_LO, MEP_F_CCRN, MEP_F_C5N4, MEP_F_C5N5
|
||||
, MEP_F_C5N6, MEP_F_C5N7, MEP_F_RL5, MEP_F_12S20
|
||||
, MEP_F_C5_RNM, MEP_F_C5_RM, MEP_F_C5_16U16, MEP_F_C5_RMUIMM20
|
||||
, MEP_F_C5_RNMUIMM24, MEP_F_MAX
|
||||
, MEP_F_C5_RNMUIMM24, MEP_F_IVC2_2U4, MEP_F_IVC2_3U4, MEP_F_IVC2_8U4
|
||||
, MEP_F_IVC2_8S4, MEP_F_IVC2_1U6, MEP_F_IVC2_2U6, MEP_F_IVC2_3U6
|
||||
, MEP_F_IVC2_6U6, MEP_F_IVC2_5U7, MEP_F_IVC2_4U8, MEP_F_IVC2_3U9
|
||||
, MEP_F_IVC2_5U16, MEP_F_IVC2_5U21, MEP_F_IVC2_5U26, MEP_F_IVC2_1U31
|
||||
, MEP_F_IVC2_4U16, MEP_F_IVC2_4U20, MEP_F_IVC2_4U24, MEP_F_IVC2_4U28
|
||||
, MEP_F_IVC2_2U0, MEP_F_IVC2_3U0, MEP_F_IVC2_4U0, MEP_F_IVC2_5U0
|
||||
, MEP_F_IVC2_8U0, MEP_F_IVC2_8S0, MEP_F_IVC2_6U2, MEP_F_IVC2_5U3
|
||||
, MEP_F_IVC2_4U4, MEP_F_IVC2_3U5, MEP_F_IVC2_5U8, MEP_F_IVC2_4U10
|
||||
, MEP_F_IVC2_3U12, MEP_F_IVC2_5U13, MEP_F_IVC2_2U18, MEP_F_IVC2_5U18
|
||||
, MEP_F_IVC2_8U20, MEP_F_IVC2_8S20, MEP_F_IVC2_5U23, MEP_F_IVC2_2U23
|
||||
, MEP_F_IVC2_3U25, MEP_F_IVC2_IMM16P0, MEP_F_IVC2_SIMM16P0, MEP_F_IVC2_CRN
|
||||
, MEP_F_IVC2_CRM, MEP_F_IVC2_CCRN_H1, MEP_F_IVC2_CCRN_H2, MEP_F_IVC2_CCRN_LO
|
||||
, MEP_F_IVC2_CMOV1, MEP_F_IVC2_CMOV2, MEP_F_IVC2_CMOV3, MEP_F_IVC2_CCRN
|
||||
, MEP_F_IVC2_CRNX, MEP_F_MAX
|
||||
} IFIELD_TYPE;
|
||||
|
||||
#define MAX_IFLD ((int) MEP_F_MAX)
|
||||
@ -181,7 +201,8 @@ typedef enum cgen_hw_attr {
|
||||
typedef enum cgen_hw_type {
|
||||
HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
|
||||
, HW_H_IADDR, HW_H_PC, HW_H_GPR, HW_H_CSR
|
||||
, HW_H_CR64, HW_H_CR, HW_H_CCR, HW_MAX
|
||||
, HW_H_CR64, HW_H_CR64_W, HW_H_CR, HW_H_CCR
|
||||
, HW_H_CCR_W, HW_H_CR_IVC2, HW_H_CCR_IVC2, HW_MAX
|
||||
} CGEN_HW_TYPE;
|
||||
|
||||
#define MAX_HW ((int) HW_MAX)
|
||||
@ -236,11 +257,21 @@ typedef enum cgen_operand_type {
|
||||
, MEP_OPERAND_UDISP7A4, MEP_OPERAND_UIMM7A4, MEP_OPERAND_UIMM24, MEP_OPERAND_CIMM4
|
||||
, MEP_OPERAND_CIMM5, MEP_OPERAND_CDISP10, MEP_OPERAND_CDISP10A2, MEP_OPERAND_CDISP10A4
|
||||
, MEP_OPERAND_CDISP10A8, MEP_OPERAND_ZERO, MEP_OPERAND_RL5, MEP_OPERAND_CDISP12
|
||||
, MEP_OPERAND_C5RMUIMM20, MEP_OPERAND_C5RNMUIMM24, MEP_OPERAND_CP_FLAG, MEP_OPERAND_MAX
|
||||
, MEP_OPERAND_C5RMUIMM20, MEP_OPERAND_C5RNMUIMM24, MEP_OPERAND_CP_FLAG, MEP_OPERAND_CROC
|
||||
, MEP_OPERAND_CRQC, MEP_OPERAND_CRPC, MEP_OPERAND_IVC_X_6_1, MEP_OPERAND_IVC_X_6_2
|
||||
, MEP_OPERAND_IVC_X_6_3, MEP_OPERAND_IMM3P4, MEP_OPERAND_IMM3P9, MEP_OPERAND_IMM4P8
|
||||
, MEP_OPERAND_IMM5P7, MEP_OPERAND_IMM6P6, MEP_OPERAND_IMM8P4, MEP_OPERAND_SIMM8P4
|
||||
, MEP_OPERAND_IMM3P5, MEP_OPERAND_IMM3P12, MEP_OPERAND_IMM4P4, MEP_OPERAND_IMM4P10
|
||||
, MEP_OPERAND_IMM5P8, MEP_OPERAND_IMM5P3, MEP_OPERAND_IMM6P2, MEP_OPERAND_IMM5P23
|
||||
, MEP_OPERAND_IMM3P25, MEP_OPERAND_IMM8P0, MEP_OPERAND_SIMM8P0, MEP_OPERAND_IMM8P20
|
||||
, MEP_OPERAND_CROP, MEP_OPERAND_CRQP, MEP_OPERAND_CRPP, MEP_OPERAND_IVC_X_0_2
|
||||
, MEP_OPERAND_IVC_X_0_3, MEP_OPERAND_IVC_X_0_4, MEP_OPERAND_IVC_X_0_5, MEP_OPERAND_IMM16P0
|
||||
, MEP_OPERAND_SIMM16P0, MEP_OPERAND_IVC2RM, MEP_OPERAND_IVC2CRN, MEP_OPERAND_IVC2CCRN
|
||||
, MEP_OPERAND_MAX
|
||||
} CGEN_OPERAND_TYPE;
|
||||
|
||||
/* Number of operands types. */
|
||||
#define MAX_OPERANDS 83
|
||||
#define MAX_OPERANDS 120
|
||||
|
||||
/* Maximum number of operands referenced by any insn. */
|
||||
#define MAX_OPERAND_INSTANCES 8
|
||||
@ -258,7 +289,7 @@ typedef enum cgen_insn_attr {
|
||||
, CGEN_INSN_OPTIONAL_VLIW64, CGEN_INSN_MAY_TRAP, CGEN_INSN_VLIW_ALONE, CGEN_INSN_VLIW_NO_CORE_NOP
|
||||
, CGEN_INSN_VLIW_NO_COP_NOP, CGEN_INSN_VLIW64_NO_MATCHING_NOP, CGEN_INSN_VLIW32_NO_MATCHING_NOP, CGEN_INSN_VOLATILE
|
||||
, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_ISA
|
||||
, CGEN_INSN_LATENCY, CGEN_INSN_CONFIG, CGEN_INSN_END_NBOOLS
|
||||
, CGEN_INSN_LATENCY, CGEN_INSN_CONFIG, CGEN_INSN_SLOTS, CGEN_INSN_END_NBOOLS
|
||||
} CGEN_INSN_ATTR;
|
||||
|
||||
/* Number of non-boolean elements in cgen_insn_attr. */
|
||||
@ -269,6 +300,7 @@ typedef enum cgen_insn_attr {
|
||||
#define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset)
|
||||
#define CGEN_ATTR_CGEN_INSN_LATENCY_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_LATENCY-CGEN_INSN_START_NBOOLS-1].nonbitset)
|
||||
#define CGEN_ATTR_CGEN_INSN_CONFIG_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_CONFIG-CGEN_INSN_START_NBOOLS-1].nonbitset)
|
||||
#define CGEN_ATTR_CGEN_INSN_SLOTS_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_SLOTS-CGEN_INSN_START_NBOOLS-1].nonbitset)
|
||||
#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
|
||||
@ -320,6 +352,8 @@ extern CGEN_KEYWORD mep_cgen_opval_h_csr;
|
||||
extern CGEN_KEYWORD mep_cgen_opval_h_cr64;
|
||||
extern CGEN_KEYWORD mep_cgen_opval_h_cr;
|
||||
extern CGEN_KEYWORD mep_cgen_opval_h_ccr;
|
||||
extern CGEN_KEYWORD mep_cgen_opval_h_cr_ivc2;
|
||||
extern CGEN_KEYWORD mep_cgen_opval_h_ccr_ivc2;
|
||||
|
||||
extern const CGEN_HW_ENTRY mep_cgen_hw_table[];
|
||||
|
||||
|
@ -89,6 +89,36 @@ print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
|
||||
}
|
||||
|
||||
/* begin-cop-ip-print-handlers */
|
||||
static void
|
||||
print_ivc2_cr (CGEN_CPU_DESC,
|
||||
void *,
|
||||
CGEN_KEYWORD *,
|
||||
long,
|
||||
unsigned int) ATTRIBUTE_UNUSED;
|
||||
static void
|
||||
print_ivc2_cr (CGEN_CPU_DESC cd,
|
||||
void *dis_info,
|
||||
CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED,
|
||||
long value,
|
||||
unsigned int attrs)
|
||||
{
|
||||
print_keyword (cd, dis_info, & mep_cgen_opval_h_cr_ivc2, value, attrs);
|
||||
}
|
||||
static void
|
||||
print_ivc2_ccr (CGEN_CPU_DESC,
|
||||
void *,
|
||||
CGEN_KEYWORD *,
|
||||
long,
|
||||
unsigned int) ATTRIBUTE_UNUSED;
|
||||
static void
|
||||
print_ivc2_ccr (CGEN_CPU_DESC cd,
|
||||
void *dis_info,
|
||||
CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED,
|
||||
long value,
|
||||
unsigned int attrs)
|
||||
{
|
||||
print_keyword (cd, dis_info, & mep_cgen_opval_h_ccr_ivc2, value, attrs);
|
||||
}
|
||||
/* end-cop-ip-print-handlers */
|
||||
|
||||
/************************************************************\
|
||||
@ -424,10 +454,199 @@ mep_examine_vliw64_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
|
||||
return status;
|
||||
}
|
||||
|
||||
#ifdef MEP_IVC2_SUPPORTED
|
||||
|
||||
static int
|
||||
print_slot_insn (CGEN_CPU_DESC cd,
|
||||
bfd_vma pc,
|
||||
disassemble_info *info,
|
||||
SLOTS_ATTR slot,
|
||||
bfd_byte *buf)
|
||||
{
|
||||
const CGEN_INSN_LIST *insn_list;
|
||||
CGEN_INSN_INT insn_value;
|
||||
CGEN_EXTRACT_INFO ex_info;
|
||||
|
||||
insn_value = cgen_get_insn_value (cd, buf, 32);
|
||||
|
||||
/* Fill in ex_info fields like read_insn would. Don't actually call
|
||||
read_insn, since the incoming buffer is already read (and possibly
|
||||
modified a la m32r). */
|
||||
ex_info.valid = (1 << 8) - 1;
|
||||
ex_info.dis_info = info;
|
||||
ex_info.insn_bytes = buf;
|
||||
|
||||
/* The instructions are stored in hash lists.
|
||||
Pick the first one and keep trying until we find the right one. */
|
||||
|
||||
insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
|
||||
while (insn_list != NULL)
|
||||
{
|
||||
const CGEN_INSN *insn = insn_list->insn;
|
||||
CGEN_FIELDS fields;
|
||||
int length;
|
||||
|
||||
if ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG)
|
||||
&& CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) != MEP_CONFIG)
|
||||
|| ! (CGEN_ATTR_CGEN_INSN_SLOTS_VALUE (CGEN_INSN_ATTRS (insn)) & (1 << slot)))
|
||||
{
|
||||
insn_list = CGEN_DIS_NEXT_INSN (insn_list);
|
||||
continue;
|
||||
}
|
||||
|
||||
if ((insn_value & CGEN_INSN_BASE_MASK (insn))
|
||||
== CGEN_INSN_BASE_VALUE (insn))
|
||||
{
|
||||
/* Printing is handled in two passes. The first pass parses the
|
||||
machine insn and extracts the fields. The second pass prints
|
||||
them. */
|
||||
|
||||
length = CGEN_EXTRACT_FN (cd, insn)
|
||||
(cd, insn, &ex_info, insn_value, &fields, pc);
|
||||
|
||||
/* Length < 0 -> error. */
|
||||
if (length < 0)
|
||||
return length;
|
||||
if (length > 0)
|
||||
{
|
||||
CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
|
||||
/* Length is in bits, result is in bytes. */
|
||||
return length / 8;
|
||||
}
|
||||
}
|
||||
|
||||
insn_list = CGEN_DIS_NEXT_INSN (insn_list);
|
||||
}
|
||||
|
||||
if (slot == SLOTS_P0S)
|
||||
(*info->fprintf_func) (info->stream, "*unknown-p0s*");
|
||||
else if (slot == SLOTS_P0)
|
||||
(*info->fprintf_func) (info->stream, "*unknown-p0*");
|
||||
else if (slot == SLOTS_P1)
|
||||
(*info->fprintf_func) (info->stream, "*unknown-p1*");
|
||||
else if (slot == SLOTS_C3)
|
||||
(*info->fprintf_func) (info->stream, "*unknown-c3*");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mep_examine_ivc2_insns (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, disassemble_info *info ATTRIBUTE_UNUSED)
|
||||
{
|
||||
int status;
|
||||
int buflength;
|
||||
int cop2buflength;
|
||||
bfd_byte buf[8];
|
||||
bfd_byte insn[8];
|
||||
int e;
|
||||
|
||||
/* At this time we're not supporting internally parallel
|
||||
coprocessors, so cop2buflength will always be 0. */
|
||||
cop2buflength = 0;
|
||||
|
||||
/* Read in 64 bits. */
|
||||
buflength = 8; /* VLIW insn spans 8 bytes. */
|
||||
status = (*info->read_memory_func) (pc, buf, buflength, info);
|
||||
|
||||
if (status != 0)
|
||||
{
|
||||
(*info->memory_error_func) (status, pc, info);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (info->endian == BFD_ENDIAN_LITTLE)
|
||||
e = 1;
|
||||
else
|
||||
e = 0;
|
||||
|
||||
if ((buf[0^e] & 0xf0) != 0xf0)
|
||||
{
|
||||
/* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */
|
||||
/* V1 [-----core-----][--------p0s-------][------------p1------------] */
|
||||
|
||||
print_insn (cd, pc, info, buf, 2);
|
||||
|
||||
insn[0^e] = 0;
|
||||
insn[1^e] = buf[2^e];
|
||||
insn[2^e] = buf[3^e];
|
||||
insn[3^e] = buf[4^e] & 0xf0;
|
||||
(*info->fprintf_func) (info->stream, " + ");
|
||||
print_slot_insn (cd, pc, info, SLOTS_P0S, insn);
|
||||
|
||||
insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4;
|
||||
insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4;
|
||||
insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4;
|
||||
insn[3^e] = buf[7^e] << 4;
|
||||
(*info->fprintf_func) (info->stream, " + ");
|
||||
print_slot_insn (cd, pc, info, SLOTS_P1, insn);
|
||||
}
|
||||
else if ((buf[0^e] & 0xf0) == 0xf0 && (buf[1^e] & 0x0f) == 0x07)
|
||||
{
|
||||
/* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */
|
||||
/* V3 1111[--p0--]0111[--------p0--------][------------p1------------] */
|
||||
/* 00000000111111112222222233333333 */
|
||||
|
||||
insn[0^e] = buf[0^e] << 4 | buf[1^e] >> 4;
|
||||
insn[1^e] = buf[2^e];
|
||||
insn[2^e] = buf[3^e];
|
||||
insn[3^e] = buf[4^e] & 0xf0;
|
||||
print_slot_insn (cd, pc, info, SLOTS_P0, insn);
|
||||
|
||||
insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4;
|
||||
insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4;
|
||||
insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4;
|
||||
insn[3^e] = buf[7^e] << 4;
|
||||
(*info->fprintf_func) (info->stream, " + ");
|
||||
print_slot_insn (cd, pc, info, SLOTS_P1, insn);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */
|
||||
/* V2 [-------------core-------------]xxxx[------------p1------------] */
|
||||
print_insn (cd, pc, info, buf, 4);
|
||||
|
||||
insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4;
|
||||
insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4;
|
||||
insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4;
|
||||
insn[3^e] = buf[7^e] << 4;
|
||||
(*info->fprintf_func) (info->stream, " + ");
|
||||
print_slot_insn (cd, pc, info, SLOTS_P1, insn);
|
||||
}
|
||||
|
||||
return 8;
|
||||
}
|
||||
|
||||
#endif /* MEP_IVC2_SUPPORTED */
|
||||
|
||||
/* This is a hack. SID calls this to update the disassembler as the
|
||||
CPU changes modes. */
|
||||
static int mep_ivc2_disassemble_p = 0;
|
||||
static int mep_ivc2_vliw_disassemble_p = 0;
|
||||
|
||||
void
|
||||
mep_print_insn_set_ivc2_mode (int ivc2_p, int vliw_p, int cfg_idx);
|
||||
void
|
||||
mep_print_insn_set_ivc2_mode (int ivc2_p, int vliw_p, int cfg_idx)
|
||||
{
|
||||
mep_ivc2_disassemble_p = ivc2_p;
|
||||
mep_ivc2_vliw_disassemble_p = vliw_p;
|
||||
mep_config_index = cfg_idx;
|
||||
}
|
||||
|
||||
static int
|
||||
mep_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
|
||||
{
|
||||
int status;
|
||||
int cop_type;
|
||||
int ivc2 = 0;
|
||||
static CGEN_ATTR_VALUE_BITSET_TYPE *ivc2_core_isa = NULL;
|
||||
|
||||
if (ivc2_core_isa == NULL)
|
||||
{
|
||||
/* IVC2 has some core-only coprocessor instructions. We
|
||||
use COP32 to flag those, and COP64 for the VLIW ones,
|
||||
since they have the same names. */
|
||||
ivc2_core_isa = cgen_bitset_create (MAX_ISAS);
|
||||
}
|
||||
|
||||
/* Extract and adapt to configuration number, if available. */
|
||||
if (info->section && info->section->owner)
|
||||
@ -435,6 +654,10 @@ mep_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
|
||||
bfd *abfd = info->section->owner;
|
||||
mep_config_index = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_INDEX_MASK;
|
||||
/* This instantly redefines MEP_CONFIG, MEP_OMASK, .... MEP_VLIW64 */
|
||||
|
||||
cop_type = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_COP_MASK;
|
||||
if (cop_type == EF_MEP_COP_IVC2)
|
||||
ivc2 = 1;
|
||||
}
|
||||
|
||||
/* Picking the right ISA bitmask for the current context is tricky. */
|
||||
@ -442,21 +665,55 @@ mep_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
|
||||
{
|
||||
if (info->section->flags & SEC_MEP_VLIW)
|
||||
{
|
||||
/* Are we in 32 or 64 bit vliw mode? */
|
||||
if (MEP_VLIW64)
|
||||
status = mep_examine_vliw64_insns (cd, pc, info);
|
||||
#ifdef MEP_IVC2_SUPPORTED
|
||||
if (ivc2)
|
||||
{
|
||||
/* ivc2 has its own way of selecting its functions. */
|
||||
cd->isas = & MEP_CORE_ISA;
|
||||
status = mep_examine_ivc2_insns (cd, pc, info);
|
||||
}
|
||||
else
|
||||
status = mep_examine_vliw32_insns (cd, pc, info);
|
||||
#endif
|
||||
/* Are we in 32 or 64 bit vliw mode? */
|
||||
if (MEP_VLIW64)
|
||||
status = mep_examine_vliw64_insns (cd, pc, info);
|
||||
else
|
||||
status = mep_examine_vliw32_insns (cd, pc, info);
|
||||
/* Both the above branches set their own isa bitmasks. */
|
||||
}
|
||||
else
|
||||
{
|
||||
cd->isas = & MEP_CORE_ISA;
|
||||
if (ivc2)
|
||||
{
|
||||
cgen_bitset_clear (ivc2_core_isa);
|
||||
cgen_bitset_union (ivc2_core_isa, &MEP_CORE_ISA, ivc2_core_isa);
|
||||
cgen_bitset_union (ivc2_core_isa, &MEP_COP32_ISA, ivc2_core_isa);
|
||||
cd->isas = ivc2_core_isa;
|
||||
}
|
||||
else
|
||||
cd->isas = & MEP_CORE_ISA;
|
||||
status = default_print_insn (cd, pc, info);
|
||||
}
|
||||
}
|
||||
else /* sid or gdb */
|
||||
{
|
||||
#ifdef MEP_IVC2_SUPPORTED
|
||||
if (mep_ivc2_disassemble_p)
|
||||
{
|
||||
if (mep_ivc2_vliw_disassemble_p)
|
||||
{
|
||||
cd->isas = & MEP_CORE_ISA;
|
||||
status = mep_examine_ivc2_insns (cd, pc, info);
|
||||
return status;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (ivc2)
|
||||
cd->isas = ivc2_core_isa;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
status = default_print_insn (cd, pc, info);
|
||||
}
|
||||
|
||||
@ -557,6 +814,24 @@ mep_cgen_print_operand (CGEN_CPU_DESC cd,
|
||||
case MEP_OPERAND_CRNX64 :
|
||||
print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_crnx, 0|(1<<CGEN_OPERAND_VIRTUAL));
|
||||
break;
|
||||
case MEP_OPERAND_CROC :
|
||||
print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u7, 0);
|
||||
break;
|
||||
case MEP_OPERAND_CROP :
|
||||
print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u23, 0);
|
||||
break;
|
||||
case MEP_OPERAND_CRPC :
|
||||
print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u26, 0);
|
||||
break;
|
||||
case MEP_OPERAND_CRPP :
|
||||
print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u18, 0);
|
||||
break;
|
||||
case MEP_OPERAND_CRQC :
|
||||
print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u21, 0);
|
||||
break;
|
||||
case MEP_OPERAND_CRQP :
|
||||
print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u13, 0);
|
||||
break;
|
||||
case MEP_OPERAND_CSRN :
|
||||
print_keyword (cd, info, & mep_cgen_opval_h_csr, fields->f_csrn, 0|(1<<CGEN_OPERAND_VIRTUAL));
|
||||
break;
|
||||
@ -578,6 +853,90 @@ mep_cgen_print_operand (CGEN_CPU_DESC cd,
|
||||
case MEP_OPERAND_HI :
|
||||
print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
|
||||
break;
|
||||
case MEP_OPERAND_IMM16P0 :
|
||||
print_normal (cd, info, fields->f_ivc2_imm16p0, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P12 :
|
||||
print_normal (cd, info, fields->f_ivc2_3u12, 0, pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P25 :
|
||||
print_normal (cd, info, fields->f_ivc2_3u25, 0, pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P4 :
|
||||
print_normal (cd, info, fields->f_ivc2_3u4, 0, pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P5 :
|
||||
print_normal (cd, info, fields->f_ivc2_3u5, 0, pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P9 :
|
||||
print_normal (cd, info, fields->f_ivc2_3u9, 0, pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_IMM4P10 :
|
||||
print_normal (cd, info, fields->f_ivc2_4u10, 0, pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_IMM4P4 :
|
||||
print_normal (cd, info, fields->f_ivc2_4u4, 0, pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_IMM4P8 :
|
||||
print_normal (cd, info, fields->f_ivc2_4u8, 0, pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P23 :
|
||||
print_normal (cd, info, fields->f_ivc2_5u23, 0, pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P3 :
|
||||
print_normal (cd, info, fields->f_ivc2_5u3, 0, pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P7 :
|
||||
print_normal (cd, info, fields->f_ivc2_5u7, 0, pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P8 :
|
||||
print_normal (cd, info, fields->f_ivc2_5u8, 0, pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_IMM6P2 :
|
||||
print_normal (cd, info, fields->f_ivc2_6u2, 0, pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_IMM6P6 :
|
||||
print_normal (cd, info, fields->f_ivc2_6u6, 0, pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_IMM8P0 :
|
||||
print_normal (cd, info, fields->f_ivc2_8u0, 0, pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_IMM8P20 :
|
||||
print_normal (cd, info, fields->f_ivc2_8u20, 0, pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_IMM8P4 :
|
||||
print_normal (cd, info, fields->f_ivc2_8u4, 0, pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_2 :
|
||||
print_normal (cd, info, fields->f_ivc2_2u0, 0, pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_3 :
|
||||
print_normal (cd, info, fields->f_ivc2_3u0, 0, pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_4 :
|
||||
print_normal (cd, info, fields->f_ivc2_4u0, 0, pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_5 :
|
||||
print_normal (cd, info, fields->f_ivc2_5u0, 0, pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_6_1 :
|
||||
print_normal (cd, info, fields->f_ivc2_1u6, 0, pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_6_2 :
|
||||
print_normal (cd, info, fields->f_ivc2_2u6, 0, pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_6_3 :
|
||||
print_normal (cd, info, fields->f_ivc2_3u6, 0, pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_IVC2CCRN :
|
||||
print_keyword (cd, info, & mep_cgen_opval_h_ccr, fields->f_ivc2_ccrn, 0|(1<<CGEN_OPERAND_VIRTUAL));
|
||||
break;
|
||||
case MEP_OPERAND_IVC2CRN :
|
||||
print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_crnx, 0|(1<<CGEN_OPERAND_VIRTUAL));
|
||||
break;
|
||||
case MEP_OPERAND_IVC2RM :
|
||||
print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_ivc2_crm, 0);
|
||||
break;
|
||||
case MEP_OPERAND_LO :
|
||||
print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
|
||||
break;
|
||||
@ -689,12 +1048,21 @@ mep_cgen_print_operand (CGEN_CPU_DESC cd,
|
||||
case MEP_OPERAND_SIMM16 :
|
||||
print_normal (cd, info, fields->f_16s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_SIMM16P0 :
|
||||
print_normal (cd, info, fields->f_ivc2_simm16p0, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_SIMM6 :
|
||||
print_normal (cd, info, fields->f_6s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_SIMM8 :
|
||||
print_normal (cd, info, fields->f_8s8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW), pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_SIMM8P0 :
|
||||
print_normal (cd, info, fields->f_ivc2_8s0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_SIMM8P4 :
|
||||
print_normal (cd, info, fields->f_ivc2_8s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
|
||||
break;
|
||||
case MEP_OPERAND_SP :
|
||||
print_keyword (cd, info, & mep_cgen_opval_h_gpr, 0, 0);
|
||||
break;
|
||||
|
@ -736,6 +736,24 @@ mep_cgen_insert_operand (CGEN_CPU_DESC cd,
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case MEP_OPERAND_CROC :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_5u7, 0, 0, 7, 5, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_CROP :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_5u23, 0, 0, 23, 5, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_CRPC :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_5u26, 0, 0, 26, 5, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_CRPP :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_5u18, 0, 0, 18, 5, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_CRQC :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_5u21, 0, 0, 21, 5, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_CRQP :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_5u13, 0, 0, 13, 5, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_CSRN :
|
||||
{
|
||||
{
|
||||
@ -774,6 +792,123 @@ mep_cgen_insert_operand (CGEN_CPU_DESC cd,
|
||||
break;
|
||||
case MEP_OPERAND_HI :
|
||||
break;
|
||||
case MEP_OPERAND_IMM16P0 :
|
||||
{
|
||||
{
|
||||
FLD (f_ivc2_8u0) = ((((unsigned int) (FLD (f_ivc2_imm16p0)) >> (8))) & (255));
|
||||
FLD (f_ivc2_8u20) = ((FLD (f_ivc2_imm16p0)) & (255));
|
||||
}
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_8u0, 0, 0, 0, 8, 32, total_length, buffer);
|
||||
if (errmsg)
|
||||
break;
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_8u20, 0, 0, 20, 8, 32, total_length, buffer);
|
||||
if (errmsg)
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P12 :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_3u12, 0, 0, 12, 3, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P25 :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_3u25, 0, 0, 25, 3, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P4 :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_3u4, 0, 0, 4, 3, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P5 :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_3u5, 0, 0, 5, 3, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P9 :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_3u9, 0, 0, 9, 3, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_IMM4P10 :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_4u10, 0, 0, 10, 4, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_IMM4P4 :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_4u4, 0, 0, 4, 4, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_IMM4P8 :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_4u8, 0, 0, 8, 4, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P23 :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_5u23, 0, 0, 23, 5, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P3 :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_5u3, 0, 0, 3, 5, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P7 :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_5u7, 0, 0, 7, 5, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P8 :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_5u8, 0, 0, 8, 5, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_IMM6P2 :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_6u2, 0, 0, 2, 6, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_IMM6P6 :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_6u6, 0, 0, 6, 6, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_IMM8P0 :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_8u0, 0, 0, 0, 8, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_IMM8P20 :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_8u20, 0, 0, 20, 8, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_IMM8P4 :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_8u4, 0, 0, 4, 8, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_2 :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_2u0, 0, 0, 0, 2, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_3 :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_3u0, 0, 0, 0, 3, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_4 :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_4u0, 0, 0, 0, 4, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_5 :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_5u0, 0, 0, 0, 5, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_6_1 :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_1u6, 0, 0, 6, 1, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_6_2 :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_2u6, 0, 0, 6, 2, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_6_3 :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_3u6, 0, 0, 6, 3, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_IVC2CCRN :
|
||||
{
|
||||
{
|
||||
FLD (f_ivc2_ccrn_h2) = ((((unsigned int) (FLD (f_ivc2_ccrn)) >> (4))) & (3));
|
||||
FLD (f_ivc2_ccrn_lo) = ((FLD (f_ivc2_ccrn)) & (15));
|
||||
}
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_ccrn_h2, 0, 0, 20, 2, 32, total_length, buffer);
|
||||
if (errmsg)
|
||||
break;
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_ccrn_lo, 0, 0, 0, 4, 32, total_length, buffer);
|
||||
if (errmsg)
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case MEP_OPERAND_IVC2CRN :
|
||||
{
|
||||
{
|
||||
FLD (f_ivc2_ccrn_h1) = ((((unsigned int) (FLD (f_ivc2_crnx)) >> (4))) & (1));
|
||||
FLD (f_ivc2_ccrn_lo) = ((FLD (f_ivc2_crnx)) & (15));
|
||||
}
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_ccrn_h1, 0, 0, 20, 1, 32, total_length, buffer);
|
||||
if (errmsg)
|
||||
break;
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_ccrn_lo, 0, 0, 0, 4, 32, total_length, buffer);
|
||||
if (errmsg)
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case MEP_OPERAND_IVC2RM :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_crm, 0, 0, 4, 4, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_LO :
|
||||
break;
|
||||
case MEP_OPERAND_LP :
|
||||
@ -908,12 +1043,32 @@ mep_cgen_insert_operand (CGEN_CPU_DESC cd,
|
||||
case MEP_OPERAND_SIMM16 :
|
||||
errmsg = insert_normal (cd, fields->f_16s16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_SIMM16P0 :
|
||||
{
|
||||
{
|
||||
FLD (f_ivc2_8u0) = ((((unsigned int) (FLD (f_ivc2_simm16p0)) >> (8))) & (255));
|
||||
FLD (f_ivc2_8u20) = ((FLD (f_ivc2_simm16p0)) & (255));
|
||||
}
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_8u0, 0, 0, 0, 8, 32, total_length, buffer);
|
||||
if (errmsg)
|
||||
break;
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_8u20, 0, 0, 20, 8, 32, total_length, buffer);
|
||||
if (errmsg)
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case MEP_OPERAND_SIMM6 :
|
||||
errmsg = insert_normal (cd, fields->f_6s8, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 6, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_SIMM8 :
|
||||
errmsg = insert_normal (cd, fields->f_8s8, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_SIMM8P0 :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_8s0, 0|(1<<CGEN_IFLD_SIGNED), 0, 0, 8, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_SIMM8P4 :
|
||||
errmsg = insert_normal (cd, fields->f_ivc2_8s4, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 32, total_length, buffer);
|
||||
break;
|
||||
case MEP_OPERAND_SP :
|
||||
break;
|
||||
case MEP_OPERAND_SPR :
|
||||
@ -1158,6 +1313,24 @@ mep_cgen_extract_operand (CGEN_CPU_DESC cd,
|
||||
FLD (f_crnx) = ((((FLD (f_crnx_hi)) << (4))) | (FLD (f_crnx_lo)));
|
||||
}
|
||||
break;
|
||||
case MEP_OPERAND_CROC :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 5, 32, total_length, pc, & fields->f_ivc2_5u7);
|
||||
break;
|
||||
case MEP_OPERAND_CROP :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 5, 32, total_length, pc, & fields->f_ivc2_5u23);
|
||||
break;
|
||||
case MEP_OPERAND_CRPC :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 5, 32, total_length, pc, & fields->f_ivc2_5u26);
|
||||
break;
|
||||
case MEP_OPERAND_CRPP :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 18, 5, 32, total_length, pc, & fields->f_ivc2_5u18);
|
||||
break;
|
||||
case MEP_OPERAND_CRQC :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 21, 5, 32, total_length, pc, & fields->f_ivc2_5u21);
|
||||
break;
|
||||
case MEP_OPERAND_CRQP :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 5, 32, total_length, pc, & fields->f_ivc2_5u13);
|
||||
break;
|
||||
case MEP_OPERAND_CSRN :
|
||||
{
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & fields->f_csrn_hi);
|
||||
@ -1186,6 +1359,110 @@ mep_cgen_extract_operand (CGEN_CPU_DESC cd,
|
||||
break;
|
||||
case MEP_OPERAND_HI :
|
||||
break;
|
||||
case MEP_OPERAND_IMM16P0 :
|
||||
{
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 0, 8, 32, total_length, pc, & fields->f_ivc2_8u0);
|
||||
if (length <= 0) break;
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 8, 32, total_length, pc, & fields->f_ivc2_8u20);
|
||||
if (length <= 0) break;
|
||||
{
|
||||
FLD (f_ivc2_imm16p0) = ((FLD (f_ivc2_8u20)) | (((FLD (f_ivc2_8u0)) << (8))));
|
||||
}
|
||||
}
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P12 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_ivc2_3u12);
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P25 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 3, 32, total_length, pc, & fields->f_ivc2_3u25);
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P4 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 3, 32, total_length, pc, & fields->f_ivc2_3u4);
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P5 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_ivc2_3u5);
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P9 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_ivc2_3u9);
|
||||
break;
|
||||
case MEP_OPERAND_IMM4P10 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 4, 32, total_length, pc, & fields->f_ivc2_4u10);
|
||||
break;
|
||||
case MEP_OPERAND_IMM4P4 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_ivc2_4u4);
|
||||
break;
|
||||
case MEP_OPERAND_IMM4P8 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_ivc2_4u8);
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P23 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 5, 32, total_length, pc, & fields->f_ivc2_5u23);
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P3 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 3, 5, 32, total_length, pc, & fields->f_ivc2_5u3);
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P7 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 5, 32, total_length, pc, & fields->f_ivc2_5u7);
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P8 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 5, 32, total_length, pc, & fields->f_ivc2_5u8);
|
||||
break;
|
||||
case MEP_OPERAND_IMM6P2 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 6, 32, total_length, pc, & fields->f_ivc2_6u2);
|
||||
break;
|
||||
case MEP_OPERAND_IMM6P6 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 6, 32, total_length, pc, & fields->f_ivc2_6u6);
|
||||
break;
|
||||
case MEP_OPERAND_IMM8P0 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 0, 8, 32, total_length, pc, & fields->f_ivc2_8u0);
|
||||
break;
|
||||
case MEP_OPERAND_IMM8P20 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 8, 32, total_length, pc, & fields->f_ivc2_8u20);
|
||||
break;
|
||||
case MEP_OPERAND_IMM8P4 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 8, 32, total_length, pc, & fields->f_ivc2_8u4);
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_2 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 0, 2, 32, total_length, pc, & fields->f_ivc2_2u0);
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_3 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 0, 3, 32, total_length, pc, & fields->f_ivc2_3u0);
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_4 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 0, 4, 32, total_length, pc, & fields->f_ivc2_4u0);
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_5 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 0, 5, 32, total_length, pc, & fields->f_ivc2_5u0);
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_6_1 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 1, 32, total_length, pc, & fields->f_ivc2_1u6);
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_6_2 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 2, 32, total_length, pc, & fields->f_ivc2_2u6);
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_6_3 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 3, 32, total_length, pc, & fields->f_ivc2_3u6);
|
||||
break;
|
||||
case MEP_OPERAND_IVC2CCRN :
|
||||
{
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 2, 32, total_length, pc, & fields->f_ivc2_ccrn_h2);
|
||||
if (length <= 0) break;
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 0, 4, 32, total_length, pc, & fields->f_ivc2_ccrn_lo);
|
||||
if (length <= 0) break;
|
||||
FLD (f_ivc2_ccrn) = ((((FLD (f_ivc2_ccrn_h2)) << (4))) | (FLD (f_ivc2_ccrn_lo)));
|
||||
}
|
||||
break;
|
||||
case MEP_OPERAND_IVC2CRN :
|
||||
{
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 1, 32, total_length, pc, & fields->f_ivc2_ccrn_h1);
|
||||
if (length <= 0) break;
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 0, 4, 32, total_length, pc, & fields->f_ivc2_ccrn_lo);
|
||||
if (length <= 0) break;
|
||||
FLD (f_ivc2_crnx) = ((((FLD (f_ivc2_ccrn_h1)) << (4))) | (FLD (f_ivc2_ccrn_lo)));
|
||||
}
|
||||
break;
|
||||
case MEP_OPERAND_IVC2RM :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_ivc2_crm);
|
||||
break;
|
||||
case MEP_OPERAND_LO :
|
||||
break;
|
||||
case MEP_OPERAND_LP :
|
||||
@ -1312,12 +1589,29 @@ mep_cgen_extract_operand (CGEN_CPU_DESC cd,
|
||||
case MEP_OPERAND_SIMM16 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_16s16);
|
||||
break;
|
||||
case MEP_OPERAND_SIMM16P0 :
|
||||
{
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 0, 8, 32, total_length, pc, & fields->f_ivc2_8u0);
|
||||
if (length <= 0) break;
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 8, 32, total_length, pc, & fields->f_ivc2_8u20);
|
||||
if (length <= 0) break;
|
||||
{
|
||||
FLD (f_ivc2_simm16p0) = ((FLD (f_ivc2_8u20)) | (((FLD (f_ivc2_8u0)) << (8))));
|
||||
}
|
||||
}
|
||||
break;
|
||||
case MEP_OPERAND_SIMM6 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 6, 32, total_length, pc, & fields->f_6s8);
|
||||
break;
|
||||
case MEP_OPERAND_SIMM8 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, pc, & fields->f_8s8);
|
||||
break;
|
||||
case MEP_OPERAND_SIMM8P0 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 0, 8, 32, total_length, pc, & fields->f_ivc2_8s0);
|
||||
break;
|
||||
case MEP_OPERAND_SIMM8P4 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 32, total_length, pc, & fields->f_ivc2_8s4);
|
||||
break;
|
||||
case MEP_OPERAND_SP :
|
||||
break;
|
||||
case MEP_OPERAND_SPR :
|
||||
@ -1480,6 +1774,24 @@ mep_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
case MEP_OPERAND_CRNX64 :
|
||||
value = fields->f_crnx;
|
||||
break;
|
||||
case MEP_OPERAND_CROC :
|
||||
value = fields->f_ivc2_5u7;
|
||||
break;
|
||||
case MEP_OPERAND_CROP :
|
||||
value = fields->f_ivc2_5u23;
|
||||
break;
|
||||
case MEP_OPERAND_CRPC :
|
||||
value = fields->f_ivc2_5u26;
|
||||
break;
|
||||
case MEP_OPERAND_CRPP :
|
||||
value = fields->f_ivc2_5u18;
|
||||
break;
|
||||
case MEP_OPERAND_CRQC :
|
||||
value = fields->f_ivc2_5u21;
|
||||
break;
|
||||
case MEP_OPERAND_CRQP :
|
||||
value = fields->f_ivc2_5u13;
|
||||
break;
|
||||
case MEP_OPERAND_CSRN :
|
||||
value = fields->f_csrn;
|
||||
break;
|
||||
@ -1501,6 +1813,90 @@ mep_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
case MEP_OPERAND_HI :
|
||||
value = 0;
|
||||
break;
|
||||
case MEP_OPERAND_IMM16P0 :
|
||||
value = fields->f_ivc2_imm16p0;
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P12 :
|
||||
value = fields->f_ivc2_3u12;
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P25 :
|
||||
value = fields->f_ivc2_3u25;
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P4 :
|
||||
value = fields->f_ivc2_3u4;
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P5 :
|
||||
value = fields->f_ivc2_3u5;
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P9 :
|
||||
value = fields->f_ivc2_3u9;
|
||||
break;
|
||||
case MEP_OPERAND_IMM4P10 :
|
||||
value = fields->f_ivc2_4u10;
|
||||
break;
|
||||
case MEP_OPERAND_IMM4P4 :
|
||||
value = fields->f_ivc2_4u4;
|
||||
break;
|
||||
case MEP_OPERAND_IMM4P8 :
|
||||
value = fields->f_ivc2_4u8;
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P23 :
|
||||
value = fields->f_ivc2_5u23;
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P3 :
|
||||
value = fields->f_ivc2_5u3;
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P7 :
|
||||
value = fields->f_ivc2_5u7;
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P8 :
|
||||
value = fields->f_ivc2_5u8;
|
||||
break;
|
||||
case MEP_OPERAND_IMM6P2 :
|
||||
value = fields->f_ivc2_6u2;
|
||||
break;
|
||||
case MEP_OPERAND_IMM6P6 :
|
||||
value = fields->f_ivc2_6u6;
|
||||
break;
|
||||
case MEP_OPERAND_IMM8P0 :
|
||||
value = fields->f_ivc2_8u0;
|
||||
break;
|
||||
case MEP_OPERAND_IMM8P20 :
|
||||
value = fields->f_ivc2_8u20;
|
||||
break;
|
||||
case MEP_OPERAND_IMM8P4 :
|
||||
value = fields->f_ivc2_8u4;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_2 :
|
||||
value = fields->f_ivc2_2u0;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_3 :
|
||||
value = fields->f_ivc2_3u0;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_4 :
|
||||
value = fields->f_ivc2_4u0;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_5 :
|
||||
value = fields->f_ivc2_5u0;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_6_1 :
|
||||
value = fields->f_ivc2_1u6;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_6_2 :
|
||||
value = fields->f_ivc2_2u6;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_6_3 :
|
||||
value = fields->f_ivc2_3u6;
|
||||
break;
|
||||
case MEP_OPERAND_IVC2CCRN :
|
||||
value = fields->f_ivc2_ccrn;
|
||||
break;
|
||||
case MEP_OPERAND_IVC2CRN :
|
||||
value = fields->f_ivc2_crnx;
|
||||
break;
|
||||
case MEP_OPERAND_IVC2RM :
|
||||
value = fields->f_ivc2_crm;
|
||||
break;
|
||||
case MEP_OPERAND_LO :
|
||||
value = 0;
|
||||
break;
|
||||
@ -1612,12 +2008,21 @@ mep_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
case MEP_OPERAND_SIMM16 :
|
||||
value = fields->f_16s16;
|
||||
break;
|
||||
case MEP_OPERAND_SIMM16P0 :
|
||||
value = fields->f_ivc2_simm16p0;
|
||||
break;
|
||||
case MEP_OPERAND_SIMM6 :
|
||||
value = fields->f_6s8;
|
||||
break;
|
||||
case MEP_OPERAND_SIMM8 :
|
||||
value = fields->f_8s8;
|
||||
break;
|
||||
case MEP_OPERAND_SIMM8P0 :
|
||||
value = fields->f_ivc2_8s0;
|
||||
break;
|
||||
case MEP_OPERAND_SIMM8P4 :
|
||||
value = fields->f_ivc2_8s4;
|
||||
break;
|
||||
case MEP_OPERAND_SP :
|
||||
value = 0;
|
||||
break;
|
||||
@ -1746,6 +2151,24 @@ mep_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
case MEP_OPERAND_CRNX64 :
|
||||
value = fields->f_crnx;
|
||||
break;
|
||||
case MEP_OPERAND_CROC :
|
||||
value = fields->f_ivc2_5u7;
|
||||
break;
|
||||
case MEP_OPERAND_CROP :
|
||||
value = fields->f_ivc2_5u23;
|
||||
break;
|
||||
case MEP_OPERAND_CRPC :
|
||||
value = fields->f_ivc2_5u26;
|
||||
break;
|
||||
case MEP_OPERAND_CRPP :
|
||||
value = fields->f_ivc2_5u18;
|
||||
break;
|
||||
case MEP_OPERAND_CRQC :
|
||||
value = fields->f_ivc2_5u21;
|
||||
break;
|
||||
case MEP_OPERAND_CRQP :
|
||||
value = fields->f_ivc2_5u13;
|
||||
break;
|
||||
case MEP_OPERAND_CSRN :
|
||||
value = fields->f_csrn;
|
||||
break;
|
||||
@ -1767,6 +2190,90 @@ mep_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
case MEP_OPERAND_HI :
|
||||
value = 0;
|
||||
break;
|
||||
case MEP_OPERAND_IMM16P0 :
|
||||
value = fields->f_ivc2_imm16p0;
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P12 :
|
||||
value = fields->f_ivc2_3u12;
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P25 :
|
||||
value = fields->f_ivc2_3u25;
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P4 :
|
||||
value = fields->f_ivc2_3u4;
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P5 :
|
||||
value = fields->f_ivc2_3u5;
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P9 :
|
||||
value = fields->f_ivc2_3u9;
|
||||
break;
|
||||
case MEP_OPERAND_IMM4P10 :
|
||||
value = fields->f_ivc2_4u10;
|
||||
break;
|
||||
case MEP_OPERAND_IMM4P4 :
|
||||
value = fields->f_ivc2_4u4;
|
||||
break;
|
||||
case MEP_OPERAND_IMM4P8 :
|
||||
value = fields->f_ivc2_4u8;
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P23 :
|
||||
value = fields->f_ivc2_5u23;
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P3 :
|
||||
value = fields->f_ivc2_5u3;
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P7 :
|
||||
value = fields->f_ivc2_5u7;
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P8 :
|
||||
value = fields->f_ivc2_5u8;
|
||||
break;
|
||||
case MEP_OPERAND_IMM6P2 :
|
||||
value = fields->f_ivc2_6u2;
|
||||
break;
|
||||
case MEP_OPERAND_IMM6P6 :
|
||||
value = fields->f_ivc2_6u6;
|
||||
break;
|
||||
case MEP_OPERAND_IMM8P0 :
|
||||
value = fields->f_ivc2_8u0;
|
||||
break;
|
||||
case MEP_OPERAND_IMM8P20 :
|
||||
value = fields->f_ivc2_8u20;
|
||||
break;
|
||||
case MEP_OPERAND_IMM8P4 :
|
||||
value = fields->f_ivc2_8u4;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_2 :
|
||||
value = fields->f_ivc2_2u0;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_3 :
|
||||
value = fields->f_ivc2_3u0;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_4 :
|
||||
value = fields->f_ivc2_4u0;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_5 :
|
||||
value = fields->f_ivc2_5u0;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_6_1 :
|
||||
value = fields->f_ivc2_1u6;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_6_2 :
|
||||
value = fields->f_ivc2_2u6;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_6_3 :
|
||||
value = fields->f_ivc2_3u6;
|
||||
break;
|
||||
case MEP_OPERAND_IVC2CCRN :
|
||||
value = fields->f_ivc2_ccrn;
|
||||
break;
|
||||
case MEP_OPERAND_IVC2CRN :
|
||||
value = fields->f_ivc2_crnx;
|
||||
break;
|
||||
case MEP_OPERAND_IVC2RM :
|
||||
value = fields->f_ivc2_crm;
|
||||
break;
|
||||
case MEP_OPERAND_LO :
|
||||
value = 0;
|
||||
break;
|
||||
@ -1878,12 +2385,21 @@ mep_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
case MEP_OPERAND_SIMM16 :
|
||||
value = fields->f_16s16;
|
||||
break;
|
||||
case MEP_OPERAND_SIMM16P0 :
|
||||
value = fields->f_ivc2_simm16p0;
|
||||
break;
|
||||
case MEP_OPERAND_SIMM6 :
|
||||
value = fields->f_6s8;
|
||||
break;
|
||||
case MEP_OPERAND_SIMM8 :
|
||||
value = fields->f_8s8;
|
||||
break;
|
||||
case MEP_OPERAND_SIMM8P0 :
|
||||
value = fields->f_ivc2_8s0;
|
||||
break;
|
||||
case MEP_OPERAND_SIMM8P4 :
|
||||
value = fields->f_ivc2_8s4;
|
||||
break;
|
||||
case MEP_OPERAND_SP :
|
||||
value = 0;
|
||||
break;
|
||||
@ -2018,6 +2534,24 @@ mep_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
case MEP_OPERAND_CRNX64 :
|
||||
fields->f_crnx = value;
|
||||
break;
|
||||
case MEP_OPERAND_CROC :
|
||||
fields->f_ivc2_5u7 = value;
|
||||
break;
|
||||
case MEP_OPERAND_CROP :
|
||||
fields->f_ivc2_5u23 = value;
|
||||
break;
|
||||
case MEP_OPERAND_CRPC :
|
||||
fields->f_ivc2_5u26 = value;
|
||||
break;
|
||||
case MEP_OPERAND_CRPP :
|
||||
fields->f_ivc2_5u18 = value;
|
||||
break;
|
||||
case MEP_OPERAND_CRQC :
|
||||
fields->f_ivc2_5u21 = value;
|
||||
break;
|
||||
case MEP_OPERAND_CRQP :
|
||||
fields->f_ivc2_5u13 = value;
|
||||
break;
|
||||
case MEP_OPERAND_CSRN :
|
||||
fields->f_csrn = value;
|
||||
break;
|
||||
@ -2034,6 +2568,90 @@ mep_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
break;
|
||||
case MEP_OPERAND_HI :
|
||||
break;
|
||||
case MEP_OPERAND_IMM16P0 :
|
||||
fields->f_ivc2_imm16p0 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P12 :
|
||||
fields->f_ivc2_3u12 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P25 :
|
||||
fields->f_ivc2_3u25 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P4 :
|
||||
fields->f_ivc2_3u4 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P5 :
|
||||
fields->f_ivc2_3u5 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P9 :
|
||||
fields->f_ivc2_3u9 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM4P10 :
|
||||
fields->f_ivc2_4u10 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM4P4 :
|
||||
fields->f_ivc2_4u4 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM4P8 :
|
||||
fields->f_ivc2_4u8 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P23 :
|
||||
fields->f_ivc2_5u23 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P3 :
|
||||
fields->f_ivc2_5u3 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P7 :
|
||||
fields->f_ivc2_5u7 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P8 :
|
||||
fields->f_ivc2_5u8 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM6P2 :
|
||||
fields->f_ivc2_6u2 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM6P6 :
|
||||
fields->f_ivc2_6u6 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM8P0 :
|
||||
fields->f_ivc2_8u0 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM8P20 :
|
||||
fields->f_ivc2_8u20 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM8P4 :
|
||||
fields->f_ivc2_8u4 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_2 :
|
||||
fields->f_ivc2_2u0 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_3 :
|
||||
fields->f_ivc2_3u0 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_4 :
|
||||
fields->f_ivc2_4u0 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_5 :
|
||||
fields->f_ivc2_5u0 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_6_1 :
|
||||
fields->f_ivc2_1u6 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_6_2 :
|
||||
fields->f_ivc2_2u6 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_6_3 :
|
||||
fields->f_ivc2_3u6 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IVC2CCRN :
|
||||
fields->f_ivc2_ccrn = value;
|
||||
break;
|
||||
case MEP_OPERAND_IVC2CRN :
|
||||
fields->f_ivc2_crnx = value;
|
||||
break;
|
||||
case MEP_OPERAND_IVC2RM :
|
||||
fields->f_ivc2_crm = value;
|
||||
break;
|
||||
case MEP_OPERAND_LO :
|
||||
break;
|
||||
case MEP_OPERAND_LP :
|
||||
@ -2133,12 +2751,21 @@ mep_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
case MEP_OPERAND_SIMM16 :
|
||||
fields->f_16s16 = value;
|
||||
break;
|
||||
case MEP_OPERAND_SIMM16P0 :
|
||||
fields->f_ivc2_simm16p0 = value;
|
||||
break;
|
||||
case MEP_OPERAND_SIMM6 :
|
||||
fields->f_6s8 = value;
|
||||
break;
|
||||
case MEP_OPERAND_SIMM8 :
|
||||
fields->f_8s8 = value;
|
||||
break;
|
||||
case MEP_OPERAND_SIMM8P0 :
|
||||
fields->f_ivc2_8s0 = value;
|
||||
break;
|
||||
case MEP_OPERAND_SIMM8P4 :
|
||||
fields->f_ivc2_8s4 = value;
|
||||
break;
|
||||
case MEP_OPERAND_SP :
|
||||
break;
|
||||
case MEP_OPERAND_SPR :
|
||||
@ -2258,6 +2885,24 @@ mep_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
case MEP_OPERAND_CRNX64 :
|
||||
fields->f_crnx = value;
|
||||
break;
|
||||
case MEP_OPERAND_CROC :
|
||||
fields->f_ivc2_5u7 = value;
|
||||
break;
|
||||
case MEP_OPERAND_CROP :
|
||||
fields->f_ivc2_5u23 = value;
|
||||
break;
|
||||
case MEP_OPERAND_CRPC :
|
||||
fields->f_ivc2_5u26 = value;
|
||||
break;
|
||||
case MEP_OPERAND_CRPP :
|
||||
fields->f_ivc2_5u18 = value;
|
||||
break;
|
||||
case MEP_OPERAND_CRQC :
|
||||
fields->f_ivc2_5u21 = value;
|
||||
break;
|
||||
case MEP_OPERAND_CRQP :
|
||||
fields->f_ivc2_5u13 = value;
|
||||
break;
|
||||
case MEP_OPERAND_CSRN :
|
||||
fields->f_csrn = value;
|
||||
break;
|
||||
@ -2274,6 +2919,90 @@ mep_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
break;
|
||||
case MEP_OPERAND_HI :
|
||||
break;
|
||||
case MEP_OPERAND_IMM16P0 :
|
||||
fields->f_ivc2_imm16p0 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P12 :
|
||||
fields->f_ivc2_3u12 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P25 :
|
||||
fields->f_ivc2_3u25 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P4 :
|
||||
fields->f_ivc2_3u4 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P5 :
|
||||
fields->f_ivc2_3u5 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM3P9 :
|
||||
fields->f_ivc2_3u9 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM4P10 :
|
||||
fields->f_ivc2_4u10 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM4P4 :
|
||||
fields->f_ivc2_4u4 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM4P8 :
|
||||
fields->f_ivc2_4u8 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P23 :
|
||||
fields->f_ivc2_5u23 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P3 :
|
||||
fields->f_ivc2_5u3 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P7 :
|
||||
fields->f_ivc2_5u7 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM5P8 :
|
||||
fields->f_ivc2_5u8 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM6P2 :
|
||||
fields->f_ivc2_6u2 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM6P6 :
|
||||
fields->f_ivc2_6u6 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM8P0 :
|
||||
fields->f_ivc2_8u0 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM8P20 :
|
||||
fields->f_ivc2_8u20 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IMM8P4 :
|
||||
fields->f_ivc2_8u4 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_2 :
|
||||
fields->f_ivc2_2u0 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_3 :
|
||||
fields->f_ivc2_3u0 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_4 :
|
||||
fields->f_ivc2_4u0 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_0_5 :
|
||||
fields->f_ivc2_5u0 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_6_1 :
|
||||
fields->f_ivc2_1u6 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_6_2 :
|
||||
fields->f_ivc2_2u6 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IVC_X_6_3 :
|
||||
fields->f_ivc2_3u6 = value;
|
||||
break;
|
||||
case MEP_OPERAND_IVC2CCRN :
|
||||
fields->f_ivc2_ccrn = value;
|
||||
break;
|
||||
case MEP_OPERAND_IVC2CRN :
|
||||
fields->f_ivc2_crnx = value;
|
||||
break;
|
||||
case MEP_OPERAND_IVC2RM :
|
||||
fields->f_ivc2_crm = value;
|
||||
break;
|
||||
case MEP_OPERAND_LO :
|
||||
break;
|
||||
case MEP_OPERAND_LP :
|
||||
@ -2373,12 +3102,21 @@ mep_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
case MEP_OPERAND_SIMM16 :
|
||||
fields->f_16s16 = value;
|
||||
break;
|
||||
case MEP_OPERAND_SIMM16P0 :
|
||||
fields->f_ivc2_simm16p0 = value;
|
||||
break;
|
||||
case MEP_OPERAND_SIMM6 :
|
||||
fields->f_6s8 = value;
|
||||
break;
|
||||
case MEP_OPERAND_SIMM8 :
|
||||
fields->f_8s8 = value;
|
||||
break;
|
||||
case MEP_OPERAND_SIMM8P0 :
|
||||
fields->f_ivc2_8s0 = value;
|
||||
break;
|
||||
case MEP_OPERAND_SIMM8P4 :
|
||||
fields->f_ivc2_8s4 = value;
|
||||
break;
|
||||
case MEP_OPERAND_SP :
|
||||
break;
|
||||
case MEP_OPERAND_SPR :
|
||||
|
4290
opcodes/mep-opc.c
4290
opcodes/mep-opc.c
File diff suppressed because it is too large
Load Diff
@ -71,6 +71,10 @@ extern CGEN_ATTR_VALUE_BITSET_TYPE mep_cop_isa (void);
|
||||
#define MEP_COP_ISA (mep_config_map[mep_config_index].cop_isa)
|
||||
#define MEP_CORE_ISA (mep_config_map[mep_config_index].core_isa)
|
||||
|
||||
/* begin-cop-ip-supported-defines */
|
||||
#define MEP_IVC2_SUPPORTED 1
|
||||
/* end-cop-ip-supported-defines */
|
||||
|
||||
extern int mep_insn_supported_by_isa (const CGEN_INSN *, CGEN_ATTR_VALUE_BITSET_TYPE *);
|
||||
|
||||
/* A mask for all ISAs executed by the core. */
|
||||
@ -152,14 +156,186 @@ typedef enum cgen_insn_type {
|
||||
, MEP_INSN_RI_8, MEP_INSN_RI_9, MEP_INSN_RI_10, MEP_INSN_RI_11
|
||||
, MEP_INSN_RI_12, MEP_INSN_RI_13, MEP_INSN_RI_14, MEP_INSN_RI_15
|
||||
, MEP_INSN_RI_17, MEP_INSN_RI_20, MEP_INSN_RI_21, MEP_INSN_RI_22
|
||||
, MEP_INSN_RI_23, MEP_INSN_RI_26
|
||||
, MEP_INSN_RI_23, MEP_INSN_RI_26, MEP_INSN_CMOV_CRN_RM, MEP_INSN_CMOV_RN_CRM
|
||||
, MEP_INSN_CMOVC_CCRN_RM, MEP_INSN_CMOVC_RN_CCRM, MEP_INSN_CMOVH_CRN_RM, MEP_INSN_CMOVH_RN_CRM
|
||||
, MEP_INSN_CMOV_CRN_RM_P0, MEP_INSN_CMOV_RN_CRM_P0, MEP_INSN_CMOVC_CCRN_RM_P0, MEP_INSN_CMOVC_RN_CCRM_P0
|
||||
, MEP_INSN_CMOVH_CRN_RM_P0, MEP_INSN_CMOVH_RN_CRM_P0, MEP_INSN_CPADD3_B_C3, MEP_INSN_CPADD3_H_C3
|
||||
, MEP_INSN_CPADD3_W_C3, MEP_INSN_CDADD3_C3, MEP_INSN_CPSUB3_B_C3, MEP_INSN_CPSUB3_H_C3
|
||||
, MEP_INSN_CPSUB3_W_C3, MEP_INSN_CDSUB3_C3, MEP_INSN_CPAND3_C3, MEP_INSN_CPOR3_C3
|
||||
, MEP_INSN_CPNOR3_C3, MEP_INSN_CPXOR3_C3, MEP_INSN_CPSEL_C3, MEP_INSN_CPFSFTBI_C3
|
||||
, MEP_INSN_CPFSFTBS0_C3, MEP_INSN_CPFSFTBS1_C3, MEP_INSN_CPUNPACKU_B_C3, MEP_INSN_CPUNPACKU_H_C3
|
||||
, MEP_INSN_CPUNPACKU_W_C3, MEP_INSN_CPUNPACKL_B_C3, MEP_INSN_CPUNPACKL_H_C3, MEP_INSN_CPUNPACKL_W_C3
|
||||
, MEP_INSN_CPPACKU_B_C3, MEP_INSN_CPPACK_B_C3, MEP_INSN_CPPACK_H_C3, MEP_INSN_CPSRL3_B_C3
|
||||
, MEP_INSN_CPSSRL3_B_C3, MEP_INSN_CPSRL3_H_C3, MEP_INSN_CPSSRL3_H_C3, MEP_INSN_CPSRL3_W_C3
|
||||
, MEP_INSN_CPSSRL3_W_C3, MEP_INSN_CDSRL3_C3, MEP_INSN_CPSRA3_B_C3, MEP_INSN_CPSSRA3_B_C3
|
||||
, MEP_INSN_CPSRA3_H_C3, MEP_INSN_CPSSRA3_H_C3, MEP_INSN_CPSRA3_W_C3, MEP_INSN_CPSSRA3_W_C3
|
||||
, MEP_INSN_CDSRA3_C3, MEP_INSN_CPSLL3_B_C3, MEP_INSN_CPSSLL3_B_C3, MEP_INSN_CPSLL3_H_C3
|
||||
, MEP_INSN_CPSSLL3_H_C3, MEP_INSN_CPSLL3_W_C3, MEP_INSN_CPSSLL3_W_C3, MEP_INSN_CDSLL3_C3
|
||||
, MEP_INSN_CPSLA3_H_C3, MEP_INSN_CPSLA3_W_C3, MEP_INSN_CPSADD3_H_C3, MEP_INSN_CPSADD3_W_C3
|
||||
, MEP_INSN_CPSSUB3_H_C3, MEP_INSN_CPSSUB3_W_C3, MEP_INSN_CPEXTUADDU3_B_C3, MEP_INSN_CPEXTUADD3_B_C3
|
||||
, MEP_INSN_CPEXTLADDU3_B_C3, MEP_INSN_CPEXTLADD3_B_C3, MEP_INSN_CPEXTUSUBU3_B_C3, MEP_INSN_CPEXTUSUB3_B_C3
|
||||
, MEP_INSN_CPEXTLSUBU3_B_C3, MEP_INSN_CPEXTLSUB3_B_C3, MEP_INSN_CPAVEU3_B_C3, MEP_INSN_CPAVE3_B_C3
|
||||
, MEP_INSN_CPAVE3_H_C3, MEP_INSN_CPAVE3_W_C3, MEP_INSN_CPADDSRU3_B_C3, MEP_INSN_CPADDSR3_B_C3
|
||||
, MEP_INSN_CPADDSR3_H_C3, MEP_INSN_CPADDSR3_W_C3, MEP_INSN_CPABSU3_B_C3, MEP_INSN_CPABS3_B_C3
|
||||
, MEP_INSN_CPABS3_H_C3, MEP_INSN_CPMAXU3_B_C3, MEP_INSN_CPMAX3_B_C3, MEP_INSN_CPMAX3_H_C3
|
||||
, MEP_INSN_CPMAXU3_W_C3, MEP_INSN_CPMAX3_W_C3, MEP_INSN_CPMINU3_B_C3, MEP_INSN_CPMIN3_B_C3
|
||||
, MEP_INSN_CPMIN3_H_C3, MEP_INSN_CPMINU3_W_C3, MEP_INSN_CPMIN3_W_C3, MEP_INSN_CPMOVFRCSAR0_C3
|
||||
, MEP_INSN_CPMOVFRCSAR1_C3, MEP_INSN_CPMOVFRCC_C3, MEP_INSN_CPMOVTOCSAR0_C3, MEP_INSN_CPMOVTOCSAR1_C3
|
||||
, MEP_INSN_CPMOVTOCC_C3, MEP_INSN_CPMOV_C3, MEP_INSN_CPABSZ_B_C3, MEP_INSN_CPABSZ_H_C3
|
||||
, MEP_INSN_CPABSZ_W_C3, MEP_INSN_CPLDZ_H_C3, MEP_INSN_CPLDZ_W_C3, MEP_INSN_CPNORM_H_C3
|
||||
, MEP_INSN_CPNORM_W_C3, MEP_INSN_CPHADDU_B_C3, MEP_INSN_CPHADD_B_C3, MEP_INSN_CPHADD_H_C3
|
||||
, MEP_INSN_CPHADD_W_C3, MEP_INSN_CPCCADD_B_C3, MEP_INSN_CPBCAST_B_C3, MEP_INSN_CPBCAST_H_C3
|
||||
, MEP_INSN_CPBCAST_W_C3, MEP_INSN_CPEXTUU_B_C3, MEP_INSN_CPEXTU_B_C3, MEP_INSN_CPEXTUU_H_C3
|
||||
, MEP_INSN_CPEXTU_H_C3, MEP_INSN_CPEXTLU_B_C3, MEP_INSN_CPEXTL_B_C3, MEP_INSN_CPEXTLU_H_C3
|
||||
, MEP_INSN_CPEXTL_H_C3, MEP_INSN_CPCASTUB_H_C3, MEP_INSN_CPCASTB_H_C3, MEP_INSN_CPCASTUB_W_C3
|
||||
, MEP_INSN_CPCASTB_W_C3, MEP_INSN_CPCASTUH_W_C3, MEP_INSN_CPCASTH_W_C3, MEP_INSN_CDCASTUW_C3
|
||||
, MEP_INSN_CDCASTW_C3, MEP_INSN_CPCMPEQZ_B_C3, MEP_INSN_CPCMPEQ_B_C3, MEP_INSN_CPCMPEQ_H_C3
|
||||
, MEP_INSN_CPCMPEQ_W_C3, MEP_INSN_CPCMPNE_B_C3, MEP_INSN_CPCMPNE_H_C3, MEP_INSN_CPCMPNE_W_C3
|
||||
, MEP_INSN_CPCMPGTU_B_C3, MEP_INSN_CPCMPGT_B_C3, MEP_INSN_CPCMPGT_H_C3, MEP_INSN_CPCMPGTU_W_C3
|
||||
, MEP_INSN_CPCMPGT_W_C3, MEP_INSN_CPCMPGEU_B_C3, MEP_INSN_CPCMPGE_B_C3, MEP_INSN_CPCMPGE_H_C3
|
||||
, MEP_INSN_CPCMPGEU_W_C3, MEP_INSN_CPCMPGE_W_C3, MEP_INSN_CPACMPEQ_B_C3, MEP_INSN_CPACMPEQ_H_C3
|
||||
, MEP_INSN_CPACMPEQ_W_C3, MEP_INSN_CPACMPNE_B_C3, MEP_INSN_CPACMPNE_H_C3, MEP_INSN_CPACMPNE_W_C3
|
||||
, MEP_INSN_CPACMPGTU_B_C3, MEP_INSN_CPACMPGT_B_C3, MEP_INSN_CPACMPGT_H_C3, MEP_INSN_CPACMPGTU_W_C3
|
||||
, MEP_INSN_CPACMPGT_W_C3, MEP_INSN_CPACMPGEU_B_C3, MEP_INSN_CPACMPGE_B_C3, MEP_INSN_CPACMPGE_H_C3
|
||||
, MEP_INSN_CPACMPGEU_W_C3, MEP_INSN_CPACMPGE_W_C3, MEP_INSN_CPOCMPEQ_B_C3, MEP_INSN_CPOCMPEQ_H_C3
|
||||
, MEP_INSN_CPOCMPEQ_W_C3, MEP_INSN_CPOCMPNE_B_C3, MEP_INSN_CPOCMPNE_H_C3, MEP_INSN_CPOCMPNE_W_C3
|
||||
, MEP_INSN_CPOCMPGTU_B_C3, MEP_INSN_CPOCMPGT_B_C3, MEP_INSN_CPOCMPGT_H_C3, MEP_INSN_CPOCMPGTU_W_C3
|
||||
, MEP_INSN_CPOCMPGT_W_C3, MEP_INSN_CPOCMPGEU_B_C3, MEP_INSN_CPOCMPGE_B_C3, MEP_INSN_CPOCMPGE_H_C3
|
||||
, MEP_INSN_CPOCMPGEU_W_C3, MEP_INSN_CPOCMPGE_W_C3, MEP_INSN_CPSRLI3_B_C3, MEP_INSN_CPSRLI3_H_C3
|
||||
, MEP_INSN_CPSRLI3_W_C3, MEP_INSN_CDSRLI3_C3, MEP_INSN_CPSRAI3_B_C3, MEP_INSN_CPSRAI3_H_C3
|
||||
, MEP_INSN_CPSRAI3_W_C3, MEP_INSN_CDSRAI3_C3, MEP_INSN_CPSLLI3_B_C3, MEP_INSN_CPSLLI3_H_C3
|
||||
, MEP_INSN_CPSLLI3_W_C3, MEP_INSN_CDSLLI3_C3, MEP_INSN_CPSLAI3_H_C3, MEP_INSN_CPSLAI3_W_C3
|
||||
, MEP_INSN_CPCLIPIU3_W_C3, MEP_INSN_CPCLIPI3_W_C3, MEP_INSN_CDCLIPIU3_C3, MEP_INSN_CDCLIPI3_C3
|
||||
, MEP_INSN_CPMOVI_B_C3, MEP_INSN_CPMOVIU_H_C3, MEP_INSN_CPMOVI_H_C3, MEP_INSN_CPMOVIU_W_C3
|
||||
, MEP_INSN_CPMOVI_W_C3, MEP_INSN_CDMOVIU_C3, MEP_INSN_CDMOVI_C3, MEP_INSN_CPADDA1U_B_C3
|
||||
, MEP_INSN_CPADDA1_B_C3, MEP_INSN_CPADDUA1_H_C3, MEP_INSN_CPADDLA1_H_C3, MEP_INSN_CPADDACA1U_B_C3
|
||||
, MEP_INSN_CPADDACA1_B_C3, MEP_INSN_CPADDACUA1_H_C3, MEP_INSN_CPADDACLA1_H_C3, MEP_INSN_CPSUBA1U_B_C3
|
||||
, MEP_INSN_CPSUBA1_B_C3, MEP_INSN_CPSUBUA1_H_C3, MEP_INSN_CPSUBLA1_H_C3, MEP_INSN_CPSUBACA1U_B_C3
|
||||
, MEP_INSN_CPSUBACA1_B_C3, MEP_INSN_CPSUBACUA1_H_C3, MEP_INSN_CPSUBACLA1_H_C3, MEP_INSN_CPABSA1U_B_C3
|
||||
, MEP_INSN_CPABSA1_B_C3, MEP_INSN_CPABSUA1_H_C3, MEP_INSN_CPABSLA1_H_C3, MEP_INSN_CPSADA1U_B_C3
|
||||
, MEP_INSN_CPSADA1_B_C3, MEP_INSN_CPSADUA1_H_C3, MEP_INSN_CPSADLA1_H_C3, MEP_INSN_CPSETA1_H_C3
|
||||
, MEP_INSN_CPSETUA1_W_C3, MEP_INSN_CPSETLA1_W_C3, MEP_INSN_CPMOVA1_B_C3, MEP_INSN_CPMOVUA1_H_C3
|
||||
, MEP_INSN_CPMOVLA1_H_C3, MEP_INSN_CPMOVUUA1_W_C3, MEP_INSN_CPMOVULA1_W_C3, MEP_INSN_CPMOVLUA1_W_C3
|
||||
, MEP_INSN_CPMOVLLA1_W_C3, MEP_INSN_CPPACKA1U_B_C3, MEP_INSN_CPPACKA1_B_C3, MEP_INSN_CPPACKUA1_H_C3
|
||||
, MEP_INSN_CPPACKLA1_H_C3, MEP_INSN_CPPACKUA1_W_C3, MEP_INSN_CPPACKLA1_W_C3, MEP_INSN_CPMOVHUA1_W_C3
|
||||
, MEP_INSN_CPMOVHLA1_W_C3, MEP_INSN_CPSRLA1_C3, MEP_INSN_CPSRAA1_C3, MEP_INSN_CPSLLA1_C3
|
||||
, MEP_INSN_CPSRLIA1_P1, MEP_INSN_CPSRAIA1_P1, MEP_INSN_CPSLLIA1_P1, MEP_INSN_CPSSQA1U_B_C3
|
||||
, MEP_INSN_CPSSQA1_B_C3, MEP_INSN_CPSSDA1U_B_C3, MEP_INSN_CPSSDA1_B_C3, MEP_INSN_CPMULA1U_B_C3
|
||||
, MEP_INSN_CPMULA1_B_C3, MEP_INSN_CPMULUA1_H_C3, MEP_INSN_CPMULLA1_H_C3, MEP_INSN_CPMULUA1U_W_C3
|
||||
, MEP_INSN_CPMULLA1U_W_C3, MEP_INSN_CPMULUA1_W_C3, MEP_INSN_CPMULLA1_W_C3, MEP_INSN_CPMADA1U_B_C3
|
||||
, MEP_INSN_CPMADA1_B_C3, MEP_INSN_CPMADUA1_H_C3, MEP_INSN_CPMADLA1_H_C3, MEP_INSN_CPMADUA1U_W_C3
|
||||
, MEP_INSN_CPMADLA1U_W_C3, MEP_INSN_CPMADUA1_W_C3, MEP_INSN_CPMADLA1_W_C3, MEP_INSN_CPMSBUA1_H_C3
|
||||
, MEP_INSN_CPMSBLA1_H_C3, MEP_INSN_CPMSBUA1U_W_C3, MEP_INSN_CPMSBLA1U_W_C3, MEP_INSN_CPMSBUA1_W_C3
|
||||
, MEP_INSN_CPMSBLA1_W_C3, MEP_INSN_CPSMADUA1_H_C3, MEP_INSN_CPSMADLA1_H_C3, MEP_INSN_CPSMADUA1_W_C3
|
||||
, MEP_INSN_CPSMADLA1_W_C3, MEP_INSN_CPSMSBUA1_H_C3, MEP_INSN_CPSMSBLA1_H_C3, MEP_INSN_CPSMSBUA1_W_C3
|
||||
, MEP_INSN_CPSMSBLA1_W_C3, MEP_INSN_CPMULSLUA1_H_C3, MEP_INSN_CPMULSLLA1_H_C3, MEP_INSN_CPMULSLUA1_W_C3
|
||||
, MEP_INSN_CPMULSLLA1_W_C3, MEP_INSN_CPSMADSLUA1_H_C3, MEP_INSN_CPSMADSLLA1_H_C3, MEP_INSN_CPSMADSLUA1_W_C3
|
||||
, MEP_INSN_CPSMADSLLA1_W_C3, MEP_INSN_CPSMSBSLUA1_H_C3, MEP_INSN_CPSMSBSLLA1_H_C3, MEP_INSN_CPSMSBSLUA1_W_C3
|
||||
, MEP_INSN_CPSMSBSLLA1_W_C3, MEP_INSN_C0NOP_P0_P0S, MEP_INSN_CPADD3_B_P0S_P1, MEP_INSN_CPADD3_H_P0S_P1
|
||||
, MEP_INSN_CPADD3_W_P0S_P1, MEP_INSN_CPUNPACKU_B_P0S_P1, MEP_INSN_CPUNPACKU_H_P0S_P1, MEP_INSN_CPUNPACKU_W_P0S_P1
|
||||
, MEP_INSN_CPUNPACKL_B_P0S_P1, MEP_INSN_CPUNPACKL_H_P0S_P1, MEP_INSN_CPUNPACKL_W_P0S_P1, MEP_INSN_CPSEL_P0S_P1
|
||||
, MEP_INSN_CPFSFTBS0_P0S_P1, MEP_INSN_CPFSFTBS1_P0S_P1, MEP_INSN_CPMOV_P0S_P1, MEP_INSN_CPABSZ_B_P0S_P1
|
||||
, MEP_INSN_CPABSZ_H_P0S_P1, MEP_INSN_CPABSZ_W_P0S_P1, MEP_INSN_CPLDZ_H_P0S_P1, MEP_INSN_CPLDZ_W_P0S_P1
|
||||
, MEP_INSN_CPNORM_H_P0S_P1, MEP_INSN_CPNORM_W_P0S_P1, MEP_INSN_CPHADDU_B_P0S_P1, MEP_INSN_CPHADD_B_P0S_P1
|
||||
, MEP_INSN_CPHADD_H_P0S_P1, MEP_INSN_CPHADD_W_P0S_P1, MEP_INSN_CPCCADD_B_P0S_P1, MEP_INSN_CPBCAST_B_P0S_P1
|
||||
, MEP_INSN_CPBCAST_H_P0S_P1, MEP_INSN_CPBCAST_W_P0S_P1, MEP_INSN_CPEXTUU_B_P0S_P1, MEP_INSN_CPEXTU_B_P0S_P1
|
||||
, MEP_INSN_CPEXTUU_H_P0S_P1, MEP_INSN_CPEXTU_H_P0S_P1, MEP_INSN_CPEXTLU_B_P0S_P1, MEP_INSN_CPEXTL_B_P0S_P1
|
||||
, MEP_INSN_CPEXTLU_H_P0S_P1, MEP_INSN_CPEXTL_H_P0S_P1, MEP_INSN_CPCASTUB_H_P0S_P1, MEP_INSN_CPCASTB_H_P0S_P1
|
||||
, MEP_INSN_CPCASTUB_W_P0S_P1, MEP_INSN_CPCASTB_W_P0S_P1, MEP_INSN_CPCASTUH_W_P0S_P1, MEP_INSN_CPCASTH_W_P0S_P1
|
||||
, MEP_INSN_CDCASTUW_P0S_P1, MEP_INSN_CDCASTW_P0S_P1, MEP_INSN_CPMOVFRCSAR0_P0S_P1, MEP_INSN_CPMOVFRCSAR1_P0S_P1
|
||||
, MEP_INSN_CPMOVFRCC_P0S_P1, MEP_INSN_CPMOVTOCSAR0_P0S_P1, MEP_INSN_CPMOVTOCSAR1_P0S_P1, MEP_INSN_CPMOVTOCC_P0S_P1
|
||||
, MEP_INSN_CPCMPEQZ_B_P0S_P1, MEP_INSN_CPCMPEQ_B_P0S_P1, MEP_INSN_CPCMPEQ_H_P0S_P1, MEP_INSN_CPCMPEQ_W_P0S_P1
|
||||
, MEP_INSN_CPCMPNE_B_P0S_P1, MEP_INSN_CPCMPNE_H_P0S_P1, MEP_INSN_CPCMPNE_W_P0S_P1, MEP_INSN_CPCMPGTU_B_P0S_P1
|
||||
, MEP_INSN_CPCMPGT_B_P0S_P1, MEP_INSN_CPCMPGT_H_P0S_P1, MEP_INSN_CPCMPGTU_W_P0S_P1, MEP_INSN_CPCMPGT_W_P0S_P1
|
||||
, MEP_INSN_CPCMPGEU_B_P0S_P1, MEP_INSN_CPCMPGE_B_P0S_P1, MEP_INSN_CPCMPGE_H_P0S_P1, MEP_INSN_CPCMPGEU_W_P0S_P1
|
||||
, MEP_INSN_CPCMPGE_W_P0S_P1, MEP_INSN_CPADDA0U_B_P0S, MEP_INSN_CPADDA0_B_P0S, MEP_INSN_CPADDUA0_H_P0S
|
||||
, MEP_INSN_CPADDLA0_H_P0S, MEP_INSN_CPADDACA0U_B_P0S, MEP_INSN_CPADDACA0_B_P0S, MEP_INSN_CPADDACUA0_H_P0S
|
||||
, MEP_INSN_CPADDACLA0_H_P0S, MEP_INSN_CPSUBA0U_B_P0S, MEP_INSN_CPSUBA0_B_P0S, MEP_INSN_CPSUBUA0_H_P0S
|
||||
, MEP_INSN_CPSUBLA0_H_P0S, MEP_INSN_CPSUBACA0U_B_P0S, MEP_INSN_CPSUBACA0_B_P0S, MEP_INSN_CPSUBACUA0_H_P0S
|
||||
, MEP_INSN_CPSUBACLA0_H_P0S, MEP_INSN_CPABSA0U_B_P0S, MEP_INSN_CPABSA0_B_P0S, MEP_INSN_CPABSUA0_H_P0S
|
||||
, MEP_INSN_CPABSLA0_H_P0S, MEP_INSN_CPSADA0U_B_P0S, MEP_INSN_CPSADA0_B_P0S, MEP_INSN_CPSADUA0_H_P0S
|
||||
, MEP_INSN_CPSADLA0_H_P0S, MEP_INSN_CPSETA0_H_P0S, MEP_INSN_CPSETUA0_W_P0S, MEP_INSN_CPSETLA0_W_P0S
|
||||
, MEP_INSN_CPMOVA0_B_P0S, MEP_INSN_CPMOVUA0_H_P0S, MEP_INSN_CPMOVLA0_H_P0S, MEP_INSN_CPMOVUUA0_W_P0S
|
||||
, MEP_INSN_CPMOVULA0_W_P0S, MEP_INSN_CPMOVLUA0_W_P0S, MEP_INSN_CPMOVLLA0_W_P0S, MEP_INSN_CPPACKA0U_B_P0S
|
||||
, MEP_INSN_CPPACKA0_B_P0S, MEP_INSN_CPPACKUA0_H_P0S, MEP_INSN_CPPACKLA0_H_P0S, MEP_INSN_CPPACKUA0_W_P0S
|
||||
, MEP_INSN_CPPACKLA0_W_P0S, MEP_INSN_CPMOVHUA0_W_P0S, MEP_INSN_CPMOVHLA0_W_P0S, MEP_INSN_CPACSUMA0_P0S
|
||||
, MEP_INSN_CPACCPA0_P0S, MEP_INSN_CPSRLA0_P0S, MEP_INSN_CPSRAA0_P0S, MEP_INSN_CPSLLA0_P0S
|
||||
, MEP_INSN_CPSRLIA0_P0S, MEP_INSN_CPSRAIA0_P0S, MEP_INSN_CPSLLIA0_P0S, MEP_INSN_CPFSFTBA0S0U_B_P0S
|
||||
, MEP_INSN_CPFSFTBA0S0_B_P0S, MEP_INSN_CPFSFTBUA0S0_H_P0S, MEP_INSN_CPFSFTBLA0S0_H_P0S, MEP_INSN_CPFACA0S0U_B_P0S
|
||||
, MEP_INSN_CPFACA0S0_B_P0S, MEP_INSN_CPFACUA0S0_H_P0S, MEP_INSN_CPFACLA0S0_H_P0S, MEP_INSN_CPFSFTBA0S1U_B_P0S
|
||||
, MEP_INSN_CPFSFTBA0S1_B_P0S, MEP_INSN_CPFSFTBUA0S1_H_P0S, MEP_INSN_CPFSFTBLA0S1_H_P0S, MEP_INSN_CPFACA0S1U_B_P0S
|
||||
, MEP_INSN_CPFACA0S1_B_P0S, MEP_INSN_CPFACUA0S1_H_P0S, MEP_INSN_CPFACLA0S1_H_P0S, MEP_INSN_CPFSFTBI_P0_P1
|
||||
, MEP_INSN_CPACMPEQ_B_P0_P1, MEP_INSN_CPACMPEQ_H_P0_P1, MEP_INSN_CPACMPEQ_W_P0_P1, MEP_INSN_CPACMPNE_B_P0_P1
|
||||
, MEP_INSN_CPACMPNE_H_P0_P1, MEP_INSN_CPACMPNE_W_P0_P1, MEP_INSN_CPACMPGTU_B_P0_P1, MEP_INSN_CPACMPGT_B_P0_P1
|
||||
, MEP_INSN_CPACMPGT_H_P0_P1, MEP_INSN_CPACMPGTU_W_P0_P1, MEP_INSN_CPACMPGT_W_P0_P1, MEP_INSN_CPACMPGEU_B_P0_P1
|
||||
, MEP_INSN_CPACMPGE_B_P0_P1, MEP_INSN_CPACMPGE_H_P0_P1, MEP_INSN_CPACMPGEU_W_P0_P1, MEP_INSN_CPACMPGE_W_P0_P1
|
||||
, MEP_INSN_CPOCMPEQ_B_P0_P1, MEP_INSN_CPOCMPEQ_H_P0_P1, MEP_INSN_CPOCMPEQ_W_P0_P1, MEP_INSN_CPOCMPNE_B_P0_P1
|
||||
, MEP_INSN_CPOCMPNE_H_P0_P1, MEP_INSN_CPOCMPNE_W_P0_P1, MEP_INSN_CPOCMPGTU_B_P0_P1, MEP_INSN_CPOCMPGT_B_P0_P1
|
||||
, MEP_INSN_CPOCMPGT_H_P0_P1, MEP_INSN_CPOCMPGTU_W_P0_P1, MEP_INSN_CPOCMPGT_W_P0_P1, MEP_INSN_CPOCMPGEU_B_P0_P1
|
||||
, MEP_INSN_CPOCMPGE_B_P0_P1, MEP_INSN_CPOCMPGE_H_P0_P1, MEP_INSN_CPOCMPGEU_W_P0_P1, MEP_INSN_CPOCMPGE_W_P0_P1
|
||||
, MEP_INSN_CDADD3_P0_P1, MEP_INSN_CPSUB3_B_P0_P1, MEP_INSN_CPSUB3_H_P0_P1, MEP_INSN_CPSUB3_W_P0_P1
|
||||
, MEP_INSN_CDSUB3_P0_P1, MEP_INSN_CPSADD3_H_P0_P1, MEP_INSN_CPSADD3_W_P0_P1, MEP_INSN_CPSSUB3_H_P0_P1
|
||||
, MEP_INSN_CPSSUB3_W_P0_P1, MEP_INSN_CPEXTUADDU3_B_P0_P1, MEP_INSN_CPEXTUADD3_B_P0_P1, MEP_INSN_CPEXTLADDU3_B_P0_P1
|
||||
, MEP_INSN_CPEXTLADD3_B_P0_P1, MEP_INSN_CPEXTUSUBU3_B_P0_P1, MEP_INSN_CPEXTUSUB3_B_P0_P1, MEP_INSN_CPEXTLSUBU3_B_P0_P1
|
||||
, MEP_INSN_CPEXTLSUB3_B_P0_P1, MEP_INSN_CPAVEU3_B_P0_P1, MEP_INSN_CPAVE3_B_P0_P1, MEP_INSN_CPAVE3_H_P0_P1
|
||||
, MEP_INSN_CPAVE3_W_P0_P1, MEP_INSN_CPADDSRU3_B_P0_P1, MEP_INSN_CPADDSR3_B_P0_P1, MEP_INSN_CPADDSR3_H_P0_P1
|
||||
, MEP_INSN_CPADDSR3_W_P0_P1, MEP_INSN_CPABSU3_B_P0_P1, MEP_INSN_CPABS3_B_P0_P1, MEP_INSN_CPABS3_H_P0_P1
|
||||
, MEP_INSN_CPAND3_P0_P1, MEP_INSN_CPOR3_P0_P1, MEP_INSN_CPNOR3_P0_P1, MEP_INSN_CPXOR3_P0_P1
|
||||
, MEP_INSN_CPPACKU_B_P0_P1, MEP_INSN_CPPACK_B_P0_P1, MEP_INSN_CPPACK_H_P0_P1, MEP_INSN_CPMAXU3_B_P0_P1
|
||||
, MEP_INSN_CPMAX3_B_P0_P1, MEP_INSN_CPMAX3_H_P0_P1, MEP_INSN_CPMAXU3_W_P0_P1, MEP_INSN_CPMAX3_W_P0_P1
|
||||
, MEP_INSN_CPMINU3_B_P0_P1, MEP_INSN_CPMIN3_B_P0_P1, MEP_INSN_CPMIN3_H_P0_P1, MEP_INSN_CPMINU3_W_P0_P1
|
||||
, MEP_INSN_CPMIN3_W_P0_P1, MEP_INSN_CPSRL3_B_P0_P1, MEP_INSN_CPSSRL3_B_P0_P1, MEP_INSN_CPSRL3_H_P0_P1
|
||||
, MEP_INSN_CPSSRL3_H_P0_P1, MEP_INSN_CPSRL3_W_P0_P1, MEP_INSN_CPSSRL3_W_P0_P1, MEP_INSN_CDSRL3_P0_P1
|
||||
, MEP_INSN_CPSRA3_B_P0_P1, MEP_INSN_CPSSRA3_B_P0_P1, MEP_INSN_CPSRA3_H_P0_P1, MEP_INSN_CPSSRA3_H_P0_P1
|
||||
, MEP_INSN_CPSRA3_W_P0_P1, MEP_INSN_CPSSRA3_W_P0_P1, MEP_INSN_CDSRA3_P0_P1, MEP_INSN_CPSLL3_B_P0_P1
|
||||
, MEP_INSN_CPSSLL3_B_P0_P1, MEP_INSN_CPSLL3_H_P0_P1, MEP_INSN_CPSSLL3_H_P0_P1, MEP_INSN_CPSLL3_W_P0_P1
|
||||
, MEP_INSN_CPSSLL3_W_P0_P1, MEP_INSN_CDSLL3_P0_P1, MEP_INSN_CPSLA3_H_P0_P1, MEP_INSN_CPSLA3_W_P0_P1
|
||||
, MEP_INSN_CPSRLI3_B_P0_P1, MEP_INSN_CPSRLI3_H_P0_P1, MEP_INSN_CPSRLI3_W_P0_P1, MEP_INSN_CDSRLI3_P0_P1
|
||||
, MEP_INSN_CPSRAI3_B_P0_P1, MEP_INSN_CPSRAI3_H_P0_P1, MEP_INSN_CPSRAI3_W_P0_P1, MEP_INSN_CDSRAI3_P0_P1
|
||||
, MEP_INSN_CPSLLI3_B_P0_P1, MEP_INSN_CPSLLI3_H_P0_P1, MEP_INSN_CPSLLI3_W_P0_P1, MEP_INSN_CDSLLI3_P0_P1
|
||||
, MEP_INSN_CPSLAI3_H_P0_P1, MEP_INSN_CPSLAI3_W_P0_P1, MEP_INSN_CPCLIPIU3_W_P0_P1, MEP_INSN_CPCLIPI3_W_P0_P1
|
||||
, MEP_INSN_CDCLIPIU3_P0_P1, MEP_INSN_CDCLIPI3_P0_P1, MEP_INSN_CPMOVI_H_P0_P1, MEP_INSN_CPMOVIU_W_P0_P1
|
||||
, MEP_INSN_CPMOVI_W_P0_P1, MEP_INSN_CDMOVIU_P0_P1, MEP_INSN_CDMOVI_P0_P1, MEP_INSN_C1NOP_P1
|
||||
, MEP_INSN_CPADDA1U_B_P1, MEP_INSN_CPADDA1_B_P1, MEP_INSN_CPADDUA1_H_P1, MEP_INSN_CPADDLA1_H_P1
|
||||
, MEP_INSN_CPADDACA1U_B_P1, MEP_INSN_CPADDACA1_B_P1, MEP_INSN_CPADDACUA1_H_P1, MEP_INSN_CPADDACLA1_H_P1
|
||||
, MEP_INSN_CPSUBA1U_B_P1, MEP_INSN_CPSUBA1_B_P1, MEP_INSN_CPSUBUA1_H_P1, MEP_INSN_CPSUBLA1_H_P1
|
||||
, MEP_INSN_CPSUBACA1U_B_P1, MEP_INSN_CPSUBACA1_B_P1, MEP_INSN_CPSUBACUA1_H_P1, MEP_INSN_CPSUBACLA1_H_P1
|
||||
, MEP_INSN_CPABSA1U_B_P1, MEP_INSN_CPABSA1_B_P1, MEP_INSN_CPABSUA1_H_P1, MEP_INSN_CPABSLA1_H_P1
|
||||
, MEP_INSN_CPSADA1U_B_P1, MEP_INSN_CPSADA1_B_P1, MEP_INSN_CPSADUA1_H_P1, MEP_INSN_CPSADLA1_H_P1
|
||||
, MEP_INSN_CPSETA1_H_P1, MEP_INSN_CPSETUA1_W_P1, MEP_INSN_CPSETLA1_W_P1, MEP_INSN_CPMOVA1_B_P1
|
||||
, MEP_INSN_CPMOVUA1_H_P1, MEP_INSN_CPMOVLA1_H_P1, MEP_INSN_CPMOVUUA1_W_P1, MEP_INSN_CPMOVULA1_W_P1
|
||||
, MEP_INSN_CPMOVLUA1_W_P1, MEP_INSN_CPMOVLLA1_W_P1, MEP_INSN_CPPACKA1U_B_P1, MEP_INSN_CPPACKA1_B_P1
|
||||
, MEP_INSN_CPPACKUA1_H_P1, MEP_INSN_CPPACKLA1_H_P1, MEP_INSN_CPPACKUA1_W_P1, MEP_INSN_CPPACKLA1_W_P1
|
||||
, MEP_INSN_CPMOVHUA1_W_P1, MEP_INSN_CPMOVHLA1_W_P1, MEP_INSN_CPACSUMA1_P1, MEP_INSN_CPACCPA1_P1
|
||||
, MEP_INSN_CPACSWP_P1, MEP_INSN_CPSRLA1_P1, MEP_INSN_CPSRAA1_P1, MEP_INSN_CPSLLA1_P1
|
||||
, MEP_INSN_CPSRLIA1_1_P1, MEP_INSN_CPSRAIA1_1_P1, MEP_INSN_CPSLLIA1_1_P1, MEP_INSN_CPFMULIA1S0U_B_P1
|
||||
, MEP_INSN_CPFMULIA1S0_B_P1, MEP_INSN_CPFMULIUA1S0_H_P1, MEP_INSN_CPFMULILA1S0_H_P1, MEP_INSN_CPFMADIA1S0U_B_P1
|
||||
, MEP_INSN_CPFMADIA1S0_B_P1, MEP_INSN_CPFMADIUA1S0_H_P1, MEP_INSN_CPFMADILA1S0_H_P1, MEP_INSN_CPFMULIA1S1U_B_P1
|
||||
, MEP_INSN_CPFMULIA1S1_B_P1, MEP_INSN_CPFMULIUA1S1_H_P1, MEP_INSN_CPFMULILA1S1_H_P1, MEP_INSN_CPFMADIA1S1U_B_P1
|
||||
, MEP_INSN_CPFMADIA1S1_B_P1, MEP_INSN_CPFMADIUA1S1_H_P1, MEP_INSN_CPFMADILA1S1_H_P1, MEP_INSN_CPAMULIA1U_B_P1
|
||||
, MEP_INSN_CPAMULIA1_B_P1, MEP_INSN_CPAMULIUA1_H_P1, MEP_INSN_CPAMULILA1_H_P1, MEP_INSN_CPAMADIA1U_B_P1
|
||||
, MEP_INSN_CPAMADIA1_B_P1, MEP_INSN_CPAMADIUA1_H_P1, MEP_INSN_CPAMADILA1_H_P1, MEP_INSN_CPFMULIA1U_B_P1
|
||||
, MEP_INSN_CPFMULIA1_B_P1, MEP_INSN_CPFMULIUA1_H_P1, MEP_INSN_CPFMULILA1_H_P1, MEP_INSN_CPFMADIA1U_B_P1
|
||||
, MEP_INSN_CPFMADIA1_B_P1, MEP_INSN_CPFMADIUA1_H_P1, MEP_INSN_CPFMADILA1_H_P1, MEP_INSN_CPSSQA1U_B_P1
|
||||
, MEP_INSN_CPSSQA1_B_P1, MEP_INSN_CPSSDA1U_B_P1, MEP_INSN_CPSSDA1_B_P1, MEP_INSN_CPMULA1U_B_P1
|
||||
, MEP_INSN_CPMULA1_B_P1, MEP_INSN_CPMULUA1_H_P1, MEP_INSN_CPMULLA1_H_P1, MEP_INSN_CPMULUA1U_W_P1
|
||||
, MEP_INSN_CPMULLA1U_W_P1, MEP_INSN_CPMULUA1_W_P1, MEP_INSN_CPMULLA1_W_P1, MEP_INSN_CPMADA1U_B_P1
|
||||
, MEP_INSN_CPMADA1_B_P1, MEP_INSN_CPMADUA1_H_P1, MEP_INSN_CPMADLA1_H_P1, MEP_INSN_CPMADUA1U_W_P1
|
||||
, MEP_INSN_CPMADLA1U_W_P1, MEP_INSN_CPMADUA1_W_P1, MEP_INSN_CPMADLA1_W_P1, MEP_INSN_CPMSBUA1_H_P1
|
||||
, MEP_INSN_CPMSBLA1_H_P1, MEP_INSN_CPMSBUA1U_W_P1, MEP_INSN_CPMSBLA1U_W_P1, MEP_INSN_CPMSBUA1_W_P1
|
||||
, MEP_INSN_CPMSBLA1_W_P1, MEP_INSN_CPSMADUA1_H_P1, MEP_INSN_CPSMADLA1_H_P1, MEP_INSN_CPSMADUA1_W_P1
|
||||
, MEP_INSN_CPSMADLA1_W_P1, MEP_INSN_CPSMSBUA1_H_P1, MEP_INSN_CPSMSBLA1_H_P1, MEP_INSN_CPSMSBUA1_W_P1
|
||||
, MEP_INSN_CPSMSBLA1_W_P1, MEP_INSN_CPMULSLUA1_H_P1, MEP_INSN_CPMULSLLA1_H_P1, MEP_INSN_CPMULSLUA1_W_P1
|
||||
, MEP_INSN_CPMULSLLA1_W_P1, MEP_INSN_CPSMADSLUA1_H_P1, MEP_INSN_CPSMADSLLA1_H_P1, MEP_INSN_CPSMADSLUA1_W_P1
|
||||
, MEP_INSN_CPSMADSLLA1_W_P1, MEP_INSN_CPSMSBSLUA1_H_P1, MEP_INSN_CPSMSBSLLA1_H_P1, MEP_INSN_CPSMSBSLUA1_W_P1
|
||||
, MEP_INSN_CPSMSBSLLA1_W_P1
|
||||
} CGEN_INSN_TYPE;
|
||||
|
||||
/* Index of `invalid' insn place holder. */
|
||||
#define CGEN_INSN_INVALID MEP_INSN_INVALID
|
||||
|
||||
/* Total number of insns in table. */
|
||||
#define MAX_INSNS ((int) MEP_INSN_RI_26 + 1)
|
||||
#define MAX_INSNS ((int) MEP_INSN_CPSMSBSLLA1_W_P1 + 1)
|
||||
|
||||
/* This struct records data prior to insertion or after extraction. */
|
||||
struct cgen_fields
|
||||
@ -266,6 +442,58 @@ struct cgen_fields
|
||||
long f_c5_16u16;
|
||||
long f_c5_rmuimm20;
|
||||
long f_c5_rnmuimm24;
|
||||
long f_ivc2_2u4;
|
||||
long f_ivc2_3u4;
|
||||
long f_ivc2_8u4;
|
||||
long f_ivc2_8s4;
|
||||
long f_ivc2_1u6;
|
||||
long f_ivc2_2u6;
|
||||
long f_ivc2_3u6;
|
||||
long f_ivc2_6u6;
|
||||
long f_ivc2_5u7;
|
||||
long f_ivc2_4u8;
|
||||
long f_ivc2_3u9;
|
||||
long f_ivc2_5u16;
|
||||
long f_ivc2_5u21;
|
||||
long f_ivc2_5u26;
|
||||
long f_ivc2_1u31;
|
||||
long f_ivc2_4u16;
|
||||
long f_ivc2_4u20;
|
||||
long f_ivc2_4u24;
|
||||
long f_ivc2_4u28;
|
||||
long f_ivc2_2u0;
|
||||
long f_ivc2_3u0;
|
||||
long f_ivc2_4u0;
|
||||
long f_ivc2_5u0;
|
||||
long f_ivc2_8u0;
|
||||
long f_ivc2_8s0;
|
||||
long f_ivc2_6u2;
|
||||
long f_ivc2_5u3;
|
||||
long f_ivc2_4u4;
|
||||
long f_ivc2_3u5;
|
||||
long f_ivc2_5u8;
|
||||
long f_ivc2_4u10;
|
||||
long f_ivc2_3u12;
|
||||
long f_ivc2_5u13;
|
||||
long f_ivc2_2u18;
|
||||
long f_ivc2_5u18;
|
||||
long f_ivc2_8u20;
|
||||
long f_ivc2_8s20;
|
||||
long f_ivc2_5u23;
|
||||
long f_ivc2_2u23;
|
||||
long f_ivc2_3u25;
|
||||
long f_ivc2_imm16p0;
|
||||
long f_ivc2_simm16p0;
|
||||
long f_ivc2_crn;
|
||||
long f_ivc2_crm;
|
||||
long f_ivc2_ccrn_h1;
|
||||
long f_ivc2_ccrn_h2;
|
||||
long f_ivc2_ccrn_lo;
|
||||
long f_ivc2_cmov1;
|
||||
long f_ivc2_cmov2;
|
||||
long f_ivc2_cmov3;
|
||||
long f_ivc2_ccrn;
|
||||
long f_ivc2_crnx;
|
||||
};
|
||||
|
||||
#define CGEN_INIT_PARSE(od) \
|
||||
|
Loading…
Reference in New Issue
Block a user