Tighten the constraints for warning about NOPs for the MSP 430 ISA, so NOPs are only inserted/warned about when needed. Specifically: 430 and 430x ISA require a NOP after DINT. Only the 430x ISA requires NOP before EINT. Only the 430x ISA requires NOP after every EINT. CPU42 errata.
* config/tc-msp430.c (is_dint): New. (is_eint): New. (gen_nop): New. (warn_eint_nop): New. (warn_unsure_interrupt): New. (msp430_operands): Determine the effect MOV #N,SR insns have on interrupt state. Only emit NOP warnings for 430 ISA in certain situations. (msp430_md_end): Only warn about an EINT at the end of the file if NOP warnings are enabled. * testsuite/gas/msp430/bad.l: Adjust expected output for new warnings. * testsuite/gas/msp430/msp430.exp: Run new tests. * testsuite/gas/msp430/nop-dint-430.d: New. * testsuite/gas/msp430/nop-dint-430.l: New. * testsuite/gas/msp430/nop-dint-430x-ignore.d: New. * testsuite/gas/msp430/nop-dint-430x-silent.d: New. * testsuite/gas/msp430/nop-dint-430x.d: New. * testsuite/gas/msp430/nop-dint-430x.l: New. * testsuite/gas/msp430/nop-dint.s: New. * testsuite/gas/msp430/nop-eint-430.d: New. * testsuite/gas/msp430/nop-eint-430.l: New. * testsuite/gas/msp430/nop-eint-430x-ignore.d: New. * testsuite/gas/msp430/nop-eint-430x-silent.d: New. * testsuite/gas/msp430/nop-eint-430x.d: New. * testsuite/gas/msp430/nop-eint-430x.l: New. * testsuite/gas/msp430/nop-eint.s: New. * testsuite/gas/msp430/nop-int-430.d: New. * testsuite/gas/msp430/nop-int-430.l: New. * testsuite/gas/msp430/nop-int-430x-silent.d: New. * testsuite/gas/msp430/nop-int-430x.d: New. * testsuite/gas/msp430/nop-int-430x.l: New. * testsuite/gas/msp430/nop-int.s: New.
This commit is contained in:
Jozef Lawrynowicz
Nick Clifton
parent
4207142d6a
commit
35ba4bc019
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@ -1,3 +1,38 @@
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2018-11-27 Jozef Lawrynowicz <jozef.l@mittosystems.com>
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* config/tc-msp430.c (is_dint): New.
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(is_eint): New.
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(gen_nop): New.
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(warn_eint_nop): New.
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(warn_unsure_interrupt): New.
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(msp430_operands): Determine the effect MOV #N,SR insns have on
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interrupt state.
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Only emit NOP warnings for 430 ISA in certain situations.
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(msp430_md_end): Only warn about an EINT at the end of the file
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if NOP warnings are enabled.
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* testsuite/gas/msp430/bad.l: Adjust expected output for new warnings.
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* testsuite/gas/msp430/msp430.exp: Run new tests.
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* testsuite/gas/msp430/nop-dint-430.d: New.
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* testsuite/gas/msp430/nop-dint-430.l: New.
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* testsuite/gas/msp430/nop-dint-430x-ignore.d: New.
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* testsuite/gas/msp430/nop-dint-430x-silent.d: New.
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* testsuite/gas/msp430/nop-dint-430x.d: New.
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* testsuite/gas/msp430/nop-dint-430x.l: New.
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* testsuite/gas/msp430/nop-dint.s: New.
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* testsuite/gas/msp430/nop-eint-430.d: New.
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* testsuite/gas/msp430/nop-eint-430.l: New.
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* testsuite/gas/msp430/nop-eint-430x-ignore.d: New.
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* testsuite/gas/msp430/nop-eint-430x-silent.d: New.
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* testsuite/gas/msp430/nop-eint-430x.d: New.
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* testsuite/gas/msp430/nop-eint-430x.l: New.
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* testsuite/gas/msp430/nop-eint.s: New.
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* testsuite/gas/msp430/nop-int-430.d: New.
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* testsuite/gas/msp430/nop-int-430.l: New.
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* testsuite/gas/msp430/nop-int-430x-silent.d: New.
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* testsuite/gas/msp430/nop-int-430x.d: New.
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* testsuite/gas/msp430/nop-int-430x.l: New.
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* testsuite/gas/msp430/nop-int.s: New.
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2018-11-23 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* testsuite/gas/arm/bl-local-v4t.d: Remove
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@ -2495,6 +2495,79 @@ static signed int check_for_nop = 0;
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#define is_opcode(NAME) (strcmp (opcode->name, NAME) == 0)
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/* is_{e,d}int only check the explicit enabling/disabling of interrupts.
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For MOV insns, more sophisticated processing is needed to determine if they
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result in enabling/disabling interrupts. */
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#define is_dint(OPCODE, BIN) ((strcmp (OPCODE, "dint") == 0) \
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|| ((strcmp (OPCODE, "bic") == 0) \
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&& BIN == 0xc232) \
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|| ((strcmp (OPCODE, "clr") == 0) \
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&& BIN == 0x4302))
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#define is_eint(OPCODE, BIN) ((strcmp (OPCODE, "eint") == 0) \
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|| ((strcmp (OPCODE, "bis") == 0) \
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&& BIN == 0xd232))
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const char * const INSERT_NOP_BEFORE_EINT = "NOP inserted here, before an interrupt enable instruction";
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const char * const INSERT_NOP_AFTER_DINT = "NOP inserted here, after an interrupt disable instruction";
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const char * const INSERT_NOP_AFTER_EINT = "NOP inserted here, after an interrupt enable instruction";
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const char * const INSERT_NOP_BEFORE_UNKNOWN = "NOP inserted here, before this interrupt state change";
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const char * const INSERT_NOP_AFTER_UNKNOWN ="NOP inserted here, after the instruction that changed interrupt state";
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const char * const INSERT_NOP_AT_EOF = "NOP inserted after the interrupt state change at the end of the file";
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const char * const WARN_NOP_BEFORE_EINT = "a NOP might be needed here, before an interrupt enable instruction";
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const char * const WARN_NOP_AFTER_DINT = "a NOP might be needed here, after an interrupt disable instruction";
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const char * const WARN_NOP_AFTER_EINT = "a NOP might be needed here, after an interrupt enable instruction";
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const char * const WARN_NOP_BEFORE_UNKNOWN = "a NOP might be needed here, before this interrupt state change";
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const char * const WARN_NOP_AFTER_UNKNOWN = "a NOP might also be needed here, after the instruction that changed interrupt state";
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const char * const WARN_NOP_AT_EOF = "a NOP might be needed after the interrupt state change at the end of the file";
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static void
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gen_nop (void)
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{
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char *frag;
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frag = frag_more (2);
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bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag);
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dwarf2_emit_insn (2);
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}
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/* Insert/inform about adding a NOP if this insn enables interrupts. */
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static void
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warn_eint_nop (bfd_boolean prev_insn_is_nop, bfd_boolean prev_insn_is_dint)
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{
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if (prev_insn_is_nop
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/* Prevent double warning for DINT immediately before EINT. */
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|| prev_insn_is_dint
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/* 430 ISA does not require a NOP before EINT. */
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|| (! target_is_430x ()))
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return;
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if (gen_interrupt_nops)
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{
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gen_nop ();
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if (warn_interrupt_nops)
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as_warn (_(INSERT_NOP_BEFORE_EINT));
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}
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else if (warn_interrupt_nops)
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as_warn (_(WARN_NOP_BEFORE_EINT));
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}
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/* Use when unsure what effect the insn will have on the interrupt status,
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to insert/warn about adding a NOP before the current insn. */
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static void
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warn_unsure_interrupt (void)
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{
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/* Since this could enable or disable interrupts, need to add/warn about
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adding a NOP before and after this insn. */
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if (gen_interrupt_nops)
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{
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gen_nop ();
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if (warn_interrupt_nops)
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as_warn (_(INSERT_NOP_BEFORE_UNKNOWN));
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}
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else if (warn_interrupt_nops)
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as_warn (_(WARN_NOP_BEFORE_UNKNOWN));
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}
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/* Parse instruction operands.
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Return binary opcode. */
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@ -2519,6 +2592,12 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
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const char * error_message;
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static signed int repeat_count = 0;
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static bfd_boolean prev_insn_is_nop = FALSE;
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static bfd_boolean prev_insn_is_dint = FALSE;
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static bfd_boolean prev_insn_is_eint = FALSE;
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/* We might decide before the end of the function that the current insn is
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equivalent to DINT/EINT. */
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bfd_boolean this_insn_is_dint = FALSE;
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bfd_boolean this_insn_is_eint = FALSE;
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bfd_boolean fix_emitted;
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/* Opcode is the one from opcodes table
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@ -2654,29 +2733,69 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
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repeat_count = 0;
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}
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/* The previous instruction set this flag if it wants to check if this insn
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is a NOP. */
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if (check_for_nop)
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{
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if (! is_opcode ("nop"))
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{
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bfd_boolean doit = FALSE;
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do
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{
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switch (check_for_nop & - check_for_nop)
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{
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case NOP_CHECK_INTERRUPT:
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if (warn_interrupt_nops)
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/* NOP_CHECK_INTERRUPT rules:
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1. 430 and 430x ISA require a NOP after DINT.
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2. Only the 430x ISA requires NOP before EINT (this has
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been dealt with in the previous call to this function).
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3. Only the 430x ISA requires NOP after every EINT.
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CPU42 errata. */
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if (gen_interrupt_nops || warn_interrupt_nops)
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{
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if (gen_interrupt_nops)
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as_warn (_("NOP inserted between two instructions that change interrupt state"));
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if (prev_insn_is_dint)
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{
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if (gen_interrupt_nops)
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{
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gen_nop ();
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if (warn_interrupt_nops)
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as_warn (_(INSERT_NOP_AFTER_DINT));
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}
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else
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as_warn (_(WARN_NOP_AFTER_DINT));
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}
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else if (prev_insn_is_eint)
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{
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if (gen_interrupt_nops)
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{
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gen_nop ();
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if (warn_interrupt_nops)
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as_warn (_(INSERT_NOP_AFTER_EINT));
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}
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else
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as_warn (_(WARN_NOP_AFTER_EINT));
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}
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/* If we get here it's because the last instruction was
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determined to either disable or enable interrupts, but
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we're not sure which.
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We have no information yet about what effect the
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current instruction has on interrupts, that has to be
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sorted out later.
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The last insn may have required a NOP after it, so we
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deal with that now. */
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else
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as_warn (_("a NOP might be needed here because of successive changes in interrupt state"));
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{
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if (gen_interrupt_nops)
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{
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gen_nop ();
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if (warn_interrupt_nops)
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as_warn (_(INSERT_NOP_AFTER_UNKNOWN));
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}
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else
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/* warn_unsure_interrupt was called on the previous
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insn. */
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as_warn (_(WARN_NOP_AFTER_UNKNOWN));
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}
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}
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if (gen_interrupt_nops)
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/* Emit a NOP between interrupt enable/disable.
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See 1.3.4.1 of the MSP430x5xx User Guide. */
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doit = TRUE;
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break;
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case NOP_CHECK_CPU12:
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@ -2684,7 +2803,7 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
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as_warn (_("CPU12: CMP/BIT with PC destination ignores next instruction"));
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if (silicon_errata_fix & SILICON_ERRATA_CPU12)
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doit = TRUE;
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gen_nop ();
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break;
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case NOP_CHECK_CPU19:
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@ -2692,7 +2811,7 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
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as_warn (_("CPU19: Instruction setting CPUOFF must be followed by a NOP"));
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if (silicon_errata_fix & SILICON_ERRATA_CPU19)
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doit = TRUE;
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gen_nop ();
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break;
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default:
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@ -2702,15 +2821,7 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
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check_for_nop &= ~ (check_for_nop & - check_for_nop);
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}
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while (check_for_nop);
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if (doit)
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{
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frag = frag_more (2);
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bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag);
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dwarf2_emit_insn (2);
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}
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}
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check_for_nop = 0;
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}
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@ -2721,24 +2832,7 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
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{
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case 0:
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if (is_opcode ("eint"))
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{
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if (! prev_insn_is_nop)
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{
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if (gen_interrupt_nops)
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{
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frag = frag_more (2);
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bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag);
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dwarf2_emit_insn (2);
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if (warn_interrupt_nops)
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as_warn (_("inserting a NOP before EINT"));
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}
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else if (warn_interrupt_nops)
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as_warn (_("a NOP might be needed before the EINT"));
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}
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}
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else if (is_opcode ("dint"))
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check_for_nop |= NOP_CHECK_INTERRUPT;
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warn_eint_nop (prev_insn_is_nop, prev_insn_is_dint);
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/* Set/clear bits instructions. */
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if (extended_op)
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@ -2796,9 +2890,6 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
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as_warn (_("CPU13: SR is destination of SR altering instruction"));
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}
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if (is_opcode ("clr") && bin == 0x4302 /* CLR R2*/)
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check_for_nop |= NOP_CHECK_INTERRUPT;
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/* Compute the entire instruction length, in bytes. */
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op_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2);
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insn_length += op_length;
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@ -2896,6 +2987,8 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
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/* ... and the opcode alters the SR. */
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&& (is_opcode ("rla") || is_opcode ("rlc")
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|| is_opcode ("rlax") || is_opcode ("rlcx")
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|| is_opcode ("sxt") || is_opcode ("sxtx")
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|| is_opcode ("swpb")
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))
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{
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if (silicon_errata_fix & SILICON_ERRATA_CPU13)
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@ -3447,6 +3540,12 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
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}
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break;
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/* FIXME: Emit warning when dest reg SR(R2) is addressed with .B or .A.
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From f5 ref man 6.3.3:
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The 16-bit Status Register (SR, also called R2), used as a source or
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destination register, can only be used in register mode addressed
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with word instructions. */
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case 1: /* Format 1, double operand. */
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line = extract_operand (line, l1, sizeof (l1));
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line = extract_operand (line, l2, sizeof (l2));
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@ -3501,20 +3600,9 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
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else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
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as_warn (_("CPU13: SR is destination of SR altering instruction"));
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}
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if ( (is_opcode ("bic") && bin == 0xc232)
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|| (is_opcode ("bis") && bin == 0xd232)
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|| (is_opcode ("mov") && op2.mode == OP_REG && op2.reg == 2))
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{
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/* Avoid false checks when a constant value is being put into the SR. */
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if (op1.mode == OP_EXP
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&& op1.exp.X_op == O_constant
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&& (op1.exp.X_add_number & 0x8) != 0x8)
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;
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else
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check_for_nop |= NOP_CHECK_INTERRUPT;
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}
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/* Chain these checks for SR manipulations so we can warn if they are not
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caught. */
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if (((is_opcode ("bis") && bin == 0xd032)
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|| (is_opcode ("mov") && bin == 0x4032)
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|| (is_opcode ("xor") && bin == 0xe032))
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@ -3522,6 +3610,60 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
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&& op1.exp.X_op == O_constant
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&& (op1.exp.X_add_number & 0x10) == 0x10)
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check_for_nop |= NOP_CHECK_CPU19;
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else if ((is_opcode ("mov") && op2.mode == OP_REG && op2.reg == 2))
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{
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/* Any MOV with the SR as the destination either enables or disables
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interrupts. */
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if (op1.mode == OP_EXP
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&& op1.exp.X_op == O_constant)
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{
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if ((op1.exp.X_add_number & 0x8) == 0x8)
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{
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/* The GIE bit is being set. */
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warn_eint_nop (prev_insn_is_nop, prev_insn_is_dint);
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this_insn_is_eint = TRUE;
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}
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else
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/* The GIE bit is being cleared. */
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this_insn_is_dint = TRUE;
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}
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/* If an immediate value which is covered by the constant generator
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is the src, then op1 will have been changed to either R2 or R3 by
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this point.
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The only constants covered by CG1 and CG2, which have bit 3 set
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and therefore would enable interrupts when writing to the SR, are
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R2 with addresing mode 0b11 and R3 with 0b11.
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The addressing mode is in bits 5:4 of the binary opcode. */
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else if (op1.mode == OP_REG
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&& (op1.reg == 2 || op1.reg == 3)
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&& (bin & 0x30) == 0x30)
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{
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warn_eint_nop (prev_insn_is_nop, prev_insn_is_dint);
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this_insn_is_eint = TRUE;
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}
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/* Any other use of the constant generator with destination R2, will
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disable interrupts. */
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else if (op1.mode == OP_REG
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||||
&& (op1.reg == 2 || op1.reg == 3))
|
||||
this_insn_is_dint = TRUE;
|
||||
else
|
||||
{
|
||||
/* FIXME: Couldn't work out whether the insn is enabling or
|
||||
disabling interrupts, so for safety need to treat it as both
|
||||
a DINT and EINT. */
|
||||
warn_unsure_interrupt ();
|
||||
check_for_nop |= NOP_CHECK_INTERRUPT;
|
||||
}
|
||||
}
|
||||
else if (is_eint (opcode->name, bin))
|
||||
warn_eint_nop (prev_insn_is_nop, prev_insn_is_dint);
|
||||
else if ((bin & 0x32) == 0x32)
|
||||
{
|
||||
/* Double-operand insn with the As==0b11 and Rdst==0x2 will result in
|
||||
* an interrupt state change if a write happens. */
|
||||
/* FIXME: How strict to be here? */
|
||||
;
|
||||
}
|
||||
|
||||
/* Compute the entire length of the instruction in bytes. */
|
||||
op_length = (extended_op ? 2 : 0) /* The extension word. */
|
||||
|
|
@ -3959,11 +4101,34 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
|
|||
as_bad (_("Illegal instruction or not implemented opcode."));
|
||||
}
|
||||
|
||||
if (is_opcode ("nop"))
|
||||
prev_insn_is_nop = TRUE;
|
||||
else
|
||||
prev_insn_is_nop = FALSE;
|
||||
|
||||
if (is_opcode ("nop"))
|
||||
{
|
||||
prev_insn_is_nop = TRUE;
|
||||
prev_insn_is_dint = FALSE;
|
||||
prev_insn_is_eint = FALSE;
|
||||
}
|
||||
else if (this_insn_is_dint || is_dint (opcode->name, bin))
|
||||
{
|
||||
prev_insn_is_dint = TRUE;
|
||||
prev_insn_is_eint = FALSE;
|
||||
prev_insn_is_nop = FALSE;
|
||||
check_for_nop |= NOP_CHECK_INTERRUPT;
|
||||
}
|
||||
/* NOP is not needed after EINT for 430 ISA. */
|
||||
else if (target_is_430x () && (this_insn_is_eint || is_eint (opcode->name, bin)))
|
||||
{
|
||||
prev_insn_is_eint = TRUE;
|
||||
prev_insn_is_nop = FALSE;
|
||||
prev_insn_is_dint = FALSE;
|
||||
check_for_nop |= NOP_CHECK_INTERRUPT;
|
||||
}
|
||||
else
|
||||
{
|
||||
prev_insn_is_nop = FALSE;
|
||||
prev_insn_is_dint = FALSE;
|
||||
prev_insn_is_eint = FALSE;
|
||||
}
|
||||
|
||||
input_line_pointer = line;
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -4699,7 +4864,16 @@ void
|
|||
msp430_md_end (void)
|
||||
{
|
||||
if (check_for_nop)
|
||||
as_warn ("assembly finished without a possibly needed NOP instruction");
|
||||
{
|
||||
if (gen_interrupt_nops)
|
||||
{
|
||||
gen_nop ();
|
||||
if (warn_interrupt_nops)
|
||||
as_warn (INSERT_NOP_AT_EOF);
|
||||
}
|
||||
else if (warn_interrupt_nops)
|
||||
as_warn (_(WARN_NOP_AT_EOF));
|
||||
}
|
||||
|
||||
bfd_elf_add_proc_attr_int (stdoutput, OFBA_MSPABI_Tag_ISA,
|
||||
target_is_430x () ? 2 : 1);
|
||||
|
|
|
|||
|
|
@ -4,14 +4,15 @@
|
|||
[^:]*:8: Error: junk found after instruction: mov.cd r1,r2
|
||||
[^:]*:9: Error: junk found after instruction: mov.cd r1,r2
|
||||
[^:]*:10: Warning: no size modifier after period, .w assumed
|
||||
[^:]*:10: Warning: a NOP might be needed here, before this interrupt state change
|
||||
[^:]*:11: Error: instruction bis.a does not exist
|
||||
[^:]*:16: Warning: a NOP might be needed here because of successive changes in interrupt state
|
||||
[^:]*:16: Warning: a NOP might be needed before the EINT
|
||||
[^:]*:25: Warning: a NOP might be needed here because of successive changes in interrupt state
|
||||
[^:]*:25: Warning: a NOP might be needed before the EINT
|
||||
[^:]*:29: Warning: a NOP might be needed here because of successive changes in interrupt state
|
||||
[^:]*:31: Warning: a NOP might be needed here because of successive changes in interrupt state
|
||||
[^:]*:32: Warning: a NOP might be needed here because of successive changes in interrupt state
|
||||
[^:]*:33: Warning: a NOP might be needed here because of successive changes in interrupt state
|
||||
[^:]*:34: Warning: a NOP might be needed here because of successive changes in interrupt state
|
||||
[^:]*: Warning: assembly finished without a possibly needed NOP instruction
|
||||
[^:]*:16: Warning: a NOP might also be needed here, after the instruction that changed interrupt state
|
||||
[^:]*:16: Warning: a NOP might be needed here, before an interrupt enable instruction
|
||||
[^:]*:25: Warning: a NOP might be needed here, after an interrupt disable instruction
|
||||
[^:]*:26: Warning: a NOP might be needed here, after an interrupt enable instruction
|
||||
[^:]*:29: Warning: a NOP might be needed here, after an interrupt disable instruction
|
||||
[^:]*:31: Warning: a NOP might be needed here, after an interrupt disable instruction
|
||||
[^:]*:32: Warning: a NOP might be needed here, after an interrupt disable instruction
|
||||
[^:]*:33: Warning: a NOP might be needed here, after an interrupt disable instruction
|
||||
[^:]*:34: Warning: a NOP might be needed here, after an interrupt enable instruction
|
||||
[^:]*: Warning: a NOP might be needed after the interrupt state change at the end of the file
|
||||
|
|
|
|||
|
|
@ -27,4 +27,15 @@ if [expr [istarget "msp430-*-*"]] then {
|
|||
run_dump_test "high-data-bss-sym" { { as "-mdata-region=upper" } }
|
||||
run_dump_test "high-data-bss-sym" { { as "-mdata-region=either" } }
|
||||
run_dump_test "pr22133"
|
||||
run_dump_test "nop-int-430"
|
||||
run_dump_test "nop-int-430x"
|
||||
run_dump_test "nop-int-430x-silent"
|
||||
run_dump_test "nop-eint-430"
|
||||
run_dump_test "nop-eint-430x"
|
||||
run_dump_test "nop-eint-430x-silent"
|
||||
run_dump_test "nop-eint-430x-ignore"
|
||||
run_dump_test "nop-dint-430"
|
||||
run_dump_test "nop-dint-430x"
|
||||
run_dump_test "nop-dint-430x-silent"
|
||||
run_dump_test "nop-dint-430x-ignore"
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,32 @@
|
|||
#name: DINT NOP Insertions (MSP430 CPU)
|
||||
#source: nop-dint.s
|
||||
#as: -my -mn -mcpu=430
|
||||
#warning_output: nop-dint-430.l
|
||||
#objdump: -d --prefix-addresses --show-raw-insn
|
||||
|
||||
.*: +file format .*msp.*
|
||||
|
||||
Disassembly of section .text:
|
||||
0x0+000 32 c2[ ]+dint[ ]+
|
||||
0x0+002 03 43[ ]+nop[ ]+
|
||||
0x0+004 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+008 32 c2[ ]+dint[ ]+
|
||||
0x0+00a 03 43[ ]+nop[ ]+
|
||||
0x0+00c 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+010 32 c2[ ]+dint[ ]+
|
||||
0x0+012 03 43[ ]+nop[ ]+
|
||||
0x0+014 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+018 02 43[ ]+clr r2 ;
|
||||
0x0+01a 03 43[ ]+nop[ ]+
|
||||
0x0+01c 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+020 32 40 07 00[ ]+mov #7, r2 ;
|
||||
0x0+024 03 43[ ]+nop[ ]+
|
||||
0x0+026 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+02a 32 40 07 f0[ ]+mov #-4089, r2 ;#0xf007
|
||||
0x0+02e 03 43[ ]+nop[ ]+
|
||||
0x0+030 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+034 02 43[ ]+clr r2 ;
|
||||
0x0+036 03 43[ ]+nop[ ]+
|
||||
0x0+038 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+03c 32 c2[ ]+dint[ ]+
|
||||
0x0+03e 03 43[ ]+nop[ ]+
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
[^:]*: Assembler messages:
|
||||
[^:]*:11: Warning: NOP inserted here, after an interrupt disable instruction
|
||||
[^:]*:15: Warning: NOP inserted here, after an interrupt disable instruction
|
||||
[^:]*:18: Warning: NOP inserted here, after an interrupt disable instruction
|
||||
[^:]*:21: Warning: NOP inserted here, after an interrupt disable instruction
|
||||
[^:]*:24: Warning: NOP inserted here, after an interrupt disable instruction
|
||||
[^:]*:27: Warning: NOP inserted here, after an interrupt disable instruction
|
||||
[^:]*:30: Warning: NOP inserted here, after an interrupt disable instruction
|
||||
[^:]*: Warning: NOP inserted after the interrupt state change at the end of the file
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
#name: Ignore DINT NOP Insertions (MSP430X CPU)
|
||||
#source: nop-dint.s
|
||||
#as: -mY -mcpu=430x
|
||||
#objdump: -d --prefix-addresses --show-raw-insn
|
||||
#failif
|
||||
#...
|
||||
0x0.*nop.*
|
||||
#...
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
#name: Silent DINT NOP Insertions (MSP430X CPU)
|
||||
#source: nop-dint.s
|
||||
#as: -mY -mn -mcpu=430x
|
||||
#objdump: -d --prefix-addresses --show-raw-insn
|
||||
|
||||
.*: +file format .*msp.*
|
||||
|
||||
Disassembly of section .text:
|
||||
0x0+000 32 c2[ ]+dint[ ]+
|
||||
0x0+002 03 43[ ]+nop[ ]+
|
||||
0x0+004 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+008 32 c2[ ]+dint[ ]+
|
||||
0x0+00a 03 43[ ]+nop[ ]+
|
||||
0x0+00c 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+010 32 c2[ ]+dint[ ]+
|
||||
0x0+012 03 43[ ]+nop[ ]+
|
||||
0x0+014 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+018 02 43[ ]+clr r2 ;
|
||||
0x0+01a 03 43[ ]+nop[ ]+
|
||||
0x0+01c 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+020 32 40 07 00[ ]+mov #7, r2 ;
|
||||
0x0+024 03 43[ ]+nop[ ]+
|
||||
0x0+026 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+02a 32 40 07 f0[ ]+mov #-4089, r2 ;#0xf007
|
||||
0x0+02e 03 43[ ]+nop[ ]+
|
||||
0x0+030 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+034 02 43[ ]+clr r2 ;
|
||||
0x0+036 03 43[ ]+nop[ ]+
|
||||
0x0+038 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+03c 32 c2[ ]+dint[ ]+
|
||||
0x0+03e 03 43[ ]+nop[ ]+
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
#name: DINT NOP Insertions (MSP430X CPU)
|
||||
#source: nop-dint.s
|
||||
#as: -my -mn -mcpu=430x
|
||||
#warning_output: nop-dint-430.l
|
||||
#objdump: -d --prefix-addresses --show-raw-insn
|
||||
|
||||
.*: +file format .*msp.*
|
||||
|
||||
Disassembly of section .text:
|
||||
0x0+000 32 c2[ ]+dint[ ]+
|
||||
0x0+002 03 43[ ]+nop[ ]+
|
||||
0x0+004 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+008 32 c2[ ]+dint[ ]+
|
||||
0x0+00a 03 43[ ]+nop[ ]+
|
||||
0x0+00c 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+010 32 c2[ ]+dint[ ]+
|
||||
0x0+012 03 43[ ]+nop[ ]+
|
||||
0x0+014 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+018 02 43[ ]+clr r2 ;
|
||||
0x0+01a 03 43[ ]+nop[ ]+
|
||||
0x0+01c 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+020 32 40 07 00[ ]+mov #7, r2 ;
|
||||
0x0+024 03 43[ ]+nop[ ]+
|
||||
0x0+026 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+02a 32 40 07 f0[ ]+mov #-4089, r2 ;#0xf007
|
||||
0x0+02e 03 43[ ]+nop[ ]+
|
||||
0x0+030 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+034 02 43[ ]+clr r2 ;
|
||||
0x0+036 03 43[ ]+nop[ ]+
|
||||
0x0+038 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+03c 32 c2[ ]+dint[ ]+
|
||||
0x0+03e 03 43[ ]+nop[ ]+
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
[^:]*: Assembler messages:
|
||||
[^:]*:11: Warning: NOP inserted here, after an interrupt disable instruction
|
||||
[^:]*:15: Warning: NOP inserted here, after an interrupt disable instruction
|
||||
[^:]*:18: Warning: NOP inserted here, after an interrupt disable instruction
|
||||
[^:]*:21: Warning: NOP inserted here, after an interrupt disable instruction
|
||||
[^:]*:24: Warning: NOP inserted here, after an interrupt disable instruction
|
||||
[^:]*:27: Warning: NOP inserted here, after an interrupt disable instruction
|
||||
[^:]*:30: Warning: NOP inserted here, after an interrupt disable instruction
|
||||
[^:]*: Warning: NOP inserted after the interrupt state change at the end of the file
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
.text
|
||||
|
||||
;;; Test for NOP warnings when disabling interrupts, which are common to both
|
||||
;;; 430 and 430x ISA.
|
||||
;;; "MOV &FOO,r10" is used as an artbitrary statement which isn't a NOP, to
|
||||
;;; break up the instructions being tested.
|
||||
|
||||
;;; Test NOP required after DINT
|
||||
DINT
|
||||
|
||||
MOV &FOO,r10
|
||||
;;; Check aliases for which the GIE bit (bit 3) of the SR can be cleared
|
||||
;;; These should all cause warnings
|
||||
BIC.W #8,R2
|
||||
MOV &FOO,r10
|
||||
|
||||
BIC.W #8,SR
|
||||
MOV &FOO,r10
|
||||
|
||||
MOV.W #0,R2
|
||||
MOV &FOO,r10
|
||||
|
||||
MOV.W #7,R2
|
||||
MOV &FOO,r10
|
||||
|
||||
MOV.W #0xf007,R2
|
||||
MOV &FOO,r10
|
||||
|
||||
CLR R2
|
||||
MOV &FOO,r10
|
||||
|
||||
;;; The above hopefully covers the legitimate ways the SR might be cleared,
|
||||
;;; but there are other insns that can technically modify R2, but shouldn't be
|
||||
;;; used.
|
||||
|
||||
;;; Test DINT at end of file
|
||||
DINT
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
#name: EINT NOP Insertions (MSP430 CPU)
|
||||
#source: nop-eint.s
|
||||
#as: -my -mn -mcpu=430
|
||||
#warning_output: nop-eint-430.l
|
||||
#objdump: -d --prefix-addresses --show-raw-insn
|
||||
|
||||
.*: +file format .*msp.*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
0x0+0000 32 d2[ ]+eint[ ]+
|
||||
0x0+0002 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+0006 32 d2[ ]+eint[ ]+
|
||||
0x0+0008 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+000c 32 d2[ ]+eint[ ]+
|
||||
0x0+000e 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+0012 32 42[ ]+mov #8, r2 ;r2 As==11
|
||||
0x0+0014 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+0018 32 40 0f 00[ ]+mov #15, r2 ;#0x000f
|
||||
0x0+001c 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+0020 32 43[ ]+mov #-1, r2 ;r3 As==11
|
||||
0x0+0022 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+0026 32 d2[ ]+eint[ ]+
|
||||
0x0+0028 32 c2[ ]+dint[ ]+
|
||||
0x0+002a 03 43[ ]+nop[ ]+
|
||||
0x0+002c 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+0030 32 c2[ ]+dint[ ]+
|
||||
0x0+0032 03 43[ ]+nop[ ]+
|
||||
0x0+0034 32 d2[ ]+eint[ ]+
|
||||
0x0+0036 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+003a 32 d2[ ]+eint[ ]+
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
[^:]*: Assembler messages:
|
||||
[^:]*:36: Warning: NOP inserted here, after an interrupt disable instruction
|
||||
[^:]*:39: Warning: NOP inserted here, after an interrupt disable instruction
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
#name: Ignore EINT NOP Insertions (MSP430X CPU)
|
||||
#source: nop-eint.s
|
||||
#as: -mY -mcpu=430x
|
||||
#objdump: -d --prefix-addresses --show-raw-insn
|
||||
#failif
|
||||
#...
|
||||
0x0.*nop.*
|
||||
#...
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
#name: Silent EINT NOP Insertions (MSP430X CPU)
|
||||
#source: nop-eint.s
|
||||
#as: -mY -mn -mcpu=430x
|
||||
#objdump: -d --prefix-addresses --show-raw-insn
|
||||
|
||||
.*: +file format .*msp.*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
0x0+0000 03 43[ ]+nop[ ]+
|
||||
0x0+0002 32 d2[ ]+eint[ ]+
|
||||
0x0+0004 03 43[ ]+nop[ ]+
|
||||
0x0+0006 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+000a 03 43[ ]+nop[ ]+
|
||||
0x0+000c 32 d2[ ]+eint[ ]+
|
||||
0x0+000e 03 43[ ]+nop[ ]+
|
||||
0x0+0010 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+0014 03 43[ ]+nop[ ]+
|
||||
0x0+0016 32 d2[ ]+eint[ ]+
|
||||
0x0+0018 03 43[ ]+nop[ ]+
|
||||
0x0+001a 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+001e 03 43[ ]+nop[ ]+
|
||||
0x0+0020 32 42[ ]+mov #8, r2 ;r2 As==11
|
||||
0x0+0022 03 43[ ]+nop[ ]+
|
||||
0x0+0024 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+0028 03 43[ ]+nop[ ]+
|
||||
0x0+002a 32 40 0f 00[ ]+mov #15, r2 ;#0x000f
|
||||
0x0+002e 03 43[ ]+nop[ ]+
|
||||
0x0+0030 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+0034 03 43[ ]+nop[ ]+
|
||||
0x0+0036 32 43[ ]+mov #-1, r2 ;r3 As==11
|
||||
0x0+0038 03 43[ ]+nop[ ]+
|
||||
0x0+003a 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+003e 03 43[ ]+nop[ ]+
|
||||
0x0+0040 32 d2[ ]+eint[ ]+
|
||||
0x0+0042 03 43[ ]+nop[ ]+
|
||||
0x0+0044 32 c2[ ]+dint[ ]+
|
||||
0x0+0046 03 43[ ]+nop[ ]+
|
||||
0x0+0048 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+004c 32 c2[ ]+dint[ ]+
|
||||
0x0+004e 03 43[ ]+nop[ ]+
|
||||
0x0+0050 32 d2[ ]+eint[ ]+
|
||||
0x0+0052 03 43[ ]+nop[ ]+
|
||||
0x0+0054 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+0058 03 43[ ]+nop[ ]+
|
||||
0x0+005a 32 d2[ ]+eint[ ]+
|
||||
0x0+005c 03 43[ ]+nop[ ]+
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
#name: EINT NOP Insertions (MSP430X CPU)
|
||||
#source: nop-eint.s
|
||||
#as: -my -mn -mcpu=430x
|
||||
#warning_output: nop-eint-430x.l
|
||||
#objdump: -d --prefix-addresses --show-raw-insn
|
||||
|
||||
.*: +file format .*msp.*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
0x0+0000 03 43[ ]+nop[ ]+
|
||||
0x0+0002 32 d2[ ]+eint[ ]+
|
||||
0x0+0004 03 43[ ]+nop[ ]+
|
||||
0x0+0006 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+000a 03 43[ ]+nop[ ]+
|
||||
0x0+000c 32 d2[ ]+eint[ ]+
|
||||
0x0+000e 03 43[ ]+nop[ ]+
|
||||
0x0+0010 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+0014 03 43[ ]+nop[ ]+
|
||||
0x0+0016 32 d2[ ]+eint[ ]+
|
||||
0x0+0018 03 43[ ]+nop[ ]+
|
||||
0x0+001a 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+001e 03 43[ ]+nop[ ]+
|
||||
0x0+0020 32 42[ ]+mov #8, r2 ;r2 As==11
|
||||
0x0+0022 03 43[ ]+nop[ ]+
|
||||
0x0+0024 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+0028 03 43[ ]+nop[ ]+
|
||||
0x0+002a 32 40 0f 00[ ]+mov #15, r2 ;#0x000f
|
||||
0x0+002e 03 43[ ]+nop[ ]+
|
||||
0x0+0030 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+0034 03 43[ ]+nop[ ]+
|
||||
0x0+0036 32 43[ ]+mov #-1, r2 ;r3 As==11
|
||||
0x0+0038 03 43[ ]+nop[ ]+
|
||||
0x0+003a 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+003e 03 43[ ]+nop[ ]+
|
||||
0x0+0040 32 d2[ ]+eint[ ]+
|
||||
0x0+0042 03 43[ ]+nop[ ]+
|
||||
0x0+0044 32 c2[ ]+dint[ ]+
|
||||
0x0+0046 03 43[ ]+nop[ ]+
|
||||
0x0+0048 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+004c 32 c2[ ]+dint[ ]+
|
||||
0x0+004e 03 43[ ]+nop[ ]+
|
||||
0x0+0050 32 d2[ ]+eint[ ]+
|
||||
0x0+0052 03 43[ ]+nop[ ]+
|
||||
0x0+0054 1a 42 00 00[ ]+mov &0x0000,r10 ;0x0000
|
||||
0x0+0058 03 43[ ]+nop[ ]+
|
||||
0x0+005a 32 d2[ ]+eint[ ]+
|
||||
0x0+005c 03 43[ ]+nop[ ]+
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
[^:]*: Assembler messages:
|
||||
[^:]*:7: Warning: NOP inserted here, before an interrupt enable instruction
|
||||
[^:]*:9: Warning: NOP inserted here, after an interrupt enable instruction
|
||||
[^:]*:12: Warning: NOP inserted here, before an interrupt enable instruction
|
||||
[^:]*:13: Warning: NOP inserted here, after an interrupt enable instruction
|
||||
[^:]*:15: Warning: NOP inserted here, before an interrupt enable instruction
|
||||
[^:]*:16: Warning: NOP inserted here, after an interrupt enable instruction
|
||||
[^:]*:18: Warning: NOP inserted here, before an interrupt enable instruction
|
||||
[^:]*:19: Warning: NOP inserted here, after an interrupt enable instruction
|
||||
[^:]*:21: Warning: NOP inserted here, before an interrupt enable instruction
|
||||
[^:]*:22: Warning: NOP inserted here, after an interrupt enable instruction
|
||||
[^:]*:24: Warning: NOP inserted here, before an interrupt enable instruction
|
||||
[^:]*:25: Warning: NOP inserted here, after an interrupt enable instruction
|
||||
[^:]*:33: Warning: NOP inserted here, before an interrupt enable instruction
|
||||
[^:]*:34: Warning: NOP inserted here, after an interrupt enable instruction
|
||||
[^:]*:36: Warning: NOP inserted here, after an interrupt disable instruction
|
||||
[^:]*:39: Warning: NOP inserted here, after an interrupt disable instruction
|
||||
[^:]*:41: Warning: NOP inserted here, after an interrupt enable instruction
|
||||
[^:]*:44: Warning: NOP inserted here, before an interrupt enable instruction
|
||||
[^:]*: Warning: NOP inserted after the interrupt state change at the end of the file
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
.text
|
||||
|
||||
;;; Test for NOP warnings when enabling interrupts, which only applies to 430x
|
||||
;;; ISA.
|
||||
;;; "MOV &FOO,r10" is used as an artbitrary statement which isn't a NOP, to
|
||||
;;; break up the instructions being tested.
|
||||
EINT
|
||||
|
||||
MOV &FOO,r10
|
||||
;;; Check aliases for which the GIE bit (bit 3) of the SR can be set
|
||||
;;; These should all cause warnings
|
||||
BIS.W #8,R2
|
||||
MOV &FOO,r10
|
||||
|
||||
BIS.W #8,SR
|
||||
MOV &FOO,r10
|
||||
|
||||
MOV.W #8,R2
|
||||
MOV &FOO,r10
|
||||
|
||||
MOV #0xf,R2
|
||||
MOV &FOO,r10
|
||||
|
||||
MOV #0xffff,R2
|
||||
MOV &FOO,r10
|
||||
|
||||
;;; The above hopefully covers the legitimate ways the SR might be set
|
||||
;;; but there are other insns that can technically modify R2, but shouldn't be
|
||||
;;; used.
|
||||
|
||||
;;; Verify EINT/DINT chained behaviour
|
||||
|
||||
EINT
|
||||
DINT
|
||||
|
||||
MOV &FOO,r10
|
||||
|
||||
DINT
|
||||
EINT
|
||||
|
||||
MOV &FOO,r10
|
||||
|
||||
;;; Test EINT at end of file
|
||||
EINT
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
#name: Interrupt NOP Warnings (MSP430 CPU)
|
||||
#source: nop-int.s
|
||||
#as: -my -mcpu=430
|
||||
#warning_output: nop-int-430.l
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
[^:]*: Assembler messages:
|
||||
[^:]*:60: Warning: a NOP might be needed here, after an interrupt disable instruction
|
||||
[^:]*:66: Warning: a NOP might be needed here, after an interrupt disable instruction
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
#name: Silence Interrupt NOP Warnings (MSP430X CPU)
|
||||
#source: nop-int.s
|
||||
#as: -mY -mcpu=430x
|
||||
#objdump: -d --prefix-addresses --show-raw-insn
|
||||
#pass
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
#name: Interrupt NOP Warnings (MSP430X CPU)
|
||||
#source: nop-int.s
|
||||
#as: -my -mcpu=430x
|
||||
#warning_output: nop-int-430x.l
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
[^:]*: Assembler messages:
|
||||
[^:]*:13: Warning: a NOP might be needed here, before an interrupt enable instruction
|
||||
[^:]*:15: Warning: a NOP might be needed here, after an interrupt enable instruction
|
||||
[^:]*:17: Warning: a NOP might be needed here, before an interrupt enable instruction
|
||||
[^:]*:19: Warning: a NOP might be needed here, after an interrupt enable instruction
|
||||
[^:]*:41: Warning: a NOP might be needed here, after an interrupt enable instruction
|
||||
[^:]*:48: Warning: a NOP might be needed here, after an interrupt enable instruction
|
||||
[^:]*:60: Warning: a NOP might be needed here, after an interrupt disable instruction
|
||||
[^:]*:66: Warning: a NOP might be needed here, after an interrupt disable instruction
|
||||
[^:]*: Warning: a NOP might be needed after the interrupt state change at the end of the file
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
.text
|
||||
|
||||
;;; Test some common instruction patterns for disabling/enabling interrupts.
|
||||
;;; "MOV &FOO,r10" is used as an artbitrary statement which isn't a NOP, to
|
||||
;;; break up the instructions being tested.
|
||||
|
||||
fn1:
|
||||
;;; 1: Test EINT
|
||||
;; 430 ISA: NOP *not* required before *or* after EINT
|
||||
;; 430x ISA: NOP *is* required before *and* after EINT
|
||||
MOV &FOO,r10
|
||||
|
||||
EINT
|
||||
|
||||
MOV &FOO,r10
|
||||
|
||||
BIS.W #8,SR ; Alias for EINT
|
||||
|
||||
MOV &FOO,r10
|
||||
;;; 2: Test DINT
|
||||
;; 430 ISA: NOP *is* required after DINT
|
||||
;; 430x ISA: NOP *is* required after DINT
|
||||
MOV &FOO,r10
|
||||
|
||||
DINT
|
||||
NOP
|
||||
|
||||
MOV &FOO,r10
|
||||
|
||||
BIC.W #8,SR ; Alias for DINT
|
||||
NOP
|
||||
|
||||
MOV &FOO,r10
|
||||
;;; 3: Test EINT immediately before DINT
|
||||
;; 430 ISA: NOP *not* required.
|
||||
;; 430x ISA: NOP *is* required between EINT and DINT
|
||||
MOV &FOO,r10
|
||||
|
||||
NOP
|
||||
EINT
|
||||
DINT
|
||||
NOP
|
||||
|
||||
MOV &FOO,r10
|
||||
|
||||
NOP
|
||||
BIS.W #8,SR ; Alias for EINT
|
||||
BIC.W #8,SR ; Alias for DINT
|
||||
NOP
|
||||
|
||||
MOV &FOO,r10
|
||||
;;; 4: Test DINT immediately before EINT
|
||||
;; 430 ISA: NOP *is* required after DINT.
|
||||
;; 430x ISA: NOP *is* required after DINT and before EINT. Ensure only one
|
||||
;; warning is emitted.
|
||||
MOV &FOO,r10
|
||||
|
||||
NOP
|
||||
DINT
|
||||
EINT
|
||||
NOP
|
||||
|
||||
MOV &FOO,r10
|
||||
|
||||
BIC.W #8,SR ; Alias for DINT
|
||||
BIS.W #8,SR ; Alias for EINT
|
||||
NOP
|
||||
|
||||
MOV &FOO,r10
|
||||
|
||||
;;; 5: Test EINT last insn in file
|
||||
|
||||
NOP
|
||||
EINT
|
||||
Loading…
Reference in New Issue