Move MDMX instructions which are public knowledge from vr5400.igen
into mdmx.igen (MDMX is MMX on steroids). Keep the file secret.
This commit is contained in:
Andrew Cagney
parent
69628a60ea
commit
35c246c9d7
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@ -24,7 +24,7 @@ else
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lose_these_too="${r5900_files} ${lose_these_too}"
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fi
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vr5400_files="vr5400.igen"
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vr5400_files="vr5400.igen mdmx.igen"
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if ( echo $* | grep keep\-vr5400 > /dev/null ) ; then
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keep_these_too="${vr5400_files} ${keep_these_too}"
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else
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@ -148,7 +148,7 @@ else
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fi
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vr5400_files="ChangeLog configure configure.in sim-main.h interp.c gencode.c mips.igen mips.dc m16.igen vr5400.igen"
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vr5400_files="ChangeLog configure configure.in sim-main.h interp.c gencode.c mips.igen mips.dc m16.igen vr5400.igen mdmx.igen"
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if ( echo $* | grep keep\-vr5400 > /dev/null ) ; then
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for i in $vr5400_files ; do
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@ -1,3 +1,15 @@
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Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* mips.igen (LWC1): Correct assembler - lwc1 not swc1.
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start-sanitize-vr5400
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* sim-main.h: Add 8*3*8 bit accumulator.
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* vr5400.igen: Move mdmx instructins from here
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* mdmx.igen: To here - new file. Add/fix missing instructions.
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* mips.igen: Include mdmx.igen.
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start-sanitize-vr5400
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Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* sim-main.h (sim-fpu.h): Include.
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File diff suppressed because it is too large
Load Diff
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@ -239,442 +239,3 @@
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int s = MASKED (GPR[RS], 5, 0);
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GPR[RD] = ROTR64 (GPR[RT], s);
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}
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// Media Instructions
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// ------------------
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// Note: Vector unit in R5400 supports only octal byte format.
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// Note: The sel field is deduced by special handling of the "vt"
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// operand.
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// If vt is:
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// of the form $vt[0], then sel is 0000
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// of the form $vt[1], then sel is 0001
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// of the form $vt[2], then sel is 0010
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// of the form $vt[3], then sel is 0011
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// of the form $vt[4], then sel is 0100
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// of the form $vt[5], then sel is 0101
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// of the form $vt[6], then sel is 0110
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// of the form $vt[7], then sel is 0111
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// Normal register specifier, then sel is 1011
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// Constant, then sel is 1111
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//
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// VecAcc is the Vector Accumulator.
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// This accumulator is organized as 8X24 bit (192 bit) register.
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// This accumulator holds only signed values.
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:function:::signed:vr:int fpr, int byte
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{
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signed8 b = V1_8 (value_fpr (sd, cia, fpr, fmt_long), byte);
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return b;
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}
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:function:::void:set_vr:int fpr, int byte, signed value
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{
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abort ();
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}
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:function:::signed:VecAcc:int byte
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{
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abort ();
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return 0;
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}
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:function:::void:set_VecAcc:int byte, signed value
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{
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abort ();
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}
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:function:::int:cc:int i
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{
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abort ();
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return 0;
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}
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:function:::void:set_cc:int i, int value
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{
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abort ();
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}
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:function:::signed:Min:signed l, signed r
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{
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if (l < r)
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return l;
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else
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return r;
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}
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:function:::signed:Max:signed l, signed r
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{
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if (l < r)
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return r;
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else
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return l;
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}
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:function:::signed:Compare:signed l, signed r
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{
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abort ();
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return 0;
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}
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:function:::signed:Clamp:signed l
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{
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abort ();
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return 0;
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}
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:function:::signed:Round:signed l
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{
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abort ();
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return 0;
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}
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:function:::void:ByteAlign:int vd, int imm, int vs, int vt
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{
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abort ();
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}
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:function:::signed:One_of:int vs, int vt
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{
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abort ();
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return 0;
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}
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:function:::unsigned:do_select:int i, int sel, int vt
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{
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if (sel < 8)
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return vr (SD_, vt, sel);
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else if (sel == 0x13)
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return vr (SD_, vt, i);
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else if (sel == 0x1f)
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return vt;
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else
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semantic_illegal (sd, cia);
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return 0;
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}
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:%s::::VT:int sel, int vt
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{
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static char buf[20];
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if (sel < 8)
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sprintf (buf, "v%d[%d]", vt, sel);
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else if (sel == 0x13)
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sprintf (buf, "v%d", vt);
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else if (sel == 0x1f)
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sprintf (buf, "%d", vt);
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else
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sprintf (buf, "(invalid)");
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return buf;
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}
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// Vector Add.
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010010,4.SEL,0,5.VT,5.VS,5.VD,001011::::ADD.OB
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"add.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
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set_vr (SD_, VD, i, vr (SD_, VS, i) + do_select (SD_, i, SEL, VT));
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}
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// Vector Align.
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010010,00,3.IMM,5.VT,5.VS,5.VD,011000::::ALNI.OB
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"alni.ob v<VD>, v<VS>, v<VT>, <IMM>"
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*vr5400:
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{
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ByteAlign (SD_, VD, IMM, VS, VT);
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}
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// Vector And.
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010010,4.SEL,0,5.VT,5.VS,5.VD,001100::::AND.OB
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"and.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
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set_vr (SD_, VD, i, vr (SD_, VS, i) & do_select (SD_, i, SEL, VT));
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}
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// Vector Compare Equal.
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010010,4.SEL,0,5.VT,5.VS,00000,000001::::C.EQ.OB
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"c.eq.ob v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
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set_cc (SD_, i, Compare (SD_, vr (SD_, VS, i), do_select (SD_, i, SEL, VT)));
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}
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// Vector Compare Less Than or Equal.
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010010,4.SEL,0,5.VT,5.VS,00000,000101::::C.LE.OB
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"c.le.ob v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
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set_cc (SD_, i, Compare (SD_, vr (SD_, VS, i), do_select (SD_, i, SEL, VT)));
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}
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// Vector Compare Less Than.
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010010,4.SEL,0,5.VT,5.VS,00000,000100::::C.LT.OB
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"c.lt.ob v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
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set_cc (SD_, i, Compare (SD_, vr (SD_, VS, i), do_select (SD_, i, SEL, VT)));
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}
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// Vector Maximum.
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010010,4.SEL,0,5.VT,5.VS,5.VD,000111::::MAX.OB
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"max.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
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set_vr (SD_, VD, i, Max (SD_, vr (SD_, VS, i), do_select (SD_, i, SEL, VT)));
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}
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// Vector Minimum.
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010010,4.SEL,0,5.VT,5.VS,5.VD,000110::::MIN.OB
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"min.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
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set_vr (SD_, VD, i, Min (SD_, vr (SD_, VS, i), do_select (SD_, i, SEL, VT)));
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}
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// Vector Multiply.
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010010,4.SEL,0,5.VT,5.VS,5.VD,110000::::MUL.OB
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"mul.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
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set_vr (SD_, VD, i, vr (SD_, VS, i) * do_select (SD_, i, SEL, VT));
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}
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// Vector Multiply, Accumulate.
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010010,4.SEL,0,5.VT,5.VS,00000,110011::::MULA.OB
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"mula.ob v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
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set_VecAcc (SD_, i, VecAcc (SD_, i) + vr (SD_, VS, i) * do_select (SD_, i, SEL, VT));
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}
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// Vector Multiply, Load Accumulator.
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010010,4.SEL,0,5.VT,5.VS,10000,110011::::MULL.OB
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"mull.ob v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
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set_VecAcc (SD_, i, 0 + vr (SD_, VS, i) * do_select (SD_, i, SEL, VT));
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}
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// Vector Multiply, Negate, Accumulate.
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010010,4.SEL,0,5.VT,5.VS,00000,110010::::MULS.OB
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"muls.ob v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
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set_VecAcc (SD_, i, VecAcc (SD_, i) - vr (SD_, VS, i) * do_select (SD_, i, SEL, VT));
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}
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// Vector Multiply, Negate, Load Accumulator.
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010010,4.SEL,0,5.VT,5.VS,10000,110010::::MULSL.OB
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"mulsl.ob v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
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set_VecAcc (SD_, i, 0 - vr (SD_, VS, i) * do_select (SD_, i, SEL, VT));
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}
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// Vector NOr.
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010010,4.SEL,0,5.VT,5.VS,5.VD,001111::::NOR.OB
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"nor.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
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set_vr (SD_, VD, i, ! (vr (SD_, VS, i) | do_select (SD_, i, SEL, VT)));
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}
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// Vector Or.
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010010,4.SEL,0,5.VT,5.VS,5.VD,001110::::OR.OB
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"or.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
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set_vr (SD_, VD, i, vr (SD_, VS, i) | do_select (SD_, i, SEL, VT));
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}
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// Vector Pick False.
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010010,4.SEL,0,5.VT,5.VS,5.VD,000010::::PICKF.OB
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"pickf.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
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set_vr (SD_, VD, i, cc (SD_, i) ? do_select (SD_, i, SEL, VT) : vr (SD_, VS, i));
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}
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// Vector Pick True.
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010010,4.SEL,0,5.VT,5.VS,5.VD,000011::::PICKT.OB
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"pickt.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
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*vr5400:
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{
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int i;
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for (i = 0; i < 8; i++)
|
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set_vr (SD_, VD, i, cc (SD_, i) ? vr (SD_, VS, i) : do_select (SD_, i, SEL, VT));
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}
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// Vector Read Accumulator High.
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010010,1000,0,00000,00000,5.VD,111111::::RACH.OB
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"rach.ob v<VD>"
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*vr5400:
|
||||
{
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int i;
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for (i = 0; i < 8; i++)
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set_vr (SD_, VD, i, EXTRACTED (VecAcc (SD_, i), 23, 16));
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}
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// Vector Read Accumulator Low.
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010010,0000,0,00000,00000,5.VD,111111::::RACL.OB
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"racl.ob v<VD>"
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*vr5400:
|
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{
|
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int i;
|
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for (i = 0; i < 8; i++)
|
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set_vr (SD_, VD, i, EXTRACTED (VecAcc (SD_, i), 7, 0));
|
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}
|
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|
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// Vector Read Accumulator Middle.
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010010,0100,0,00000,00000,5.VD,111111::::RACM.OB
|
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"racm.ob v<VD>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, EXTRACTED (VecAcc (SD_, i), 15, 8));
|
||||
}
|
||||
|
||||
// Vector Scale, Round and Clamp Accumulator.
|
||||
010010,4.SEL,0,5.VT,00000,5.VD,100000::::RZU.OB
|
||||
"rzu.ob v<VD>, %s<VT#SEL,VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, Clamp (SD_, Round (SD_, VecAcc (SD_, i) >> do_select (SD_, i, SEL, VT))));
|
||||
}
|
||||
|
||||
// Vector Element Shuffle.
|
||||
010010,0110,0,5.VT,5.VS,5.VD,011111::::SHFL.MIXH.OB
|
||||
"shfl.mixh.ob v<VD>, v<VS>, <VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, One_of (SD_, VS, VT));
|
||||
}
|
||||
|
||||
// Vector Element Shuffle.
|
||||
010010,0111,0,5.VT,5.VS,5.VD,011111::::SHFL.MIXL.OB
|
||||
"shfl.mixl.ob v<VD>, v<VS>, <VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, One_of (SD_, VS, VT));
|
||||
}
|
||||
|
||||
// Vector Element Shuffle.
|
||||
010010,0100,0,5.VT,5.VS,5.VD,011111::::SHFL.PACH.OB
|
||||
"shfl.pach.ob v<VD>, v<VS>, <VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, One_of (SD_, VS, VT));
|
||||
}
|
||||
|
||||
// Vector Element Shuffle.
|
||||
010010,0101,0,5.VT,5.VS,5.VD,011111::::SHFL.PACL.OB
|
||||
"shfl.pacl.ob v<VD>, v<VS>, <VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, One_of (SD_, VS, VT));
|
||||
}
|
||||
|
||||
// Vector Shift Left Logical.
|
||||
010010,4.SEL,0,5.VT,5.VS,5.VD,010000::::SLL.OB
|
||||
"sll.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, vr (SD_, VS, i) << do_select (SD_, i, SEL, VT));
|
||||
}
|
||||
|
||||
// Vector Shift Right Logical.
|
||||
010010,4.SEL,0,5.VT,5.VS,5.VD,010010::::SRL.OB
|
||||
"srl.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, vr (SD_, VS, i) >> do_select (SD_, i, SEL, VT));
|
||||
}
|
||||
|
||||
// Vector Subtract.
|
||||
010010,4.SEL,0,5.VT,5.VS,5.VD,001010::::SUB.OB
|
||||
"sub.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, vr (SD_, VS, i) - do_select (SD_, i, SEL, VT));
|
||||
}
|
||||
|
||||
// Vector Write Accumulator High.
|
||||
010010,1000,0,00000,5.VS,00000,111110::::WACH.OB
|
||||
"wach.ob v<VS>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
/* High8 */ set_VecAcc (SD_, i, (vr (SD_, VS, i) << 16) | MASKED (VecAcc (SD_, i), 15, 0));
|
||||
}
|
||||
|
||||
// Vector Write Accumulator Low.
|
||||
010010,0000,0,5.VT,5.VS,00000,111110::::WACL.OB
|
||||
"wacl.ob v<VS>, <VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_VecAcc (SD_, i, (EXTEND8 (vr (SD_, VS, i)) << 8) | vr (SD_, VT, i));
|
||||
}
|
||||
|
||||
// Vector XOr.
|
||||
010010,4.SEL,0,5.VT,5.VS,5.VD,001101::::XOR.OB
|
||||
"xor.ob v<VD>, v<VS>, %s<VT#SEL,VT>"
|
||||
*vr5400:
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 8; i++)
|
||||
set_vr (SD_, VD, i, vr (SD_, VS, i) ^ do_select (SD_, i, SEL, VT));
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue