include/opcode/
* mips.h (mips_opcode): Add the exclusions field. (OPCODE_IS_MEMBER): Remove macro. (cpu_is_member): New inline function. (opcode_is_member): Likewise. opcodes/ * micromips-opc.c (micromips_opcodes): Update comment. * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor instructions for IOCT as appropriate. * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with opcode_is_member. * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with the result of a check for the -Wno-missing-field-initializers GCC option. * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable. (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to compilation. (mips16-opc.lo): Likewise. (micromips-opc.lo): Likewise. * aclocal.m4: Regenerate. * configure: Regenerate. * Makefile.in: Regenerate. gas/ * config/tc-mips.c (NO_ISA_COP, COP_INSN): Remove macros. (is_opcode_valid): Remove coprocessor instruction exclusions. Replace OPCODE_IS_MEMBER with opcode_is_member. (is_opcode_valid_16): Replace OPCODE_IS_MEMBER with opcode_is_member. (macro): Remove coprocessor instruction exclusions.
This commit is contained in:
Maciej W. Rozycki
parent
a276b80c45
commit
35d0a16941
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@ -1,3 +1,12 @@
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2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
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* config/tc-mips.c (NO_ISA_COP, COP_INSN): Remove macros.
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(is_opcode_valid): Remove coprocessor instruction exclusions.
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Replace OPCODE_IS_MEMBER with opcode_is_member.
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(is_opcode_valid_16): Replace OPCODE_IS_MEMBER with
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opcode_is_member.
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(macro): Remove coprocessor instruction exclusions.
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2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
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* config/tc-mips.c (s_cpload, s_cpsetup): Fail if MIPS16 mode.
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@ -505,11 +505,6 @@ static int mips_32bitmode = 0;
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/* True if CPU has seq/sne and seqi/snei instructions. */
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#define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
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/* True if CPU does not implement the all the coprocessor insns. For these
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CPUs only those COP insns are accepted that are explicitly marked to be
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available on the CPU. ISA membership for COP insns is ignored. */
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#define NO_ISA_COP(CPU) (CPU_IS_OCTEON (CPU))
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/* True if mflo and mfhi can be immediately followed by instructions
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which write to the HI and LO registers.
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@ -580,15 +575,6 @@ static int mips_32bitmode = 0;
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#define MF_HILO_INSN(PINFO) \
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((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
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/* Returns true for a (non floating-point) coprocessor instruction. Reading
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or writing the condition code is only possible on the coprocessors and
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these insns are not marked with INSN_COP. Thus for these insns use the
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condition-code flags. */
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#define COP_INSN(PINFO) \
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(PINFO != INSN_MACRO \
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&& ((PINFO) & (FP_S | FP_D)) == 0 \
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&& ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
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/* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
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has been selected. This implies, in particular, that addresses of text
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labels have their LSB set. */
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@ -2221,13 +2207,7 @@ is_opcode_valid (const struct mips_opcode *mo)
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if (mips_opts.ase_mcu)
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isa |= INSN_MCU;
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/* Don't accept instructions based on the ISA if the CPU does not implement
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all the coprocessor insns. */
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if (NO_ISA_COP (mips_opts.arch)
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&& COP_INSN (mo->pinfo))
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isa = 0;
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if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
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if (!opcode_is_member (mo, isa, mips_opts.arch))
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return FALSE;
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/* Check whether the instruction or macro requires single-precision or
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@ -2259,7 +2239,7 @@ is_opcode_valid (const struct mips_opcode *mo)
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static bfd_boolean
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is_opcode_valid_16 (const struct mips_opcode *mo)
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{
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return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
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return opcode_is_member (mo, mips_opts.isa, mips_opts.arch);
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}
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/* Return TRUE if the size of the microMIPS opcode MO matches one
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@ -8265,15 +8245,6 @@ macro (struct mips_cl_insn *ip)
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tempreg = AT;
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used_at = 1;
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ld_noat:
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if (coproc
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&& NO_ISA_COP (mips_opts.arch)
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&& (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
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{
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as_bad (_("Opcode not supported on this processor: %s"),
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mips_cpu_info_from_arch (mips_opts.arch)->name);
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break;
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}
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if (offset_expr.X_op != O_constant
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&& offset_expr.X_op != O_symbol)
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{
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@ -9199,14 +9170,6 @@ macro (struct mips_cl_insn *ip)
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s = "c3";
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copz:
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gas_assert (!mips_opts.micromips);
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if (NO_ISA_COP (mips_opts.arch)
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&& (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
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{
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as_bad (_("Opcode not supported on this processor: %s"),
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mips_cpu_info_from_arch (mips_opts.arch)->name);
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break;
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}
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/* For now we just do C (same as Cz). The parameter will be
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stored in insn_opcode by mips_ip. */
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macro_build (NULL, s, "C", ip->insn_opcode);
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@ -1,3 +1,11 @@
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2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
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Maciej W. Rozycki <macro@codesourcery.com>
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* mips.h (mips_opcode): Add the exclusions field.
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(OPCODE_IS_MEMBER): Remove macro.
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(cpu_is_member): New inline function.
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(opcode_is_member): Likewise.
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2012-07-31 Chao-Ying Fu <fu@mips.com>
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Catherine Moore <clm@codesourcery.com>
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Maciej W. Rozycki <macro@codesourcery.com>
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@ -25,6 +25,8 @@
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#ifndef _MIPS_H_
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#define _MIPS_H_
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#include "bfd.h"
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/* These are bit masks and shift counts to use to access the various
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fields of an instruction. To retrieve the X field of an
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instruction, use the expression
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@ -353,6 +355,9 @@ struct mips_opcode
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/* A collection of bits describing the instruction sets of which this
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instruction or macro is a member. */
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unsigned long membership;
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/* A collection of bits describing the instruction sets of which this
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instruction or macro is not a member. */
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unsigned long exclusions;
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};
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/* These are the characters which may appear in the args field of an
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@ -829,46 +834,102 @@ static const unsigned int mips_isa_table[] =
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#define CPU_OCTEON2 6502
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#define CPU_XLR 887682 /* decimal 'XLR' */
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/* Return true if the given CPU is included in INSN_* mask MASK. */
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static inline bfd_boolean
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cpu_is_member (int cpu, unsigned int mask)
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{
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switch (cpu)
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{
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case CPU_R4650:
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case CPU_RM7000:
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case CPU_RM9000:
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return (mask & INSN_4650) != 0;
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case CPU_R4010:
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return (mask & INSN_4010) != 0;
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case CPU_VR4100:
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return (mask & INSN_4100) != 0;
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case CPU_R3900:
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return (mask & INSN_3900) != 0;
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case CPU_R10000:
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case CPU_R12000:
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case CPU_R14000:
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case CPU_R16000:
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return (mask & INSN_10000) != 0;
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case CPU_SB1:
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return (mask & INSN_SB1) != 0;
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case CPU_R4111:
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return (mask & INSN_4111) != 0;
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case CPU_VR4120:
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return (mask & INSN_4120) != 0;
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case CPU_VR5400:
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return (mask & INSN_5400) != 0;
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case CPU_VR5500:
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return (mask & INSN_5500) != 0;
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case CPU_LOONGSON_2E:
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return (mask & INSN_LOONGSON_2E) != 0;
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case CPU_LOONGSON_2F:
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return (mask & INSN_LOONGSON_2F) != 0;
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case CPU_LOONGSON_3A:
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return (mask & INSN_LOONGSON_3A) != 0;
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case CPU_OCTEON:
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return (mask & INSN_OCTEON) != 0;
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case CPU_OCTEONP:
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return (mask & INSN_OCTEONP) != 0;
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case CPU_OCTEON2:
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return (mask & INSN_OCTEON2) != 0;
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case CPU_XLR:
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return (mask & INSN_XLR) != 0;
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default:
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return FALSE;
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}
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}
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/* Test for membership in an ISA including chip specific ISAs. INSN
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is pointer to an element of the opcode table; ISA is the specified
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ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
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test, or zero if no CPU specific ISA test is desired. */
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test, or zero if no CPU specific ISA test is desired. Return true
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if instruction INSN is available to the given ISA and CPU. */
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#define OPCODE_IS_MEMBER(insn, isa, cpu) \
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(((isa & INSN_ISA_MASK) != 0 \
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&& ((insn)->membership & INSN_ISA_MASK) != 0 \
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&& ((mips_isa_table [(isa & INSN_ISA_MASK) - 1] >> \
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(((insn)->membership & INSN_ISA_MASK) - 1)) & 1) != 0) \
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|| ((isa & ~INSN_ISA_MASK) \
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& ((insn)->membership & ~INSN_ISA_MASK)) != 0 \
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|| (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
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|| (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
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|| (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
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|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
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|| (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
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|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
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|| ((cpu == CPU_R10000 || cpu == CPU_R12000 || cpu == CPU_R14000 \
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|| cpu == CPU_R16000) \
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&& ((insn)->membership & INSN_10000) != 0) \
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|| (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
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|| (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
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|| (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
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|| (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
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|| (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
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|| (cpu == CPU_LOONGSON_2E \
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&& ((insn)->membership & INSN_LOONGSON_2E) != 0) \
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|| (cpu == CPU_LOONGSON_2F \
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&& ((insn)->membership & INSN_LOONGSON_2F) != 0) \
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|| (cpu == CPU_LOONGSON_3A \
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&& ((insn)->membership & INSN_LOONGSON_3A) != 0) \
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|| (cpu == CPU_OCTEON \
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&& ((insn)->membership & INSN_OCTEON) != 0) \
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|| (cpu == CPU_OCTEONP \
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&& ((insn)->membership & INSN_OCTEONP) != 0) \
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|| (cpu == CPU_OCTEON2 \
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&& ((insn)->membership & INSN_OCTEON2) != 0) \
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|| (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \
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|| 0) /* Please keep this term for easier source merging. */
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static inline bfd_boolean
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opcode_is_member (const struct mips_opcode *insn, int isa, int cpu)
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{
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if (!cpu_is_member (cpu, insn->exclusions))
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{
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/* Test for ISA level compatibility. */
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if ((isa & INSN_ISA_MASK) != 0
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&& (insn->membership & INSN_ISA_MASK) != 0
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&& ((mips_isa_table[(isa & INSN_ISA_MASK) - 1]
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>> ((insn->membership & INSN_ISA_MASK) - 1)) & 1) != 0)
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return TRUE;
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/* Test for ASE compatibility. */
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if (((isa & ~INSN_ISA_MASK) & (insn->membership & ~INSN_ISA_MASK)) != 0)
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return TRUE;
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/* Test for processor-specific extensions. */
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if (cpu_is_member (cpu, insn->membership))
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return TRUE;
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}
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return FALSE;
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}
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/* This is a list of macro expanded instructions.
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@ -1,3 +1,22 @@
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2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
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* micromips-opc.c (micromips_opcodes): Update comment.
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* mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
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instructions for IOCT as appropriate.
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* mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
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opcode_is_member.
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* configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
|
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the result of a check for the -Wno-missing-field-initializers
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GCC option.
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* Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
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(mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
|
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compilation.
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(mips16-opc.lo): Likewise.
|
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(micromips-opc.lo): Likewise.
|
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* aclocal.m4: Regenerate.
|
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* configure: Regenerate.
|
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* Makefile.in: Regenerate.
|
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|
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2012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
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PR gas/14423
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|
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@ -11,6 +11,7 @@ BFDDIR = $(srcdir)/../bfd
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WARN_CFLAGS = @WARN_CFLAGS@
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NO_WERROR = @NO_WERROR@
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NO_WMISSING_FIELD_INITIALIZERS = @NO_WMISSING_FIELD_INITIALIZERS@
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AM_CFLAGS = $(WARN_CFLAGS)
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COMPILE_FOR_BUILD = $(CC_FOR_BUILD) $(INCLUDES) $(AM_CPPFLAGS) \
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@ -528,6 +529,15 @@ ia64-opc.lo: $(srcdir)/ia64-asmtab.c
|
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$(srcdir)/rl78-decode.c: @MAINT@ $(srcdir)/rl78-decode.opc opc2c$(EXEEXT_FOR_BUILD)
|
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./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rl78-decode.opc > $(srcdir)/rl78-decode.c
|
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micromips-opc.lo: micromips-opc.c
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$(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
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mips-opc.lo: mips-opc.c
|
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$(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
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mips16-opc.lo: mips16-opc.c
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$(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
|
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|
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$(srcdir)/rx-decode.c: @MAINT@ $(srcdir)/rx-decode.opc opc2c$(EXEEXT_FOR_BUILD)
|
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./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rx-decode.opc > $(srcdir)/rx-decode.c
|
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|
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|
|
|
|||
|
|
@ -54,6 +54,7 @@ am__aclocal_m4_deps = $(top_srcdir)/../bfd/acinclude.m4 \
|
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$(top_srcdir)/../config/override.m4 \
|
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$(top_srcdir)/../config/po.m4 \
|
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$(top_srcdir)/../config/progtest.m4 \
|
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$(top_srcdir)/../config/warnings.m4 \
|
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$(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \
|
||||
$(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \
|
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$(top_srcdir)/../lt~obsolete.m4 $(top_srcdir)/configure.in
|
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|
|
@ -195,6 +196,7 @@ MSGMERGE = @MSGMERGE@
|
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NM = @NM@
|
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NMEDIT = @NMEDIT@
|
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NO_WERROR = @NO_WERROR@
|
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NO_WMISSING_FIELD_INITIALIZERS = @NO_WMISSING_FIELD_INITIALIZERS@
|
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OBJDUMP = @OBJDUMP@
|
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OBJEXT = @OBJEXT@
|
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OTOOL = @OTOOL@
|
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|
|
@ -1377,6 +1379,15 @@ ia64-opc.lo: $(srcdir)/ia64-asmtab.c
|
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$(srcdir)/rl78-decode.c: @MAINT@ $(srcdir)/rl78-decode.opc opc2c$(EXEEXT_FOR_BUILD)
|
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./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rl78-decode.opc > $(srcdir)/rl78-decode.c
|
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|
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micromips-opc.lo: micromips-opc.c
|
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$(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
|
||||
|
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mips-opc.lo: mips-opc.c
|
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$(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
|
||||
|
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mips16-opc.lo: mips16-opc.c
|
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$(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
|
||||
|
||||
$(srcdir)/rx-decode.c: @MAINT@ $(srcdir)/rx-decode.opc opc2c$(EXEEXT_FOR_BUILD)
|
||||
./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rx-decode.opc > $(srcdir)/rx-decode.c
|
||||
|
||||
|
|
|
|||
|
|
@ -978,6 +978,7 @@ m4_include([../config/nls.m4])
|
|||
m4_include([../config/override.m4])
|
||||
m4_include([../config/po.m4])
|
||||
m4_include([../config/progtest.m4])
|
||||
m4_include([../config/warnings.m4])
|
||||
m4_include([../libtool.m4])
|
||||
m4_include([../ltoptions.m4])
|
||||
m4_include([../ltsugar.m4])
|
||||
|
|
|
|||
|
|
@ -640,6 +640,7 @@ INSTALL_LIBBFD_TRUE
|
|||
MAINT
|
||||
MAINTAINER_MODE_FALSE
|
||||
MAINTAINER_MODE_TRUE
|
||||
NO_WMISSING_FIELD_INITIALIZERS
|
||||
NO_WERROR
|
||||
WARN_CFLAGS
|
||||
OTOOL64
|
||||
|
|
@ -11134,7 +11135,7 @@ else
|
|||
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
|
||||
lt_status=$lt_dlunknown
|
||||
cat > conftest.$ac_ext <<_LT_EOF
|
||||
#line 11137 "configure"
|
||||
#line 11138 "configure"
|
||||
#include "confdefs.h"
|
||||
|
||||
#if HAVE_DLFCN_H
|
||||
|
|
@ -11240,7 +11241,7 @@ else
|
|||
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
|
||||
lt_status=$lt_dlunknown
|
||||
cat > conftest.$ac_ext <<_LT_EOF
|
||||
#line 11243 "configure"
|
||||
#line 11244 "configure"
|
||||
#include "confdefs.h"
|
||||
|
||||
#if HAVE_DLFCN_H
|
||||
|
|
@ -11561,6 +11562,51 @@ fi
|
|||
|
||||
|
||||
|
||||
NO_WMISSING_FIELD_INITIALIZERS=
|
||||
save_CFLAGS="$CFLAGS"
|
||||
for real_option in -Wno-missing-field-initializers; do
|
||||
# Do the check with the no- prefix removed since gcc silently
|
||||
# accepts any -Wno-* option on purpose
|
||||
case $real_option in
|
||||
-Wno-*) option=-W`expr x$real_option : 'x-Wno-\(.*\)'` ;;
|
||||
*) option=$real_option ;;
|
||||
esac
|
||||
as_acx_Woption=`$as_echo "acx_cv_prog_cc_warning_$option" | $as_tr_sh`
|
||||
|
||||
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC supports $option" >&5
|
||||
$as_echo_n "checking whether $CC supports $option... " >&6; }
|
||||
if { as_var=$as_acx_Woption; eval "test \"\${$as_var+set}\" = set"; }; then :
|
||||
$as_echo_n "(cached) " >&6
|
||||
else
|
||||
CFLAGS="$option"
|
||||
cat confdefs.h - <<_ACEOF >conftest.$ac_ext
|
||||
/* end confdefs.h. */
|
||||
|
||||
int
|
||||
main ()
|
||||
{
|
||||
|
||||
;
|
||||
return 0;
|
||||
}
|
||||
_ACEOF
|
||||
if ac_fn_c_try_compile "$LINENO"; then :
|
||||
eval "$as_acx_Woption=yes"
|
||||
else
|
||||
eval "$as_acx_Woption=no"
|
||||
fi
|
||||
rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
|
||||
|
||||
fi
|
||||
eval ac_res=\$$as_acx_Woption
|
||||
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5
|
||||
$as_echo "$ac_res" >&6; }
|
||||
if test `eval 'as_val=${'$as_acx_Woption'};$as_echo "$as_val"'` = yes; then :
|
||||
NO_WMISSING_FIELD_INITIALIZERS="$NO_WMISSING_FIELD_INITIALIZERS${NO_WMISSING_FIELD_INITIALIZERS:+ }$real_option"
|
||||
fi
|
||||
done
|
||||
CFLAGS="$save_CFLAGS"
|
||||
|
||||
|
||||
ac_config_headers="$ac_config_headers config.h:config.in"
|
||||
|
||||
|
|
|
|||
|
|
@ -42,6 +42,8 @@ AC_ARG_ENABLE(targets,
|
|||
esac])dnl
|
||||
|
||||
AM_BINUTILS_WARNINGS
|
||||
ACX_PROG_CC_WARNING_OPTS([-Wno-missing-field-initializers],
|
||||
[NO_WMISSING_FIELD_INITIALIZERS])
|
||||
|
||||
AC_CONFIG_HEADERS(config.h:config.in)
|
||||
|
||||
|
|
|
|||
|
|
@ -115,7 +115,7 @@ const struct mips_opcode micromips_opcodes[] =
|
|||
/* These instructions appear first so that the disassembler will find
|
||||
them first. The assemblers uses a hash table based on the
|
||||
instruction name anyhow. */
|
||||
/* name, args, match, mask, pinfo, pinfo2, membership */
|
||||
/* name, args, match, mask, pinfo, pinfo2, membership, [exclusions] */
|
||||
{"pref", "k,~(b)", 0x60002000, 0xfc00f000, RD_b, 0, I1 },
|
||||
{"pref", "k,o(b)", 0, (int) M_PREF_OB, INSN_MACRO, 0, I1 },
|
||||
{"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I1 },
|
||||
|
|
|
|||
|
|
@ -1562,7 +1562,7 @@ print_insn_mips (bfd_vma memaddr,
|
|||
const char *d;
|
||||
|
||||
/* We always allow to disassemble the jalx instruction. */
|
||||
if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
|
||||
if (!opcode_is_member (op, mips_isa, mips_processor)
|
||||
&& strcmp (op->name, "jalx"))
|
||||
continue;
|
||||
|
||||
|
|
|
|||
|
|
@ -197,7 +197,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
/* These instructions appear first so that the disassembler will find
|
||||
them first. The assemblers uses a hash table based on the
|
||||
instruction name anyhow. */
|
||||
/* name, args, match, mask, pinfo, pinfo2, membership */
|
||||
/* name, args, match, mask, pinfo, pinfo2, membership, [exclusions] */
|
||||
{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4_32|G3 },
|
||||
{"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I4_32|G3 },
|
||||
{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t|FP_S, 0, I4_33 },
|
||||
|
|
@ -593,27 +593,27 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3_33 },
|
||||
{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
|
||||
{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
|
||||
{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 },
|
||||
{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 },
|
||||
{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 },
|
||||
/* cfc2 is at the bottom of the table. */
|
||||
/* cfc3 is at the bottom of the table. */
|
||||
{"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
|
||||
{"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
|
||||
{"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
|
||||
{"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32, IOCT|IOCTP|IOCT2 },
|
||||
{"cins32", "t,r,+p,+S",0x70000033, 0xfc00003f, WR_t|RD_s, 0, IOCT },
|
||||
{"cins", "t,r,+P,+S",0x70000033, 0xfc00003f, WR_t|RD_s, 0, IOCT }, /* cins32 */
|
||||
{"cins", "t,r,+p,+s",0x70000032, 0xfc00003f, WR_t|RD_s, 0, IOCT },
|
||||
{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
|
||||
{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
|
||||
{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
|
||||
{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
|
||||
{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
|
||||
/* ctc2 is at the bottom of the table. */
|
||||
/* ctc3 is at the bottom of the table. */
|
||||
{"cttc1", "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
|
||||
{"cttc1", "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
|
||||
{"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32 },
|
||||
{"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32, IOCT|IOCTP|IOCT2 },
|
||||
{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3_33 },
|
||||
{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
|
||||
{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
|
||||
|
|
@ -658,8 +658,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
|
||||
{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3 },
|
||||
{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3 },
|
||||
{"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33|IOCT},
|
||||
{"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33|IOCT},
|
||||
{"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 },
|
||||
{"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
|
||||
{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 },
|
||||
{"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, 0, I65 },
|
||||
{"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, 0, I65 },
|
||||
|
|
@ -694,14 +694,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
|
||||
{"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
|
||||
{"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, 0, N411 },
|
||||
{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3|IOCT },
|
||||
{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64|IOCT},
|
||||
{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64|IOCT},
|
||||
{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3 },
|
||||
{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
|
||||
{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
|
||||
{"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 },
|
||||
{"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
|
||||
{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3|IOCT },
|
||||
{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64|IOCT},
|
||||
{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64|IOCT},
|
||||
{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3 },
|
||||
{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
|
||||
{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
|
||||
{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 },
|
||||
{"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 },
|
||||
{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 },
|
||||
|
|
@ -773,8 +773,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 },
|
||||
{"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 },
|
||||
{"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
|
||||
{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33|IOCT},
|
||||
{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33|IOCT},
|
||||
{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 },
|
||||
{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
|
||||
{"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 },
|
||||
{"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
|
||||
{"eret", "", 0x42000018, 0xffffffff, NODS, 0, I3_32 },
|
||||
|
|
@ -858,10 +858,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */
|
||||
{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, INSN2_M_FP_D, I1 },
|
||||
{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, INSN2_M_FP_D, I1 },
|
||||
{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
|
||||
{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 },
|
||||
{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
|
||||
{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2 },
|
||||
{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2, IOCT|IOCTP|IOCT2 },
|
||||
{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2 },
|
||||
{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2, IOCT|IOCTP|IOCT2 },
|
||||
{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2 },
|
||||
{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
|
||||
{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 },
|
||||
{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
|
||||
|
|
@ -884,18 +884,18 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I5_33|N55},
|
||||
{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
|
||||
{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1 },
|
||||
{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
|
||||
{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1 },
|
||||
{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 },
|
||||
{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 },
|
||||
{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
|
||||
{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
|
||||
{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */
|
||||
{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
|
||||
{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
|
||||
{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 },
|
||||
{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
|
||||
{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 },
|
||||
{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
|
||||
{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 },
|
||||
{"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */
|
||||
|
|
@ -958,20 +958,20 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"mftc0", "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
|
||||
{"mftc1", "d,T", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 },
|
||||
{"mftc1", "d,E", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 },
|
||||
{"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
|
||||
{"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32, IOCT|IOCTP|IOCT2 },
|
||||
{"mftdsp", "d", 0x41100021, 0xffff07ff, TRAP|WR_d, 0, MT32 },
|
||||
{"mftgpr", "d,t", 0x41000020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 },
|
||||
{"mfthc1", "d,T", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 },
|
||||
{"mfthc1", "d,E", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 },
|
||||
{"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
|
||||
{"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32, IOCT|IOCTP|IOCT2 },
|
||||
{"mfthi", "d", 0x41010021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
|
||||
{"mfthi", "d,*", 0x41010021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
|
||||
{"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
|
||||
{"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
|
||||
{"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, MT32 },
|
||||
{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1|IOCT },
|
||||
{"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32|IOCT},
|
||||
{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32|IOCT},
|
||||
{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 },
|
||||
{"mfc0", "t,+D",0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
|
||||
{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
|
||||
{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 },
|
||||
{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 },
|
||||
{"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 },
|
||||
|
|
@ -1050,9 +1050,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
|
||||
{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
|
||||
{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
|
||||
{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1|IOCT },
|
||||
{"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32|IOCT},
|
||||
{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32|IOCT},
|
||||
{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1 },
|
||||
{"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 },
|
||||
{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 },
|
||||
{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 },
|
||||
{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 },
|
||||
{"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 },
|
||||
|
|
@ -1078,14 +1078,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
|
||||
{"mttc1", "t,S", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 },
|
||||
{"mttc1", "t,G", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 },
|
||||
{"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 },
|
||||
{"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32, IOCT|IOCTP|IOCT2 },
|
||||
{"mttacx", "t", 0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
|
||||
{"mttacx", "t,&", 0x41801021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
|
||||
{"mttdsp", "t", 0x41808021, 0xffe0ffff, TRAP|RD_t, 0, MT32 },
|
||||
{"mttgpr", "t,d", 0x41800020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 },
|
||||
{"mtthc1", "t,S", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 },
|
||||
{"mtthc1", "t,G", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 },
|
||||
{"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 },
|
||||
{"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32, IOCT|IOCTP|IOCT2 },
|
||||
{"mtthi", "t", 0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
|
||||
{"mtthi", "t,&", 0x41800821, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
|
||||
{"mttlo", "t", 0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
|
||||
|
|
@ -1303,10 +1303,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
|
||||
{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 },
|
||||
{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2 },
|
||||
{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2 },
|
||||
{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2 },
|
||||
{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2 },
|
||||
{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 },
|
||||
{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2, IOCT|IOCTP|IOCT2 },
|
||||
{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2 },
|
||||
{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2, IOCT|IOCTP|IOCT2 },
|
||||
{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2, IOCT|IOCTP|IOCT2 },
|
||||
{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
|
||||
{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, INSN2_M_FP_D, I1 },
|
||||
{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, INSN2_M_FP_D, I1 },
|
||||
|
|
@ -1428,18 +1428,18 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"swapw", "t,b", 0x70000014, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
|
||||
{"swapwu", "t,b", 0x70000015, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
|
||||
{"swapd", "t,b", 0x70000016, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
|
||||
{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1 },
|
||||
{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1 },
|
||||
{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
|
||||
{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
|
||||
{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
|
||||
{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
|
||||
{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */
|
||||
{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1 },
|
||||
{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 },
|
||||
{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 },
|
||||
{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 },
|
||||
{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 },
|
||||
{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
|
||||
{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 },
|
||||
{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */
|
||||
|
|
@ -1618,47 +1618,47 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
|
||||
/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
|
||||
instructions so they are here for the latters to take precedence. */
|
||||
{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 },
|
||||
{"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32 },
|
||||
{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
|
||||
{"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32 },
|
||||
{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1 },
|
||||
{"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32 },
|
||||
{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
|
||||
{"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32 },
|
||||
{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 },
|
||||
{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
|
||||
{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 },
|
||||
{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
|
||||
{"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 },
|
||||
{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 },
|
||||
{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
|
||||
{"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 },
|
||||
{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"dmfc2", "t,i", 0x48200000, 0xffe00000, LCD|WR_t|RD_C2, 0, IOCT },
|
||||
{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3 },
|
||||
{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 },
|
||||
{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3, IOCT|IOCTP|IOCT2 },
|
||||
{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64, IOCT|IOCTP|IOCT2 },
|
||||
{"dmtc2", "t,i", 0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, IOCT },
|
||||
{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3 },
|
||||
{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 },
|
||||
{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 },
|
||||
{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 },
|
||||
{"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33 },
|
||||
{"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I33 },
|
||||
{"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33 },
|
||||
{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1 },
|
||||
{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 },
|
||||
{"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33 },
|
||||
{"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33 },
|
||||
{"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33 },
|
||||
{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3, IOCT|IOCTP|IOCT2 },
|
||||
{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64, IOCT|IOCTP|IOCT2 },
|
||||
{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32, IOCT|IOCTP|IOCT2 },
|
||||
{"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33, IOCT|IOCTP|IOCT2 },
|
||||
{"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I33, IOCT|IOCTP|IOCT2 },
|
||||
{"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33, IOCT|IOCTP|IOCT2 },
|
||||
{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32, IOCT|IOCTP|IOCT2 },
|
||||
{"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33, IOCT|IOCTP|IOCT2 },
|
||||
{"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33, IOCT|IOCTP|IOCT2 },
|
||||
{"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33, IOCT|IOCTP|IOCT2 },
|
||||
|
||||
/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
|
||||
instructions, so they are here for the latters to take precedence. */
|
||||
{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1 },
|
||||
{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
|
||||
{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1 },
|
||||
{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
|
||||
{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 },
|
||||
{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
|
||||
{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3 },
|
||||
{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3 },
|
||||
{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 },
|
||||
{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32 },
|
||||
{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 },
|
||||
{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 },
|
||||
{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
|
||||
{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
|
||||
{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3, IOCT|IOCTP|IOCT2 },
|
||||
{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3, IOCT|IOCTP|IOCT2 },
|
||||
{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32, IOCT|IOCTP|IOCT2 },
|
||||
{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32, IOCT|IOCTP|IOCT2 },
|
||||
|
||||
/* Conflicts with the 4650's "mul" instruction. Nobody's using the
|
||||
4010 any more, so move this insn out of the way. If the object
|
||||
|
|
@ -1945,10 +1945,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
|
||||
{"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
|
||||
/* Move bc0* after mftr and mttr to avoid opcode collision. */
|
||||
{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 },
|
||||
{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
|
||||
{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 },
|
||||
{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
|
||||
{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
|
||||
{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
|
||||
/* ST Microelectronics Loongson-2E and -2F. */
|
||||
{"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
|
||||
{"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
|
||||
|
|
@ -2108,14 +2108,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
change the state of the processor and if they do it's up to the
|
||||
user to put in nops as necessary. These are at the end so that the
|
||||
disassembler recognizes more specific versions first. */
|
||||
{"c0", "C", 0x42000000, 0xfe000000, CP, 0, I1 },
|
||||
{"c0", "C", 0x42000000, 0xfe000000, CP, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"c1", "C", 0x46000000, 0xfe000000, FP_S, 0, I1 },
|
||||
{"c2", "C", 0x4a000000, 0xfe000000, CP, 0, I1 },
|
||||
{"c3", "C", 0x4e000000, 0xfe000000, CP, 0, I1 },
|
||||
{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1 },
|
||||
{"c2", "C", 0x4a000000, 0xfe000000, CP, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"c3", "C", 0x4e000000, 0xfe000000, CP, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, INSN2_M_FP_S, I1 },
|
||||
{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1 },
|
||||
{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1 }
|
||||
{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1, IOCT|IOCTP|IOCT2 },
|
||||
};
|
||||
|
||||
#define MIPS_NUM_OPCODES \
|
||||
|
|
|
|||
Loading…
Reference in New Issue