* sim-xcat.h: Delete.
* cgen-mem.h: Delete inclusion of sim-xcat.h. * cgen-sim.h: Ditto. * sim-alu.h: Replace sim-xcat.h with symcat.h. * sim-n-bits.h: Ditto. * sim-n-core.h: Ditto. * sim-n-endian.h: Ditto.
This commit is contained in:
Doug Evans
parent
3aeca4624a
commit
36dbc8bb7c
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@ -109,7 +109,6 @@ sim-utils.c
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sim-utils.h
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sim-watch.c
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sim-watch.h
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sim-xcat.h
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syscall.c
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tconfig.in
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@ -1,3 +1,13 @@
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Mon Feb 23 13:08:35 1998 Doug Evans <devans@canuck.cygnus.com>
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* sim-xcat.h: Delete.
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* cgen-mem.h: Delete inclusion of sim-xcat.h.
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* cgen-sim.h: Ditto.
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* sim-alu.h: Replace sim-xcat.h with symcat.h.
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* sim-n-bits.h: Ditto.
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* sim-n-core.h: Ditto.
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* sim-n-endian.h: Ditto.
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Mon Feb 23 13:19:58 1998 Michael Meissner <meissner@cygnus.com>
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* syscall.c (cb_syscall): Handle short reads, and EOF.
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@ -1,10 +1,8 @@
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/* Memory ops header for CGEN-based simlators.
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Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
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Contributed by Cygnus Solutions.
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This file is machine generated.
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Copyright (C) 1996, 1997 Free Software Foundation, Inc.
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This file is part of the GNU Binutils and/or GDB, the GNU debugger.
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This file is part of the GNU Simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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@ -18,9 +16,7 @@ GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#ifndef CGEN_MEM_H
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#define CGEN_MEM_H
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@ -31,473 +27,131 @@ with this program; if not, write to the Free Software Foundation, Inc.,
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#define MEMOPS_INLINE extern inline
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#endif
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/* Only used in this file. */
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typedef unsigned char *ptr;
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#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
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MEMOPS_INLINE QI
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GETTQI (ptr p)
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{
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if (TARGET_BIG_ENDIAN)
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return p[0];
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else
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return p[0];
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#define DECLARE_GETMEM(mode, size) \
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MEMOPS_INLINE mode \
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XCONCAT2 (GETMEM,mode) (SIM_CPU *cpu, ADDR a) \
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{ \
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PROFILE_COUNT_READ (cpu, a, XCONCAT2 (MODE_,mode)); \
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/* Don't read anything into "unaligned" here. Bad name choice. */\
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return XCONCAT2 (sim_core_read_unaligned_,size) (cpu, NULL_CIA, sim_core_read_map, a); \
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}
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#else
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extern QI GETTQI (ptr);
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#define DECLARE_GETMEM(mode, size) \
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extern mode XCONCAT2 (GETMEM,mode) (SIM_CPU *, ADDR);
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#endif
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DECLARE_GETMEM (QI, 1)
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DECLARE_GETMEM (UQI, 1)
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DECLARE_GETMEM (HI, 2)
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DECLARE_GETMEM (UHI, 2)
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DECLARE_GETMEM (SI, 4)
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DECLARE_GETMEM (USI, 4)
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DECLARE_GETMEM (DI, 8)
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DECLARE_GETMEM (UDI, 8)
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#undef DECLARE_GETMEM
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#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
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MEMOPS_INLINE HI
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GETTHI (ptr p)
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{
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if (TARGET_BIG_ENDIAN)
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return ((p[0] << 8) | p[1]);
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else
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return ((p[1] << 8) | p[0]);
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#define DECLARE_SETMEM(mode, size) \
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MEMOPS_INLINE void \
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XCONCAT2 (SETMEM,mode) (SIM_CPU *cpu, ADDR a, mode val) \
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{ \
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PROFILE_COUNT_WRITE (cpu, a, XCONCAT2 (MODE_,mode)); \
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/* Don't read anything into "unaligned" here. Bad name choice. */ \
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XCONCAT2 (sim_core_write_unaligned_,size) (cpu, NULL_CIA, sim_core_write_map, a, val); \
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}
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#else
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extern HI GETTHI (ptr);
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#define DECLARE_SETMEM(mode, size) \
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extern void XCONCAT2 (SETMEM,mode) (SIM_CPU *, ADDR, mode);
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#endif
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DECLARE_SETMEM (QI, 1)
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DECLARE_SETMEM (UQI, 1)
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DECLARE_SETMEM (HI, 2)
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DECLARE_SETMEM (UHI, 2)
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DECLARE_SETMEM (SI, 4)
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DECLARE_SETMEM (USI, 4)
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DECLARE_SETMEM (DI, 8)
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DECLARE_SETMEM (UDI, 8)
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#undef DECLARE_SETMEM
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#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
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MEMOPS_INLINE SI
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GETTSI (ptr p)
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{
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if (TARGET_BIG_ENDIAN)
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return ((p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3]);
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else
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return ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]);
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#define DECLARE_GETIMEM(mode, size) \
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MEMOPS_INLINE mode \
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XCONCAT2 (GETIMEM,mode) (SIM_CPU *cpu, ADDR a) \
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{ \
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/*PROFILE_COUNT_READ (cpu, a, XCONCAT2 (MODE_,mode));*/ \
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/* Don't read anything into "unaligned" here. Bad name choice. */\
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return XCONCAT2 (sim_core_read_unaligned_,size) (cpu, NULL_CIA, sim_core_execute_map, a); \
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}
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#else
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extern SI GETTSI (ptr);
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#define DECLARE_GETIMEM(mode, size) \
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extern mode XCONCAT2 (GETIMEM,mode) (SIM_CPU *, ADDR);
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#endif
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DECLARE_GETIMEM (UQI, 1)
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DECLARE_GETIMEM (UHI, 2)
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DECLARE_GETIMEM (USI, 4)
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DECLARE_GETIMEM (UDI, 8)
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#undef DECLARE_GETIMEM
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/* GETT<mode>: translate target value at P to host value.
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??? How inefficient is the current implementation? */
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#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
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MEMOPS_INLINE DI
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GETTDI (ptr p)
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{
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if (TARGET_BIG_ENDIAN)
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return MAKEDI ((p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3], (p[4] << 24) | (p[5] << 16) | (p[6] << 8) | p[7]);
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else
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return MAKEDI ((p[7] << 24) | (p[6] << 16) | (p[5] << 8) | p[4], (p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]);
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#define DECLARE_GETT(mode, size) \
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MEMOPS_INLINE mode \
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XCONCAT2 (GETT,mode) (unsigned char *p) \
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{ \
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mode tmp; \
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memcpy (&tmp, p, sizeof (mode)); \
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return XCONCAT2 (T2H_,size) (tmp); \
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}
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#else
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extern DI GETTDI (ptr);
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#define DECLARE_GETT(mode, size) \
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extern mode XCONCAT2 (GETT,mode) (unsigned char *);
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#endif
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DECLARE_GETT (QI, 1)
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DECLARE_GETT (UQI, 1)
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DECLARE_GETT (HI, 2)
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DECLARE_GETT (UHI, 2)
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DECLARE_GETT (SI, 4)
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DECLARE_GETT (USI, 4)
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DECLARE_GETT (DI, 8)
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DECLARE_GETT (UDI, 8)
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#undef DECLARE_GETT
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/* SETT<mode>: translate host value to target value and store at P.
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??? How inefficient is the current implementation? */
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#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
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MEMOPS_INLINE UQI
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GETTUQI (ptr p)
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{
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if (TARGET_BIG_ENDIAN)
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return p[0];
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else
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return p[0];
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#define DECLARE_SETT(mode, size) \
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MEMOPS_INLINE mode \
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XCONCAT2 (SETT,mode) (unsigned char *buf, mode val) \
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{ \
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mode tmp; \
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tmp = XCONCAT2 (H2T_,size) (val); \
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memcpy (buf, &tmp, sizeof (mode)); \
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}
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#else
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extern UQI GETTUQI (ptr);
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#define DECLARE_SETT(mode, size) \
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extern mode XCONCAT2 (GETT,mode) (unsigned char *, mode);
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#endif
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#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
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MEMOPS_INLINE UHI
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GETTUHI (ptr p)
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{
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if (TARGET_BIG_ENDIAN)
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return ((p[0] << 8) | p[1]);
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else
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return ((p[1] << 8) | p[0]);
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}
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#else
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extern UHI GETTUHI (ptr);
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#endif
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DECLARE_SETT (QI, 1)
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DECLARE_SETT (UQI, 1)
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DECLARE_SETT (HI, 2)
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DECLARE_SETT (UHI, 2)
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DECLARE_SETT (SI, 4)
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DECLARE_SETT (USI, 4)
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DECLARE_SETT (DI, 8)
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DECLARE_SETT (UDI, 8)
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#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
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MEMOPS_INLINE USI
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GETTUSI (ptr p)
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{
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if (TARGET_BIG_ENDIAN)
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return ((p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3]);
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else
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return ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]);
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}
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#else
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extern USI GETTUSI (ptr);
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#endif
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#undef DECLARE_SETT
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#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
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MEMOPS_INLINE UDI
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GETTUDI (ptr p)
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{
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if (TARGET_BIG_ENDIAN)
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return MAKEDI ((p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3], (p[4] << 24) | (p[5] << 16) | (p[6] << 8) | p[7]);
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else
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return MAKEDI ((p[7] << 24) | (p[6] << 16) | (p[5] << 8) | p[4], (p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]);
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}
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#else
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extern UDI GETTUDI (ptr);
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#endif
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#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
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MEMOPS_INLINE void
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SETTQI (ptr p, QI val)
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{
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if (TARGET_BIG_ENDIAN)
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do { p[0] = val; } while (0);
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else
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do { p[0] = val; } while (0);
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}
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#else
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extern void SETTQI (ptr, QI);
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#endif
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#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
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MEMOPS_INLINE void
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SETTHI (ptr p, HI val)
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{
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if (TARGET_BIG_ENDIAN)
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do { p[0] = val >> 8; p[1] = val; } while (0);
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else
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do { p[1] = val >> 8; p[0] = val; } while (0);
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}
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#else
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extern void SETTHI (ptr, HI);
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#endif
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#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
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MEMOPS_INLINE void
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SETTSI (ptr p, SI val)
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{
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if (TARGET_BIG_ENDIAN)
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do { p[0] = val >> 24; p[1] = val >> 16; p[2] = val >> 8; p[3] = val; } while (0);
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else
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do { p[3] = val >> 24; p[2] = val >> 16; p[1] = val >> 8; p[0] = val; } while (0);
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}
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#else
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extern void SETTSI (ptr, SI);
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#endif
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|
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#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
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MEMOPS_INLINE void
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SETTDI (ptr p, DI val)
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{
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if (TARGET_BIG_ENDIAN)
|
||||
do { SI t = GETHIDI (val); p[0] = t >> 24; p[1] = t >> 16; p[2] = t >> 8; p[3] = t; t = GETLODI (val); p[4] = t >> 24; p[5] = t >> 16; p[6] = t >> 8; p[7] = t; } while (0);
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else
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do { SI t = GETHIDI (val); p[7] = t >> 24; p[6] = t >> 16; p[5] = t >> 8; p[4] = t; t = GETLODI (val); p[3] = t >> 24; p[2] = t >> 16; p[1] = t >> 8; p[0] = t; } while (0);
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||||
}
|
||||
#else
|
||||
extern void SETTDI (ptr, DI);
|
||||
#endif
|
||||
|
||||
#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
|
||||
MEMOPS_INLINE void
|
||||
SETTUQI (ptr p, UQI val)
|
||||
{
|
||||
if (TARGET_BIG_ENDIAN)
|
||||
do { p[0] = val; } while (0);
|
||||
else
|
||||
do { p[0] = val; } while (0);
|
||||
}
|
||||
#else
|
||||
extern void SETTUQI (ptr, UQI);
|
||||
#endif
|
||||
|
||||
#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
|
||||
MEMOPS_INLINE void
|
||||
SETTUHI (ptr p, UHI val)
|
||||
{
|
||||
if (TARGET_BIG_ENDIAN)
|
||||
do { p[0] = val >> 8; p[1] = val; } while (0);
|
||||
else
|
||||
do { p[1] = val >> 8; p[0] = val; } while (0);
|
||||
}
|
||||
#else
|
||||
extern void SETTUHI (ptr, UHI);
|
||||
#endif
|
||||
|
||||
#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
|
||||
MEMOPS_INLINE void
|
||||
SETTUSI (ptr p, USI val)
|
||||
{
|
||||
if (TARGET_BIG_ENDIAN)
|
||||
do { p[0] = val >> 24; p[1] = val >> 16; p[2] = val >> 8; p[3] = val; } while (0);
|
||||
else
|
||||
do { p[3] = val >> 24; p[2] = val >> 16; p[1] = val >> 8; p[0] = val; } while (0);
|
||||
}
|
||||
#else
|
||||
extern void SETTUSI (ptr, USI);
|
||||
#endif
|
||||
|
||||
#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
|
||||
MEMOPS_INLINE void
|
||||
SETTUDI (ptr p, UDI val)
|
||||
{
|
||||
if (TARGET_BIG_ENDIAN)
|
||||
do { SI t = GETHIDI (val); p[0] = t >> 24; p[1] = t >> 16; p[2] = t >> 8; p[3] = t; t = GETLODI (val); p[4] = t >> 24; p[5] = t >> 16; p[6] = t >> 8; p[7] = t; } while (0);
|
||||
else
|
||||
do { SI t = GETHIDI (val); p[7] = t >> 24; p[6] = t >> 16; p[5] = t >> 8; p[4] = t; t = GETLODI (val); p[3] = t >> 24; p[2] = t >> 16; p[1] = t >> 8; p[0] = t; } while (0);
|
||||
}
|
||||
#else
|
||||
extern void SETTUDI (ptr, UDI);
|
||||
#endif
|
||||
|
||||
|
||||
/* FIXME: Need to merge with sim-core. */
|
||||
/* FIXME: Don't perform >= 4, text section checks if OEA. */
|
||||
#ifndef MEM_CHECK_READ
|
||||
#define MEM_CHECK_READ(addr, type) \
|
||||
((addr) >= 4 /*&& (addr) < STATE_MEM_SIZE (current_state)*/)
|
||||
#endif
|
||||
#ifndef MEM_CHECK_WRITE
|
||||
#define MEM_CHECK_WRITE(addr, type) \
|
||||
((addr) >= 4 /*&& (addr) < STATE_MEM_SIZE (current_state)*/ \
|
||||
&& ((addr) >= STATE_TEXT_END (current_state) \
|
||||
|| (addr) < STATE_TEXT_START (current_state)))
|
||||
#endif
|
||||
#ifndef MEM_CHECK_ALIGNMENT
|
||||
#define MEM_CHECK_ALIGNMENT(addr, type) \
|
||||
(((addr) & (sizeof (type) - 1)) == 0)
|
||||
#endif
|
||||
|
||||
#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
|
||||
MEMOPS_INLINE QI
|
||||
GETMEMQI (SIM_CPU *cpu, ADDR a)
|
||||
{
|
||||
if (! MEM_CHECK_READ (a, QI))
|
||||
{ engine_signal (cpu, SIM_SIGACCESS); }
|
||||
if (! MEM_CHECK_ALIGNMENT (a, QI))
|
||||
{ engine_signal (cpu, SIM_SIGALIGN); }
|
||||
PROFILE_COUNT_READ (cpu, a, MODE_QI);
|
||||
return sim_core_read_1 (CPU_STATE (cpu), sim_core_read_map, a);
|
||||
}
|
||||
#else
|
||||
extern QI GETMEMQI (SIM_CPU *, ADDR);
|
||||
#endif
|
||||
|
||||
#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
|
||||
MEMOPS_INLINE HI
|
||||
GETMEMHI (SIM_CPU *cpu, ADDR a)
|
||||
{
|
||||
if (! MEM_CHECK_READ (a, HI))
|
||||
{ engine_signal (cpu, SIM_SIGACCESS); }
|
||||
if (! MEM_CHECK_ALIGNMENT (a, HI))
|
||||
{ engine_signal (cpu, SIM_SIGALIGN); }
|
||||
PROFILE_COUNT_READ (cpu, a, MODE_HI);
|
||||
return sim_core_read_2 (CPU_STATE (cpu), sim_core_read_map, a);
|
||||
}
|
||||
#else
|
||||
extern HI GETMEMHI (SIM_CPU *, ADDR);
|
||||
#endif
|
||||
|
||||
#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
|
||||
MEMOPS_INLINE SI
|
||||
GETMEMSI (SIM_CPU *cpu, ADDR a)
|
||||
{
|
||||
if (! MEM_CHECK_READ (a, SI))
|
||||
{ engine_signal (cpu, SIM_SIGACCESS); }
|
||||
if (! MEM_CHECK_ALIGNMENT (a, SI))
|
||||
{ engine_signal (cpu, SIM_SIGALIGN); }
|
||||
PROFILE_COUNT_READ (cpu, a, MODE_SI);
|
||||
return sim_core_read_4 (CPU_STATE (cpu), sim_core_read_map, a);
|
||||
}
|
||||
#else
|
||||
extern SI GETMEMSI (SIM_CPU *, ADDR);
|
||||
#endif
|
||||
|
||||
#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
|
||||
MEMOPS_INLINE DI
|
||||
GETMEMDI (SIM_CPU *cpu, ADDR a)
|
||||
{
|
||||
if (! MEM_CHECK_READ (a, DI))
|
||||
{ engine_signal (cpu, SIM_SIGACCESS); }
|
||||
if (! MEM_CHECK_ALIGNMENT (a, DI))
|
||||
{ engine_signal (cpu, SIM_SIGALIGN); }
|
||||
PROFILE_COUNT_READ (cpu, a, MODE_DI);
|
||||
return sim_core_read_8 (CPU_STATE (cpu), sim_core_read_map, a);
|
||||
}
|
||||
#else
|
||||
extern DI GETMEMDI (SIM_CPU *, ADDR);
|
||||
#endif
|
||||
|
||||
#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
|
||||
MEMOPS_INLINE UQI
|
||||
GETMEMUQI (SIM_CPU *cpu, ADDR a)
|
||||
{
|
||||
if (! MEM_CHECK_READ (a, UQI))
|
||||
{ engine_signal (cpu, SIM_SIGACCESS); }
|
||||
if (! MEM_CHECK_ALIGNMENT (a, UQI))
|
||||
{ engine_signal (cpu, SIM_SIGALIGN); }
|
||||
PROFILE_COUNT_READ (cpu, a, MODE_UQI);
|
||||
return sim_core_read_1 (CPU_STATE (cpu), sim_core_read_map, a);
|
||||
}
|
||||
#else
|
||||
extern UQI GETMEMUQI (SIM_CPU *, ADDR);
|
||||
#endif
|
||||
|
||||
#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
|
||||
MEMOPS_INLINE UHI
|
||||
GETMEMUHI (SIM_CPU *cpu, ADDR a)
|
||||
{
|
||||
if (! MEM_CHECK_READ (a, UHI))
|
||||
{ engine_signal (cpu, SIM_SIGACCESS); }
|
||||
if (! MEM_CHECK_ALIGNMENT (a, UHI))
|
||||
{ engine_signal (cpu, SIM_SIGALIGN); }
|
||||
PROFILE_COUNT_READ (cpu, a, MODE_UHI);
|
||||
return sim_core_read_2 (CPU_STATE (cpu), sim_core_read_map, a);
|
||||
}
|
||||
#else
|
||||
extern UHI GETMEMUHI (SIM_CPU *, ADDR);
|
||||
#endif
|
||||
|
||||
#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
|
||||
MEMOPS_INLINE USI
|
||||
GETMEMUSI (SIM_CPU *cpu, ADDR a)
|
||||
{
|
||||
if (! MEM_CHECK_READ (a, USI))
|
||||
{ engine_signal (cpu, SIM_SIGACCESS); }
|
||||
if (! MEM_CHECK_ALIGNMENT (a, USI))
|
||||
{ engine_signal (cpu, SIM_SIGALIGN); }
|
||||
PROFILE_COUNT_READ (cpu, a, MODE_USI);
|
||||
return sim_core_read_4 (CPU_STATE (cpu), sim_core_read_map, a);
|
||||
}
|
||||
#else
|
||||
extern USI GETMEMUSI (SIM_CPU *, ADDR);
|
||||
#endif
|
||||
|
||||
#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
|
||||
MEMOPS_INLINE UDI
|
||||
GETMEMUDI (SIM_CPU *cpu, ADDR a)
|
||||
{
|
||||
if (! MEM_CHECK_READ (a, UDI))
|
||||
{ engine_signal (cpu, SIM_SIGACCESS); }
|
||||
if (! MEM_CHECK_ALIGNMENT (a, UDI))
|
||||
{ engine_signal (cpu, SIM_SIGALIGN); }
|
||||
PROFILE_COUNT_READ (cpu, a, MODE_UDI);
|
||||
return sim_core_read_8 (CPU_STATE (cpu), sim_core_read_map, a);
|
||||
}
|
||||
#else
|
||||
extern UDI GETMEMUDI (SIM_CPU *, ADDR);
|
||||
#endif
|
||||
|
||||
#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
|
||||
MEMOPS_INLINE void
|
||||
SETMEMQI (SIM_CPU *cpu, ADDR a, QI val)
|
||||
{
|
||||
if (! MEM_CHECK_WRITE (a, QI))
|
||||
{ engine_signal (cpu, SIM_SIGACCESS); return; }
|
||||
if (! MEM_CHECK_ALIGNMENT (a, QI))
|
||||
{ engine_signal (cpu, SIM_SIGALIGN); return; }
|
||||
PROFILE_COUNT_WRITE (cpu, a, MODE_QI);
|
||||
sim_core_write_1 (CPU_STATE (cpu), sim_core_read_map, a, val);
|
||||
}
|
||||
#else
|
||||
extern void SETMEMQI (SIM_CPU *, ADDR, QI);
|
||||
#endif
|
||||
|
||||
#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
|
||||
MEMOPS_INLINE void
|
||||
SETMEMHI (SIM_CPU *cpu, ADDR a, HI val)
|
||||
{
|
||||
if (! MEM_CHECK_WRITE (a, HI))
|
||||
{ engine_signal (cpu, SIM_SIGACCESS); return; }
|
||||
if (! MEM_CHECK_ALIGNMENT (a, HI))
|
||||
{ engine_signal (cpu, SIM_SIGALIGN); return; }
|
||||
PROFILE_COUNT_WRITE (cpu, a, MODE_HI);
|
||||
sim_core_write_2 (CPU_STATE (cpu), sim_core_read_map, a, val);
|
||||
}
|
||||
#else
|
||||
extern void SETMEMHI (SIM_CPU *, ADDR, HI);
|
||||
#endif
|
||||
|
||||
#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
|
||||
MEMOPS_INLINE void
|
||||
SETMEMSI (SIM_CPU *cpu, ADDR a, SI val)
|
||||
{
|
||||
if (! MEM_CHECK_WRITE (a, SI))
|
||||
{ engine_signal (cpu, SIM_SIGACCESS); return; }
|
||||
if (! MEM_CHECK_ALIGNMENT (a, SI))
|
||||
{ engine_signal (cpu, SIM_SIGALIGN); return; }
|
||||
PROFILE_COUNT_WRITE (cpu, a, MODE_SI);
|
||||
sim_core_write_4 (CPU_STATE (cpu), sim_core_read_map, a, val);
|
||||
}
|
||||
#else
|
||||
extern void SETMEMSI (SIM_CPU *, ADDR, SI);
|
||||
#endif
|
||||
|
||||
#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
|
||||
MEMOPS_INLINE void
|
||||
SETMEMDI (SIM_CPU *cpu, ADDR a, DI val)
|
||||
{
|
||||
if (! MEM_CHECK_WRITE (a, DI))
|
||||
{ engine_signal (cpu, SIM_SIGACCESS); return; }
|
||||
if (! MEM_CHECK_ALIGNMENT (a, DI))
|
||||
{ engine_signal (cpu, SIM_SIGALIGN); return; }
|
||||
PROFILE_COUNT_WRITE (cpu, a, MODE_DI);
|
||||
sim_core_write_8 (CPU_STATE (cpu), sim_core_read_map, a, val);
|
||||
}
|
||||
#else
|
||||
extern void SETMEMDI (SIM_CPU *, ADDR, DI);
|
||||
#endif
|
||||
|
||||
#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
|
||||
MEMOPS_INLINE void
|
||||
SETMEMUQI (SIM_CPU *cpu, ADDR a, UQI val)
|
||||
{
|
||||
if (! MEM_CHECK_WRITE (a, UQI))
|
||||
{ engine_signal (cpu, SIM_SIGACCESS); return; }
|
||||
if (! MEM_CHECK_ALIGNMENT (a, UQI))
|
||||
{ engine_signal (cpu, SIM_SIGALIGN); return; }
|
||||
PROFILE_COUNT_WRITE (cpu, a, MODE_UQI);
|
||||
sim_core_write_1 (CPU_STATE (cpu), sim_core_read_map, a, val);
|
||||
}
|
||||
#else
|
||||
extern void SETMEMUQI (SIM_CPU *, ADDR, UQI);
|
||||
#endif
|
||||
|
||||
#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
|
||||
MEMOPS_INLINE void
|
||||
SETMEMUHI (SIM_CPU *cpu, ADDR a, UHI val)
|
||||
{
|
||||
if (! MEM_CHECK_WRITE (a, UHI))
|
||||
{ engine_signal (cpu, SIM_SIGACCESS); return; }
|
||||
if (! MEM_CHECK_ALIGNMENT (a, UHI))
|
||||
{ engine_signal (cpu, SIM_SIGALIGN); return; }
|
||||
PROFILE_COUNT_WRITE (cpu, a, MODE_UHI);
|
||||
sim_core_write_2 (CPU_STATE (cpu), sim_core_read_map, a, val);
|
||||
}
|
||||
#else
|
||||
extern void SETMEMUHI (SIM_CPU *, ADDR, UHI);
|
||||
#endif
|
||||
|
||||
#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
|
||||
MEMOPS_INLINE void
|
||||
SETMEMUSI (SIM_CPU *cpu, ADDR a, USI val)
|
||||
{
|
||||
if (! MEM_CHECK_WRITE (a, USI))
|
||||
{ engine_signal (cpu, SIM_SIGACCESS); return; }
|
||||
if (! MEM_CHECK_ALIGNMENT (a, USI))
|
||||
{ engine_signal (cpu, SIM_SIGALIGN); return; }
|
||||
PROFILE_COUNT_WRITE (cpu, a, MODE_USI);
|
||||
sim_core_write_4 (CPU_STATE (cpu), sim_core_read_map, a, val);
|
||||
}
|
||||
#else
|
||||
extern void SETMEMUSI (SIM_CPU *, ADDR, USI);
|
||||
#endif
|
||||
|
||||
#if defined (__GNUC__) || defined (MEMOPS_DEFINE_INLINE)
|
||||
MEMOPS_INLINE void
|
||||
SETMEMUDI (SIM_CPU *cpu, ADDR a, UDI val)
|
||||
{
|
||||
if (! MEM_CHECK_WRITE (a, UDI))
|
||||
{ engine_signal (cpu, SIM_SIGACCESS); return; }
|
||||
if (! MEM_CHECK_ALIGNMENT (a, UDI))
|
||||
{ engine_signal (cpu, SIM_SIGALIGN); return; }
|
||||
PROFILE_COUNT_WRITE (cpu, a, MODE_UDI);
|
||||
sim_core_write_8 (CPU_STATE (cpu), sim_core_read_map, a, val);
|
||||
}
|
||||
#else
|
||||
extern void SETMEMUDI (SIM_CPU *, ADDR, UDI);
|
||||
#endif
|
||||
|
||||
#endif /* CGEN_MEMS_H */
|
||||
#endif /* CGEN_MEM_H */
|
||||
|
|
|
|||
|
|
@ -21,8 +21,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
#ifndef CGEN_SIM_H
|
||||
#define CGEN_SIM_H
|
||||
|
||||
#include "sim-xcat.h"
|
||||
|
||||
#define PC CPU (h_pc)
|
||||
|
||||
/* Instruction field support macros. */
|
||||
|
|
@ -44,49 +42,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
|||
/* Forward decls. Defined in the machine generated arch.h and cpu.h files. */
|
||||
typedef struct argbuf ARGBUF;
|
||||
typedef struct scache SCACHE;
|
||||
typedef struct parallel_exec PARALLEL_EXEC;
|
||||
|
||||
/* Types of the machine generated extract and semantic fns. */
|
||||
typedef void (EXTRACT_FN) (SIM_CPU *, PCADDR, insn_t, ARGBUF *);
|
||||
/* ??? READ_FN isn't currently used anywhere, we always use a switch. */
|
||||
typedef void (READ_FN) (SIM_CPU *, PCADDR, insn_t, PARALLEL_EXEC *);
|
||||
/*typedef CIA (SEMANTIC_FN) (SEM_ARG);*/
|
||||
typedef PCADDR (SEMANTIC_FN) (SIM_CPU *, ARGBUF *);
|
||||
#if 0 /* wip */
|
||||
typedef void (EXTRACT_CACHE_FN) (SIM_CPU *, PCADDR, insn_t, ARGBUF *);
|
||||
#endif
|
||||
typedef PCADDR (SEMANTIC_CACHE_FN) (SIM_CPU *, SCACHE *);
|
||||
|
||||
typedef struct {
|
||||
/* Using cgen_insn_type requires <cpu>-opc.h. */
|
||||
int /*enum cgen_insn_type*/ insn_type;
|
||||
const struct cgen_insn *opcode;
|
||||
EXTRACT_FN *extract;
|
||||
#ifdef HAVE_PARALLEL_EXEC
|
||||
#ifdef __GNUC__
|
||||
void *read;
|
||||
#else
|
||||
int read;
|
||||
#endif
|
||||
#endif
|
||||
SEMANTIC_FN *semantic;
|
||||
SEMANTIC_CACHE_FN *semantic_fast;
|
||||
#if WITH_SEM_SWITCH_FULL && defined (__GNUC__)
|
||||
/* Set at runtime. */
|
||||
void *sem_full_lab;
|
||||
#endif
|
||||
#if WITH_SEM_SWITCH_FAST && defined (__GNUC__)
|
||||
/* Set at runtime. */
|
||||
void *semantic_lab; /* FIXME: Rename to sem_fast_lab. */
|
||||
#endif
|
||||
} DECODE;
|
||||
|
||||
/* Execution support.
|
||||
|
||||
Semantic functions come in two versions.
|
||||
One that uses the cache, and one that doesn't.
|
||||
??? The one that doesn't may eventually be thrown away or replaced with
|
||||
something else. */
|
||||
typedef struct parexec PAREXEC;
|
||||
|
||||
#ifdef SCACHE_P
|
||||
|
||||
|
|
@ -108,6 +64,57 @@ typedef ARGBUF *SEM_ARG;
|
|||
|
||||
#endif /* ! SCACHE_P */
|
||||
|
||||
/* Semantic functions come in two versions on two axis:
|
||||
fast and full (featured), and using or not using scache.
|
||||
A full featured simulator is always provided. --enable-sim-fast includes
|
||||
support for fast execution by duplicating the semantic code but leaving
|
||||
out all features like tracing and profiling.
|
||||
Using the scache is selected with --enable-sim-scache. */
|
||||
/* FIXME: --enable-sim-fast not implemented yet. */
|
||||
|
||||
/* Types of the machine generated extract and semantic fns. */
|
||||
/* FIXME: Eventually conditionalize EXTRACT_FN on WITH_SCACHE. */
|
||||
typedef void (EXTRACT_FN) (SIM_CPU *, PCADDR, insn_t, ARGBUF *);
|
||||
#if WITH_SCACHE
|
||||
#ifdef HAVE_PARALLEL_EXEC
|
||||
typedef CIA (SEMANTIC_FN) (SIM_CPU *, SCACHE *, PAREXEC *);
|
||||
#else
|
||||
typedef CIA (SEMANTIC_FN) (SIM_CPU *, SCACHE *);
|
||||
#endif
|
||||
#else /* ! WITH_SCACHE */
|
||||
#ifdef HAVE_PARALLEL_EXEC
|
||||
typedef CIA (SEMANTIC_FN) (SIM_CPU *, ARGBUF *, PAREXEC *);
|
||||
#else
|
||||
typedef CIA (SEMANTIC_FN) (SIM_CPU *, ARGBUF *);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* DECODE struct, there is one per instruction. */
|
||||
|
||||
typedef struct {
|
||||
/* Using cgen_insn_type requires <cpu>-opc.h. */
|
||||
int /*enum cgen_insn_type*/ insn_type;
|
||||
const struct cgen_insn *opcode;
|
||||
EXTRACT_FN *extract;
|
||||
#ifdef HAVE_PARALLEL_EXEC
|
||||
#ifdef __GNUC__
|
||||
void *read;
|
||||
#else
|
||||
int read;
|
||||
#endif
|
||||
#endif
|
||||
SEMANTIC_FN *semantic;
|
||||
SEMANTIC_FN *semantic_fast;
|
||||
#if WITH_SEM_SWITCH_FULL && defined (__GNUC__)
|
||||
/* Set at runtime. */
|
||||
void *sem_full_lab;
|
||||
#endif
|
||||
#if WITH_SEM_SWITCH_FAST && defined (__GNUC__)
|
||||
/* Set at runtime. */
|
||||
void *semantic_lab; /* FIXME: Rename to sem_fast_lab. */
|
||||
#endif
|
||||
} DECODE;
|
||||
|
||||
/* Scache data for each cpu. */
|
||||
|
||||
typedef struct cpu_scache {
|
||||
|
|
@ -182,17 +189,16 @@ do { \
|
|||
#define EXEC_SEQUENCE 0
|
||||
#define EXEC_PARALLEL 1
|
||||
|
||||
/* These are used so that we can compile two copies of the semantic code,
|
||||
one with full feature support and one without. */
|
||||
/* FIXME: Eventually delete extraction if not using scache. */
|
||||
#define EX_FN_NAME(cpu,fn) XCONCAT3 (cpu,_ex_,fn)
|
||||
#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)
|
||||
|
||||
#ifdef SCACHE_P
|
||||
|
||||
#define CIA_ADDR(cia) (cia)
|
||||
|
||||
/* These are used so that we can compile two copies of the semantic code,
|
||||
one with scache support and one without. */
|
||||
/* FIXME: Do we want _ex_ or _exc_? */
|
||||
/*#define EX_FN_NAME(cpu,fn) XCONCAT3 (cpu,_exc_,fn)*/
|
||||
#define EX_FN_NAME(cpu,fn) XCONCAT3 (cpu,_ex_,fn)
|
||||
#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semc_,fn)
|
||||
|
||||
/* extract.c support */
|
||||
/* scache_unset is a cache entry that is never used.
|
||||
It's raison d'etre is so BRANCH_VIA_CACHE doesn't have to test for
|
||||
|
|
@ -215,11 +221,6 @@ do { (fld) = (val); } while (0)
|
|||
|
||||
#define CIA_ADDR(cia) (cia)
|
||||
|
||||
/* These are used so that we can compile two copies of the semantic code,
|
||||
one with scache support and one without. */
|
||||
#define EX_FN_NAME(cpu,fn) XCONCAT3 (cpu,_ex_,fn)
|
||||
#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)
|
||||
|
||||
/* extract.c support */
|
||||
#define RECORD_IADDR(fld, val) \
|
||||
do { (fld) = (val); } while (0)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -26,7 +26,15 @@
|
|||
#define M N
|
||||
#endif
|
||||
|
||||
#include "sim-xcat.h"
|
||||
/* N: The number of bytes of data to transfer.
|
||||
M: The number of bytes in the type used to transfer the data */
|
||||
|
||||
#if (N > M)
|
||||
#error "N (nr bytes of data) must be <= M (nr of bytes in data type)"
|
||||
#endif
|
||||
|
||||
|
||||
#include "symcat.h"
|
||||
|
||||
/* NOTE: see end of file for #undef of these macros */
|
||||
|
||||
|
|
@ -43,6 +51,14 @@
|
|||
#define sim_core_write_unaligned_N XCONCAT2(sim_core_write_unaligned_,N)
|
||||
#define sim_core_write_misaligned_N XCONCAT2(sim_core_write_misaligned_,N)
|
||||
#define sim_core_trace_M XCONCAT2(sim_core_trace_,M)
|
||||
#define sim_core_dummy_M XCONCAT2(sim_core_dummy_,M)
|
||||
|
||||
|
||||
#if (M == N && N > 1)
|
||||
/* dummy variable used as a return value when nothing else is
|
||||
available and the compiler is complaining */
|
||||
static unsigned_M sim_core_dummy_M;
|
||||
#endif
|
||||
|
||||
|
||||
/* TAGS: sim_core_trace_1 sim_core_trace_2 */
|
||||
|
|
@ -148,7 +164,7 @@ sim_core_read_aligned_N(sim_cpu *cpu,
|
|||
#if (WITH_DEVICES)
|
||||
if (WITH_CALLBACK_MEMORY && mapping->device != NULL) {
|
||||
unsigned_M data;
|
||||
if (device_io_read_buffer (mapping->device, &data, mapping->space, addr, N) != N)
|
||||
if (device_io_read_buffer (mapping->device, &data, mapping->space, addr, N, cpu, cia) != N)
|
||||
device_error (mapping->device, "internal error - %s - io_read_buffer should not fail",
|
||||
XSTRING (sim_core_read_aligned_N));
|
||||
val = T2H_M (data);
|
||||
|
|
@ -209,10 +225,7 @@ sim_core_read_unaligned_N(sim_cpu *cpu,
|
|||
"internal error - %s - bad switch",
|
||||
XSTRING (sim_core_read_unaligned_N));
|
||||
/* to keep some compilers happy, we return a dummy */
|
||||
{
|
||||
unsigned_M val[1] = { 0 };
|
||||
return val[0];
|
||||
}
|
||||
return sim_core_dummy_M;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
@ -372,5 +385,6 @@ sim_core_write_misaligned_N(sim_cpu *cpu,
|
|||
#undef sim_core_write_unaligned_N
|
||||
#undef sim_core_write_misaligned_N
|
||||
#undef sim_core_trace_M
|
||||
#undef sim_core_dummy_M
|
||||
#undef M
|
||||
#undef N
|
||||
|
|
|
|||
|
|
@ -1,45 +0,0 @@
|
|||
/* This file is part of the program GDB.
|
||||
|
||||
Copyright (C) 1997, Free Software Foundation, Inc.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
|
||||
*/
|
||||
|
||||
|
||||
/* from Michael Meissner, macro's to handle concating symbols better */
|
||||
|
||||
#ifndef _SIM_XCAT_H_
|
||||
#define _SIM_XCAT_H_
|
||||
|
||||
#if defined __STDC__ || defined ALMOST_STDC
|
||||
#define CONCAT2(a,b) a##b
|
||||
#define CONCAT3(a,b,c) a##b##c
|
||||
#define CONCAT4(a,b,c,d) a##b##c##d
|
||||
#define STRINGX(s) #s
|
||||
#else
|
||||
#define CONCAT2(a,b) a/**/b
|
||||
#define CONCAT3(a,b,c) a/**/b/**/c
|
||||
#define CONCAT4(a,b,c,d) a/**/b/**/c/**/d
|
||||
#define STRINGX(s) "?"
|
||||
#endif
|
||||
|
||||
#define XCONCAT2(a,b) CONCAT2(a,b)
|
||||
#define XCONCAT3(a,b,c) CONCAT3(a,b,c)
|
||||
#define XCONCAT4(a,b,c,d) CONCAT4(a,b,c,d)
|
||||
|
||||
#define XSTRING(s) STRINGX(s)
|
||||
|
||||
#endif _SIM_XCAT_H_
|
||||
Loading…
Reference in New Issue