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[AArch64] BFD_RELOC_AARCH64_TLSLE_ADD_LO12 should enable overflow check 

BFD_RELOC_AARCH64_TLSLE_ADD_LO12 is used to generate simplest
one-instruction addressing for TLS LE model when tls size is smaller
4K. Linker need to make sure there is no TLS offset overflow.

2015-06-01  Jiong Wang  <jiong.wang@arm.com>

bfd/
  * elfnn-aarch64.c (elfNN_aarch64_howto_table): Set overflow type to
  complain_overflow_unsigned for BFD_RELOC_AARCH64_TLSLE_ADD_LO12.
  * elfxx-aarch64.c (_bfd_aarch64_elf_resolve_relocation): Don't use
  PGOFF for BFD_RELOC_AARCH64_TLSLE_ADD_LO12, that will mask off all
  potential high overflowed bits.

ld/testsuite/
  * ld-aarch64/tprel_add_lo12_overflow.s: New testcase.
  * ld-aarch64/tprel_add_lo12_overflow.d: Nex expectation file.
  * ld-aarch64/aarch64-elf.exp: Run new testcase.
This commit is contained in:
Jiong Wang 2015-06-01 10:31:38 +01:00
parent 99ad26cb0d
commit 36e6c1400b
7 changed files with 48 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
bfd/ChangeLog
View File

@ -1,3 +1,10 @@
2015-06-01 Jiong Wang <jiong.wang@arm.com>
* elfnn-aarch64.c (elfNN_aarch64_howto_table): Set overflow type to
complain_overflow_unsigned for BFD_RELOC_AARCH64_TLSLE_ADD_LO12.
* elfxx-aarch64.c (_bfd_aarch64_elf_resolve_relocation): Don't use
PGOFF for BFD_RELOC_AARCH64_TLSLE_ADD_LO12.
2015-06-01 Jiong Wang <jiong.wang@arm.com>
* elfnn-aarch64.c (aarch64_reloc_got_type): Support

2
bfd/elfnn-aarch64.c
View File

@ -1083,7 +1083,7 @@ static reloc_howto_type elfNN_aarch64_howto_table[] =
12, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
complain_overflow_unsigned, /* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
AARCH64_R_STR (TLSLE_ADD_TPREL_LO12), /* name */
FALSE, /* partial_inplace */

5
bfd/elfxx-aarch64.c
View File

@ -435,11 +435,14 @@ _bfd_aarch64_elf_resolve_relocation (bfd_reloc_code_real_type r_type,
case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
value = PG_OFFSET (value + addend);
break;
case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
value = value + addend;
break;
case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
value = (value + addend) & (bfd_vma) 0xffff0000;

6
ld/testsuite/ChangeLog
View File

@ -1,3 +1,9 @@
2015-06-01 Jiong Wang <jiong.wang@arm.com>
* ld-aarch64/tprel_add_lo12_overflow.s: New testcase.
* ld-aarch64/tprel_add_lo12_overflow.d: Nex expectation file.
* ld-aarch64/aarch64-elf.exp: Run new testcase.
2015-06-01 Jiong Wang <jiong.wang@arm.com>
* ld-aarch64/emit-relocs-313.s: New test file.

1
ld/testsuite/ld-aarch64/aarch64-elf.exp
View File

@ -146,6 +146,7 @@ run_dump_test "gc-relocs-257-dyn"
run_dump_test "gc-relocs-257"
run_dump_test "pr17415"
run_dump_test "tprel_g2_overflow"
run_dump_test "tprel_add_lo12_overflow"
# ifunc tests
run_dump_test "ifunc-1"

6
ld/testsuite/ld-aarch64/tprel_add_lo12_overflow.d Normal file
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@ -0,0 +1,6 @@
#name: TLS offset out of range - TPREL_ADD_LO12
#source: tprel_add_lo12_overflow.s
#as:
#ld: -e0
#error: .*\(.text\+0x\d+\): relocation truncated to fit: R_AARCH64_TLSLE_ADD_TPREL_LO12 against symbol `i' .*

23
ld/testsuite/ld-aarch64/tprel_add_lo12_overflow.s Normal file
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@ -0,0 +1,23 @@
.cpu generic
.global ff
.section .tdata,"awT",%progbits
.align 2
.type ff, %object
# Maximum 12bit - 16byte TCB header is the upper limit
# for tprel_add_lo12
.size ff, 4096 - 16
ff:
.zero 4096 - 16
.global i
.type i, %object
.size i, 4
i:
.zero 4
.text
.align 2
.global main
.type main, %function
main:
add x0, x0, #:tprel_lo12:i
ret
.size main, .-main