2002-03-19 Chris Demetriou <cgd@broadcom.com>
* cp1.c: Fix many formatting issues.
This commit is contained in:
Chris Demetriou
parent
07892c0b5a
commit
37d146fa1d
|
|
@ -1,3 +1,7 @@
|
|||
2002-03-19 Chris Demetriou <cgd@broadcom.com>
|
||||
|
||||
* cp1.c: Fix many formatting issues.
|
||||
|
||||
2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
|
||||
|
||||
* cp1.c (fpu_format_name): New function to replace...
|
||||
|
|
|
|||
216
sim/mips/cp1.c
216
sim/mips/cp1.c
|
|
@ -51,8 +51,8 @@
|
|||
*/
|
||||
|
||||
/* Extract sign-bit: */
|
||||
#define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
|
||||
#define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
|
||||
#define FP_S_s(v) (((v) & (((unsigned) 1) << 31)) ? 1 : 0)
|
||||
#define FP_D_s(v) (((v) & (((uword64) 1) << 63)) ? 1 : 0)
|
||||
/* Extract biased exponent: */
|
||||
#define FP_S_be(v) (((v) >> 23) & 0xFF)
|
||||
#define FP_D_be(v) (((v) >> 52) & 0x7FF)
|
||||
|
|
@ -60,8 +60,8 @@
|
|||
#define FP_S_e(v) (FP_S_be (v) - 0x7F)
|
||||
#define FP_D_e(v) (FP_D_be (v) - 0x3FF)
|
||||
/* Extract complete fraction field: */
|
||||
#define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
|
||||
#define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
|
||||
#define FP_S_f(v) ((v) & ~(((unsigned) 0x1FF) << 23))
|
||||
#define FP_D_f(v) ((v) & ~(((uword64) 0xFFF) << 52))
|
||||
/* Extract numbered fraction bit: */
|
||||
#define FP_S_fb(b, v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
|
||||
#define FP_D_fb(b, v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
|
||||
|
|
@ -69,12 +69,12 @@
|
|||
/* Explicit QNaN values used when value required: */
|
||||
#define FPQNaN_SINGLE (0x7FBFFFFF)
|
||||
#define FPQNaN_WORD (0x7FFFFFFF)
|
||||
#define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
|
||||
#define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
|
||||
#define FPQNaN_DOUBLE ((((uword64) 0x7FF7FFFF) << 32) | 0xFFFFFFFF)
|
||||
#define FPQNaN_LONG ((((uword64) 0x7FFFFFFF) << 32) | 0xFFFFFFFF)
|
||||
|
||||
/* Explicit Infinity values used when required: */
|
||||
#define FPINF_SINGLE (0x7F800000)
|
||||
#define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
|
||||
#define FPINF_DOUBLE ((((uword64) 0x7FF00000) << 32) | 0x00000000)
|
||||
|
||||
static const char *fpu_format_name (FP_formats fmt);
|
||||
#ifdef DEBUG
|
||||
|
|
@ -93,6 +93,7 @@ value_fpr (SIM_DESC sd,
|
|||
|
||||
/* Treat unused register values, as fixed-point 64bit values: */
|
||||
if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown))
|
||||
{
|
||||
#if 1
|
||||
/* If request to read data as "uninterpreted", then use the current
|
||||
encoding: */
|
||||
|
|
@ -100,22 +101,30 @@ value_fpr (SIM_DESC sd,
|
|||
#else
|
||||
fmt = fmt_long;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* For values not yet accessed, set to the desired format: */
|
||||
if (FPR_STATE[fpr] == fmt_uninterpreted) {
|
||||
if (FPR_STATE[fpr] == fmt_uninterpreted)
|
||||
{
|
||||
FPR_STATE[fpr] = fmt;
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr, fpu_format_name (fmt));
|
||||
printf ("DBG: Register %d was fmt_uninterpreted. Now %s\n", fpr,
|
||||
fpu_format_name (fmt));
|
||||
#endif /* DEBUG */
|
||||
}
|
||||
if (fmt != FPR_STATE[fpr]) {
|
||||
sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr, fpu_format_name (FPR_STATE[fpr]), fpu_format_name (fmt),pr_addr(cia));
|
||||
if (fmt != FPR_STATE[fpr])
|
||||
{
|
||||
sim_io_eprintf (sd, "FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",
|
||||
fpr, fpu_format_name (FPR_STATE[fpr]),
|
||||
fpu_format_name (fmt), pr_addr (cia));
|
||||
FPR_STATE[fpr] = fmt_unknown;
|
||||
}
|
||||
|
||||
if (FPR_STATE[fpr] == fmt_unknown) {
|
||||
if (FPR_STATE[fpr] == fmt_unknown)
|
||||
{
|
||||
/* Set QNaN value: */
|
||||
switch (fmt) {
|
||||
switch (fmt)
|
||||
{
|
||||
case fmt_single:
|
||||
value = FPQNaN_SINGLE;
|
||||
break;
|
||||
|
|
@ -136,8 +145,11 @@ value_fpr (SIM_DESC sd,
|
|||
err = -1;
|
||||
break;
|
||||
}
|
||||
} else if (SizeFGR() == 64) {
|
||||
switch (fmt) {
|
||||
}
|
||||
else if (SizeFGR () == 64)
|
||||
{
|
||||
switch (fmt)
|
||||
{
|
||||
case fmt_single:
|
||||
case fmt_word:
|
||||
value = (FGR[fpr] & 0xFFFFFFFF);
|
||||
|
|
@ -153,8 +165,11 @@ value_fpr (SIM_DESC sd,
|
|||
err = -1;
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
switch (fmt) {
|
||||
}
|
||||
else
|
||||
{
|
||||
switch (fmt)
|
||||
{
|
||||
case fmt_single:
|
||||
case fmt_word:
|
||||
value = (FGR[fpr] & 0xFFFFFFFF);
|
||||
|
|
@ -163,14 +178,19 @@ value_fpr (SIM_DESC sd,
|
|||
case fmt_uninterpreted:
|
||||
case fmt_double:
|
||||
case fmt_long:
|
||||
if ((fpr & 1) == 0) { /* even registers only */
|
||||
if ((fpr & 1) == 0)
|
||||
{
|
||||
/* even registers only */
|
||||
#ifdef DEBUG
|
||||
printf ("DBG: ValueFPR: FGR[%d] = %s, FGR[%d] = %s\n",
|
||||
fpr + 1, pr_uword64 ((uword64) FGR[fpr+1]),
|
||||
fpr, pr_uword64 ((uword64) FGR[fpr]));
|
||||
#endif
|
||||
value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF));
|
||||
} else {
|
||||
value = ((((uword64) FGR[fpr+1]) << 32)
|
||||
| (FGR[fpr] & 0xFFFFFFFF));
|
||||
}
|
||||
else
|
||||
{
|
||||
SignalException (ReservedInstruction, 0);
|
||||
}
|
||||
break;
|
||||
|
|
@ -185,7 +205,9 @@ value_fpr (SIM_DESC sd,
|
|||
SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR ()");
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr, fpu_format_name (fmt),pr_uword64(value),pr_addr(cia),SizeFGR());
|
||||
printf ("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR () = %d\n",
|
||||
fpr, fpu_format_name (fmt), pr_uword64 (value), pr_addr (cia),
|
||||
SizeFGR ());
|
||||
#endif /* DEBUG */
|
||||
|
||||
return (value);
|
||||
|
|
@ -202,17 +224,22 @@ store_fpr (SIM_DESC sd,
|
|||
int err = 0;
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d,\n",fpr, fpu_format_name (fmt),pr_uword64(value),pr_addr(cia),SizeFGR());
|
||||
printf ("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR () = %d, \n",
|
||||
fpr, fpu_format_name (fmt), pr_uword64 (value), pr_addr (cia),
|
||||
SizeFGR ());
|
||||
#endif /* DEBUG */
|
||||
|
||||
if (SizeFGR() == 64) {
|
||||
switch (fmt) {
|
||||
if (SizeFGR () == 64)
|
||||
{
|
||||
switch (fmt)
|
||||
{
|
||||
case fmt_uninterpreted_32:
|
||||
fmt = fmt_uninterpreted;
|
||||
case fmt_single :
|
||||
case fmt_word :
|
||||
if (STATE_VERBOSE_P (SD))
|
||||
sim_io_eprintf (SD, "Warning: PC 0x%s: interp.c store_fpr DEADCODE\n",
|
||||
sim_io_eprintf (SD,
|
||||
"Warning: PC 0x%s: interp.c store_fpr DEADCODE\n",
|
||||
pr_addr (cia));
|
||||
FGR[fpr] = (((uword64) 0xDEADC0DE << 32) | (value & 0xFFFFFFFF));
|
||||
FPR_STATE[fpr] = fmt;
|
||||
|
|
@ -232,8 +259,11 @@ store_fpr (SIM_DESC sd,
|
|||
err = -1;
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
switch (fmt) {
|
||||
}
|
||||
else
|
||||
{
|
||||
switch (fmt)
|
||||
{
|
||||
case fmt_uninterpreted_32:
|
||||
fmt = fmt_uninterpreted;
|
||||
case fmt_single :
|
||||
|
|
@ -247,12 +277,16 @@ store_fpr (SIM_DESC sd,
|
|||
case fmt_uninterpreted:
|
||||
case fmt_double :
|
||||
case fmt_long :
|
||||
if ((fpr & 1) == 0) { /* even register number only */
|
||||
if ((fpr & 1) == 0)
|
||||
{
|
||||
/* even register number only */
|
||||
FGR[fpr+1] = (value >> 32);
|
||||
FGR[fpr] = (value & 0xFFFFFFFF);
|
||||
FPR_STATE[fpr + 1] = fmt;
|
||||
FPR_STATE[fpr] = fmt;
|
||||
} else {
|
||||
}
|
||||
else
|
||||
{
|
||||
FPR_STATE[fpr] = fmt_unknown;
|
||||
FPR_STATE[fpr + 1] = fmt_unknown;
|
||||
SignalException (ReservedInstruction, 0);
|
||||
|
|
@ -274,7 +308,8 @@ store_fpr (SIM_DESC sd,
|
|||
SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR ()");
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_uword64(FGR[fpr]), fpu_format_name (fmt));
|
||||
printf ("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",
|
||||
fpr, pr_uword64 (FGR[fpr]), fpu_format_name (fmt));
|
||||
#endif /* DEBUG */
|
||||
|
||||
return;
|
||||
|
|
@ -286,7 +321,8 @@ NaN(op,fmt)
|
|||
FP_formats fmt;
|
||||
{
|
||||
int boolean = 0;
|
||||
switch (fmt) {
|
||||
switch (fmt)
|
||||
{
|
||||
case fmt_single:
|
||||
case fmt_word:
|
||||
{
|
||||
|
|
@ -309,7 +345,8 @@ NaN(op,fmt)
|
|||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op), fpu_format_name (fmt));
|
||||
printf ("DBG: NaN: returning %d for 0x%s (format = %s)\n",
|
||||
boolean, pr_addr (op), fpu_format_name (fmt));
|
||||
#endif /* DEBUG */
|
||||
|
||||
return (boolean);
|
||||
|
|
@ -323,10 +360,12 @@ Infinity(op,fmt)
|
|||
int boolean = 0;
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Infinity: format %s 0x%s\n", fpu_format_name (fmt),pr_addr(op));
|
||||
printf ("DBG: Infinity: format %s 0x%s\n",
|
||||
fpu_format_name (fmt), pr_addr (op));
|
||||
#endif /* DEBUG */
|
||||
|
||||
switch (fmt) {
|
||||
switch (fmt)
|
||||
{
|
||||
case fmt_single:
|
||||
{
|
||||
sim_fpu wop;
|
||||
|
|
@ -342,12 +381,14 @@ Infinity(op,fmt)
|
|||
break;
|
||||
}
|
||||
default:
|
||||
printf("DBG: TODO: unrecognised format (%s) for Infinity check\n", fpu_format_name (fmt));
|
||||
printf ("DBG: TODO: unrecognised format (%s) for Infinity check\n",
|
||||
fpu_format_name (fmt));
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op), fpu_format_name (fmt));
|
||||
printf ("DBG: Infinity: returning %d for 0x%s (format = %s)\n",
|
||||
boolean, pr_addr (op), fpu_format_name (fmt));
|
||||
#endif /* DEBUG */
|
||||
|
||||
return (boolean);
|
||||
|
|
@ -364,11 +405,13 @@ Less(op1,op2,fmt)
|
|||
/* Argument checking already performed by the FPCOMPARE code */
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n", fpu_format_name (fmt),pr_addr(op1),pr_addr(op2));
|
||||
printf ("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",
|
||||
fpu_format_name (fmt), pr_addr (op1), pr_addr (op2));
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* The format type should already have been checked: */
|
||||
switch (fmt) {
|
||||
switch (fmt)
|
||||
{
|
||||
case fmt_single:
|
||||
{
|
||||
sim_fpu wop1;
|
||||
|
|
@ -393,7 +436,8 @@ Less(op1,op2,fmt)
|
|||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Less: returning %d (format = %s)\n",boolean, fpu_format_name (fmt));
|
||||
printf ("DBG: Less: returning %d (format = %s)\n",
|
||||
boolean, fpu_format_name (fmt));
|
||||
#endif /* DEBUG */
|
||||
|
||||
return (boolean);
|
||||
|
|
@ -410,11 +454,13 @@ Equal(op1,op2,fmt)
|
|||
/* Argument checking already performed by the FPCOMPARE code */
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n", fpu_format_name (fmt),pr_addr(op1),pr_addr(op2));
|
||||
printf ("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",
|
||||
fpu_format_name (fmt), pr_addr (op1), pr_addr (op2));
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* The format type should already have been checked: */
|
||||
switch (fmt) {
|
||||
switch (fmt)
|
||||
{
|
||||
case fmt_single:
|
||||
{
|
||||
sim_fpu wop1;
|
||||
|
|
@ -439,7 +485,8 @@ Equal(op1,op2,fmt)
|
|||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Equal: returning %d (format = %s)\n",boolean, fpu_format_name (fmt));
|
||||
printf ("DBG: Equal: returning %d (format = %s)\n",
|
||||
boolean, fpu_format_name (fmt));
|
||||
#endif /* DEBUG */
|
||||
|
||||
return (boolean);
|
||||
|
|
@ -453,11 +500,13 @@ AbsoluteValue(op,fmt)
|
|||
uword64 result = 0;
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: AbsoluteValue: %s: op = 0x%s\n", fpu_format_name (fmt),pr_addr(op));
|
||||
printf ("DBG: AbsoluteValue: %s: op = 0x%s\n",
|
||||
fpu_format_name (fmt), pr_addr (op));
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* The format type should already have been checked: */
|
||||
switch (fmt) {
|
||||
switch (fmt)
|
||||
{
|
||||
case fmt_single:
|
||||
{
|
||||
sim_fpu wop;
|
||||
|
|
@ -494,11 +543,13 @@ Negate(op,fmt)
|
|||
uword64 result = 0;
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Negate: %s: op = 0x%s\n", fpu_format_name (fmt),pr_addr(op));
|
||||
printf ("DBG: Negate: %s: op = 0x%s\n",
|
||||
fpu_format_name (fmt), pr_addr (op));
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* The format type should already have been checked: */
|
||||
switch (fmt) {
|
||||
switch (fmt)
|
||||
{
|
||||
case fmt_single:
|
||||
{
|
||||
sim_fpu wop;
|
||||
|
|
@ -536,14 +587,16 @@ Add(op1,op2,fmt)
|
|||
uword64 result = 0;
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n", fpu_format_name (fmt),pr_addr(op1),pr_addr(op2));
|
||||
printf ("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",
|
||||
fpu_format_name (fmt), pr_addr (op1), pr_addr (op2));
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* The registers must specify FPRs valid for operands of type
|
||||
"fmt". If they are not valid, the result is undefined. */
|
||||
|
||||
/* The format type should already have been checked: */
|
||||
switch (fmt) {
|
||||
switch (fmt)
|
||||
{
|
||||
case fmt_single:
|
||||
{
|
||||
sim_fpu wop1;
|
||||
|
|
@ -576,7 +629,8 @@ Add(op1,op2,fmt)
|
|||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result), fpu_format_name (fmt));
|
||||
printf ("DBG: Add: returning 0x%s (format = %s)\n",
|
||||
pr_addr (result), fpu_format_name (fmt));
|
||||
#endif /* DEBUG */
|
||||
|
||||
return (result);
|
||||
|
|
@ -591,14 +645,16 @@ Sub(op1,op2,fmt)
|
|||
uword64 result = 0;
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n", fpu_format_name (fmt),pr_addr(op1),pr_addr(op2));
|
||||
printf ("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",
|
||||
fpu_format_name (fmt), pr_addr (op1), pr_addr (op2));
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* The registers must specify FPRs valid for operands of type
|
||||
"fmt". If they are not valid, the result is undefined. */
|
||||
|
||||
/* The format type should already have been checked: */
|
||||
switch (fmt) {
|
||||
switch (fmt)
|
||||
{
|
||||
case fmt_single:
|
||||
{
|
||||
sim_fpu wop1;
|
||||
|
|
@ -631,7 +687,8 @@ Sub(op1,op2,fmt)
|
|||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result), fpu_format_name (fmt));
|
||||
printf ("DBG: Sub: returning 0x%s (format = %s)\n",
|
||||
pr_addr (result), fpu_format_name (fmt));
|
||||
#endif /* DEBUG */
|
||||
|
||||
return (result);
|
||||
|
|
@ -646,14 +703,16 @@ Multiply(op1,op2,fmt)
|
|||
uword64 result = 0;
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n", fpu_format_name (fmt),pr_addr(op1),pr_addr(op2));
|
||||
printf ("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",
|
||||
fpu_format_name (fmt), pr_addr (op1), pr_addr (op2));
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* The registers must specify FPRs valid for operands of type
|
||||
"fmt". If they are not valid, the result is undefined. */
|
||||
|
||||
/* The format type should already have been checked: */
|
||||
switch (fmt) {
|
||||
switch (fmt)
|
||||
{
|
||||
case fmt_single:
|
||||
{
|
||||
sim_fpu wop1;
|
||||
|
|
@ -686,7 +745,8 @@ Multiply(op1,op2,fmt)
|
|||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result), fpu_format_name (fmt));
|
||||
printf ("DBG: Multiply: returning 0x%s (format = %s)\n",
|
||||
pr_addr (result), fpu_format_name (fmt));
|
||||
#endif /* DEBUG */
|
||||
|
||||
return (result);
|
||||
|
|
@ -701,14 +761,16 @@ Divide(op1,op2,fmt)
|
|||
uword64 result = 0;
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n", fpu_format_name (fmt),pr_addr(op1),pr_addr(op2));
|
||||
printf ("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",
|
||||
fpu_format_name (fmt), pr_addr (op1), pr_addr (op2));
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* The registers must specify FPRs valid for operands of type
|
||||
"fmt". If they are not valid, the result is undefined. */
|
||||
|
||||
/* The format type should already have been checked: */
|
||||
switch (fmt) {
|
||||
switch (fmt)
|
||||
{
|
||||
case fmt_single:
|
||||
{
|
||||
sim_fpu wop1;
|
||||
|
|
@ -741,7 +803,8 @@ Divide(op1,op2,fmt)
|
|||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result), fpu_format_name (fmt));
|
||||
printf ("DBG: Divide: returning 0x%s (format = %s)\n",
|
||||
pr_addr (result), fpu_format_name (fmt));
|
||||
#endif /* DEBUG */
|
||||
|
||||
return (result);
|
||||
|
|
@ -755,14 +818,16 @@ Recip(op,fmt)
|
|||
uword64 result = 0;
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Recip: %s: op = 0x%s\n", fpu_format_name (fmt),pr_addr(op));
|
||||
printf ("DBG: Recip: %s: op = 0x%s\n",
|
||||
fpu_format_name (fmt), pr_addr (op));
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* The registers must specify FPRs valid for operands of type
|
||||
"fmt". If they are not valid, the result is undefined. */
|
||||
|
||||
/* The format type should already have been checked: */
|
||||
switch (fmt) {
|
||||
switch (fmt)
|
||||
{
|
||||
case fmt_single:
|
||||
{
|
||||
sim_fpu wop;
|
||||
|
|
@ -791,7 +856,8 @@ Recip(op,fmt)
|
|||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result), fpu_format_name (fmt));
|
||||
printf ("DBG: Recip: returning 0x%s (format = %s)\n",
|
||||
pr_addr (result), fpu_format_name (fmt));
|
||||
#endif /* DEBUG */
|
||||
|
||||
return (result);
|
||||
|
|
@ -805,14 +871,16 @@ SquareRoot(op,fmt)
|
|||
uword64 result = 0;
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: SquareRoot: %s: op = 0x%s\n", fpu_format_name (fmt),pr_addr(op));
|
||||
printf ("DBG: SquareRoot: %s: op = 0x%s\n",
|
||||
fpu_format_name (fmt), pr_addr (op));
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* The registers must specify FPRs valid for operands of type
|
||||
"fmt". If they are not valid, the result is undefined. */
|
||||
|
||||
/* The format type should already have been checked: */
|
||||
switch (fmt) {
|
||||
switch (fmt)
|
||||
{
|
||||
case fmt_single:
|
||||
{
|
||||
sim_fpu wop;
|
||||
|
|
@ -841,7 +909,8 @@ SquareRoot(op,fmt)
|
|||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result), fpu_format_name (fmt));
|
||||
printf ("DBG: SquareRoot: returning 0x%s (format = %s)\n",
|
||||
pr_addr (result), fpu_format_name (fmt));
|
||||
#endif /* DEBUG */
|
||||
|
||||
return (result);
|
||||
|
|
@ -857,7 +926,8 @@ Max (uword64 op1,
|
|||
unsigned64 result;
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n", fpu_format_name (fmt),pr_addr(op1),pr_addr(op2));
|
||||
printf ("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",
|
||||
fpu_format_name (fmt), pr_addr (op1), pr_addr (op2));
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* The registers must specify FPRs valid for operands of type
|
||||
|
|
@ -910,7 +980,8 @@ Max (uword64 op1,
|
|||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result), fpu_format_name (fmt));
|
||||
printf ("DBG: Max: returning 0x%s (format = %s)\n",
|
||||
pr_addr (result), fpu_format_name (fmt));
|
||||
#endif /* DEBUG */
|
||||
|
||||
return (result);
|
||||
|
|
@ -927,7 +998,8 @@ Min (uword64 op1,
|
|||
unsigned64 result;
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n", fpu_format_name (fmt),pr_addr(op1),pr_addr(op2));
|
||||
printf ("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",
|
||||
fpu_format_name (fmt), pr_addr (op1), pr_addr (op2));
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* The registers must specify FPRs valid for operands of type
|
||||
|
|
@ -980,7 +1052,8 @@ Min (uword64 op1,
|
|||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result), fpu_format_name (fmt));
|
||||
printf ("DBG: Min: returning 0x%s (format = %s)\n",
|
||||
pr_addr (result), fpu_format_name (fmt));
|
||||
#endif /* DEBUG */
|
||||
|
||||
return (result);
|
||||
|
|
@ -1003,7 +1076,9 @@ convert (SIM_DESC sd,
|
|||
|
||||
#ifdef DEBUG
|
||||
#if 0 /* FIXME: doesn't compile */
|
||||
printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n", fpu_rounding_mode_name (rm),pr_addr(op), fpu_format_name (from), fpu_format_name (to),pr_addr(IPC));
|
||||
printf ("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",
|
||||
fpu_rounding_mode_name (rm), pr_addr (op), fpu_format_name (from),
|
||||
fpu_format_name (to), pr_addr (IPC));
|
||||
#endif
|
||||
#endif /* DEBUG */
|
||||
|
||||
|
|
@ -1088,7 +1163,8 @@ convert (SIM_DESC sd,
|
|||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64), fpu_format_name (to));
|
||||
printf ("DBG: Convert: returning 0x%s (to format = %s)\n",
|
||||
pr_addr (result64), fpu_format_name (to));
|
||||
#endif /* DEBUG */
|
||||
|
||||
return (result64);
|
||||
|
|
|
|||
Loading…
Reference in New Issue