2002-03-19 Chris Demetriou <cgd@broadcom.com>
* cp1.c: Fix many formatting issues.
This commit is contained in:
parent
07892c0b5a
commit
37d146fa1d
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@ -1,3 +1,7 @@
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2002-03-19 Chris Demetriou <cgd@broadcom.com>
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* cp1.c: Fix many formatting issues.
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2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
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* cp1.c (fpu_format_name): New function to replace...
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304
sim/mips/cp1.c
304
sim/mips/cp1.c
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@ -51,30 +51,30 @@
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*/
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/* Extract sign-bit: */
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#define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
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#define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
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#define FP_S_s(v) (((v) & (((unsigned) 1) << 31)) ? 1 : 0)
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#define FP_D_s(v) (((v) & (((uword64) 1) << 63)) ? 1 : 0)
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/* Extract biased exponent: */
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#define FP_S_be(v) (((v) >> 23) & 0xFF)
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#define FP_D_be(v) (((v) >> 52) & 0x7FF)
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/* Extract unbiased Exponent: */
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#define FP_S_e(v) (FP_S_be(v) - 0x7F)
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#define FP_D_e(v) (FP_D_be(v) - 0x3FF)
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#define FP_S_e(v) (FP_S_be (v) - 0x7F)
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#define FP_D_e(v) (FP_D_be (v) - 0x3FF)
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/* Extract complete fraction field: */
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#define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
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#define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
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#define FP_S_f(v) ((v) & ~(((unsigned) 0x1FF) << 23))
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#define FP_D_f(v) ((v) & ~(((uword64) 0xFFF) << 52))
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/* Extract numbered fraction bit: */
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#define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
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#define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
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#define FP_S_fb(b, v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
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#define FP_D_fb(b, v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
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/* Explicit QNaN values used when value required: */
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#define FPQNaN_SINGLE (0x7FBFFFFF)
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#define FPQNaN_WORD (0x7FFFFFFF)
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#define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
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#define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
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#define FPQNaN_DOUBLE ((((uword64) 0x7FF7FFFF) << 32) | 0xFFFFFFFF)
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#define FPQNaN_LONG ((((uword64) 0x7FFFFFFF) << 32) | 0xFFFFFFFF)
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/* Explicit Infinity values used when required: */
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#define FPINF_SINGLE (0x7F800000)
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#define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
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#define FPINF_DOUBLE ((((uword64) 0x7FF00000) << 32) | 0x00000000)
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static const char *fpu_format_name (FP_formats fmt);
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#ifdef DEBUG
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@ -93,6 +93,7 @@ value_fpr (SIM_DESC sd,
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/* Treat unused register values, as fixed-point 64bit values: */
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if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown))
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{
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#if 1
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/* If request to read data as "uninterpreted", then use the current
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encoding: */
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@ -100,22 +101,30 @@ value_fpr (SIM_DESC sd,
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#else
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fmt = fmt_long;
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#endif
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}
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/* For values not yet accessed, set to the desired format: */
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if (FPR_STATE[fpr] == fmt_uninterpreted) {
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if (FPR_STATE[fpr] == fmt_uninterpreted)
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{
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FPR_STATE[fpr] = fmt;
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#ifdef DEBUG
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printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr, fpu_format_name (fmt));
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printf ("DBG: Register %d was fmt_uninterpreted. Now %s\n", fpr,
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fpu_format_name (fmt));
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#endif /* DEBUG */
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}
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if (fmt != FPR_STATE[fpr]) {
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sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr, fpu_format_name (FPR_STATE[fpr]), fpu_format_name (fmt),pr_addr(cia));
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if (fmt != FPR_STATE[fpr])
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{
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sim_io_eprintf (sd, "FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",
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fpr, fpu_format_name (FPR_STATE[fpr]),
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fpu_format_name (fmt), pr_addr (cia));
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FPR_STATE[fpr] = fmt_unknown;
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}
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if (FPR_STATE[fpr] == fmt_unknown) {
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if (FPR_STATE[fpr] == fmt_unknown)
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{
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/* Set QNaN value: */
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switch (fmt) {
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switch (fmt)
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{
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case fmt_single:
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value = FPQNaN_SINGLE;
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break;
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@ -136,8 +145,11 @@ value_fpr (SIM_DESC sd,
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err = -1;
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break;
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}
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} else if (SizeFGR() == 64) {
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switch (fmt) {
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}
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else if (SizeFGR () == 64)
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{
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switch (fmt)
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{
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case fmt_single:
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case fmt_word:
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value = (FGR[fpr] & 0xFFFFFFFF);
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@ -149,12 +161,15 @@ value_fpr (SIM_DESC sd,
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value = FGR[fpr];
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break;
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default :
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default:
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err = -1;
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break;
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}
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} else {
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switch (fmt) {
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}
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else
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{
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switch (fmt)
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{
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case fmt_single:
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case fmt_word:
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value = (FGR[fpr] & 0xFFFFFFFF);
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@ -163,15 +178,20 @@ value_fpr (SIM_DESC sd,
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case fmt_uninterpreted:
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case fmt_double:
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case fmt_long:
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if ((fpr & 1) == 0) { /* even registers only */
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if ((fpr & 1) == 0)
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{
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/* even registers only */
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#ifdef DEBUG
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printf("DBG: ValueFPR: FGR[%d] = %s, FGR[%d] = %s\n",
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fpr+1, pr_uword64( (uword64) FGR[fpr+1] ),
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fpr, pr_uword64( (uword64) FGR[fpr] ));
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printf ("DBG: ValueFPR: FGR[%d] = %s, FGR[%d] = %s\n",
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fpr + 1, pr_uword64 ((uword64) FGR[fpr+1]),
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fpr, pr_uword64 ((uword64) FGR[fpr]));
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#endif
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value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF));
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} else {
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SignalException(ReservedInstruction,0);
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value = ((((uword64) FGR[fpr+1]) << 32)
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| (FGR[fpr] & 0xFFFFFFFF));
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}
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else
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{
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SignalException (ReservedInstruction, 0);
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}
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break;
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}
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if (err)
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SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
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SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR ()");
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#ifdef DEBUG
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printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr, fpu_format_name (fmt),pr_uword64(value),pr_addr(cia),SizeFGR());
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printf ("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR () = %d\n",
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fpr, fpu_format_name (fmt), pr_uword64 (value), pr_addr (cia),
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SizeFGR ());
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#endif /* DEBUG */
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return(value);
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return (value);
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}
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void
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@ -202,19 +224,24 @@ store_fpr (SIM_DESC sd,
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int err = 0;
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#ifdef DEBUG
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printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d,\n",fpr, fpu_format_name (fmt),pr_uword64(value),pr_addr(cia),SizeFGR());
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printf ("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR () = %d, \n",
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fpr, fpu_format_name (fmt), pr_uword64 (value), pr_addr (cia),
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SizeFGR ());
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#endif /* DEBUG */
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if (SizeFGR() == 64) {
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switch (fmt) {
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if (SizeFGR () == 64)
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{
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switch (fmt)
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{
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case fmt_uninterpreted_32:
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fmt = fmt_uninterpreted;
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case fmt_single :
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case fmt_word :
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if (STATE_VERBOSE_P(SD))
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sim_io_eprintf (SD, "Warning: PC 0x%s: interp.c store_fpr DEADCODE\n",
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pr_addr(cia));
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FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF));
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if (STATE_VERBOSE_P (SD))
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sim_io_eprintf (SD,
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"Warning: PC 0x%s: interp.c store_fpr DEADCODE\n",
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pr_addr (cia));
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FGR[fpr] = (((uword64) 0xDEADC0DE << 32) | (value & 0xFFFFFFFF));
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FPR_STATE[fpr] = fmt;
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break;
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err = -1;
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break;
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}
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} else {
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switch (fmt) {
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}
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else
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{
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switch (fmt)
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{
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case fmt_uninterpreted_32:
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fmt = fmt_uninterpreted;
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case fmt_single :
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case fmt_uninterpreted:
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case fmt_double :
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case fmt_long :
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if ((fpr & 1) == 0) { /* even register number only */
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if ((fpr & 1) == 0)
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{
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/* even register number only */
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FGR[fpr+1] = (value >> 32);
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FGR[fpr] = (value & 0xFFFFFFFF);
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FPR_STATE[fpr + 1] = fmt;
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FPR_STATE[fpr] = fmt;
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} else {
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}
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else
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{
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FPR_STATE[fpr] = fmt_unknown;
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FPR_STATE[fpr + 1] = fmt_unknown;
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SignalException(ReservedInstruction,0);
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SignalException (ReservedInstruction, 0);
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}
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break;
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}
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#if defined(WARN_RESULT)
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else
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UndefinedResult();
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UndefinedResult ();
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#endif /* WARN_RESULT */
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if (err)
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SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
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SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR ()");
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#ifdef DEBUG
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printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_uword64(FGR[fpr]), fpu_format_name (fmt));
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printf ("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",
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fpr, pr_uword64 (FGR[fpr]), fpu_format_name (fmt));
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#endif /* DEBUG */
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return;
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}
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int
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NaN(op,fmt)
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NaN (op, fmt)
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uword64 op;
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FP_formats fmt;
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{
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int boolean = 0;
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switch (fmt) {
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switch (fmt)
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{
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case fmt_single:
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case fmt_word:
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{
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}
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#ifdef DEBUG
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printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op), fpu_format_name (fmt));
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printf ("DBG: NaN: returning %d for 0x%s (format = %s)\n",
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boolean, pr_addr (op), fpu_format_name (fmt));
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#endif /* DEBUG */
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return(boolean);
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return (boolean);
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}
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int
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Infinity(op,fmt)
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Infinity (op, fmt)
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uword64 op;
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FP_formats fmt;
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{
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int boolean = 0;
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#ifdef DEBUG
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printf("DBG: Infinity: format %s 0x%s\n", fpu_format_name (fmt),pr_addr(op));
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printf ("DBG: Infinity: format %s 0x%s\n",
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fpu_format_name (fmt), pr_addr (op));
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#endif /* DEBUG */
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switch (fmt) {
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switch (fmt)
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{
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case fmt_single:
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{
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sim_fpu wop;
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@ -342,19 +381,21 @@ Infinity(op,fmt)
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break;
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}
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default:
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printf("DBG: TODO: unrecognised format (%s) for Infinity check\n", fpu_format_name (fmt));
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printf ("DBG: TODO: unrecognised format (%s) for Infinity check\n",
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fpu_format_name (fmt));
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break;
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}
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#ifdef DEBUG
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printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op), fpu_format_name (fmt));
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printf ("DBG: Infinity: returning %d for 0x%s (format = %s)\n",
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boolean, pr_addr (op), fpu_format_name (fmt));
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#endif /* DEBUG */
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return(boolean);
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return (boolean);
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}
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int
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Less(op1,op2,fmt)
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Less (op1, op2, fmt)
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uword64 op1;
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uword64 op2;
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FP_formats fmt;
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@ -364,11 +405,13 @@ Less(op1,op2,fmt)
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/* Argument checking already performed by the FPCOMPARE code */
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#ifdef DEBUG
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printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n", fpu_format_name (fmt),pr_addr(op1),pr_addr(op2));
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printf ("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",
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fpu_format_name (fmt), pr_addr (op1), pr_addr (op2));
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#endif /* DEBUG */
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/* The format type should already have been checked: */
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switch (fmt) {
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switch (fmt)
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{
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case fmt_single:
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{
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sim_fpu wop1;
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@ -393,14 +436,15 @@ Less(op1,op2,fmt)
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}
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#ifdef DEBUG
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printf("DBG: Less: returning %d (format = %s)\n",boolean, fpu_format_name (fmt));
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printf ("DBG: Less: returning %d (format = %s)\n",
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boolean, fpu_format_name (fmt));
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#endif /* DEBUG */
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return(boolean);
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return (boolean);
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}
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int
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Equal(op1,op2,fmt)
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Equal (op1, op2, fmt)
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uword64 op1;
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uword64 op2;
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FP_formats fmt;
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@ -410,11 +454,13 @@ Equal(op1,op2,fmt)
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/* Argument checking already performed by the FPCOMPARE code */
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#ifdef DEBUG
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printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n", fpu_format_name (fmt),pr_addr(op1),pr_addr(op2));
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printf ("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",
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fpu_format_name (fmt), pr_addr (op1), pr_addr (op2));
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#endif /* DEBUG */
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/* The format type should already have been checked: */
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switch (fmt) {
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switch (fmt)
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{
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case fmt_single:
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{
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sim_fpu wop1;
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@ -439,25 +485,28 @@ Equal(op1,op2,fmt)
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}
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#ifdef DEBUG
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printf("DBG: Equal: returning %d (format = %s)\n",boolean, fpu_format_name (fmt));
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printf ("DBG: Equal: returning %d (format = %s)\n",
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boolean, fpu_format_name (fmt));
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#endif /* DEBUG */
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return(boolean);
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return (boolean);
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}
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uword64
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AbsoluteValue(op,fmt)
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AbsoluteValue (op, fmt)
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uword64 op;
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FP_formats fmt;
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{
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uword64 result = 0;
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#ifdef DEBUG
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printf("DBG: AbsoluteValue: %s: op = 0x%s\n", fpu_format_name (fmt),pr_addr(op));
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printf ("DBG: AbsoluteValue: %s: op = 0x%s\n",
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fpu_format_name (fmt), pr_addr (op));
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#endif /* DEBUG */
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/* The format type should already have been checked: */
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switch (fmt) {
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switch (fmt)
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{
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case fmt_single:
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{
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sim_fpu wop;
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|
@ -483,22 +532,24 @@ AbsoluteValue(op,fmt)
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abort ();
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}
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return(result);
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return (result);
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}
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uword64
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Negate(op,fmt)
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Negate (op, fmt)
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uword64 op;
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FP_formats fmt;
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{
|
||||
uword64 result = 0;
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Negate: %s: op = 0x%s\n", fpu_format_name (fmt),pr_addr(op));
|
||||
printf ("DBG: Negate: %s: op = 0x%s\n",
|
||||
fpu_format_name (fmt), pr_addr (op));
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* The format type should already have been checked: */
|
||||
switch (fmt) {
|
||||
switch (fmt)
|
||||
{
|
||||
case fmt_single:
|
||||
{
|
||||
sim_fpu wop;
|
||||
|
@ -524,11 +575,11 @@ Negate(op,fmt)
|
|||
abort ();
|
||||
}
|
||||
|
||||
return(result);
|
||||
return (result);
|
||||
}
|
||||
|
||||
uword64
|
||||
Add(op1,op2,fmt)
|
||||
Add (op1, op2, fmt)
|
||||
uword64 op1;
|
||||
uword64 op2;
|
||||
FP_formats fmt;
|
||||
|
@ -536,14 +587,16 @@ Add(op1,op2,fmt)
|
|||
uword64 result = 0;
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n", fpu_format_name (fmt),pr_addr(op1),pr_addr(op2));
|
||||
printf ("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",
|
||||
fpu_format_name (fmt), pr_addr (op1), pr_addr (op2));
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* The registers must specify FPRs valid for operands of type
|
||||
"fmt". If they are not valid, the result is undefined. */
|
||||
|
||||
/* The format type should already have been checked: */
|
||||
switch (fmt) {
|
||||
switch (fmt)
|
||||
{
|
||||
case fmt_single:
|
||||
{
|
||||
sim_fpu wop1;
|
||||
|
@ -576,14 +629,15 @@ Add(op1,op2,fmt)
|
|||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result), fpu_format_name (fmt));
|
||||
printf ("DBG: Add: returning 0x%s (format = %s)\n",
|
||||
pr_addr (result), fpu_format_name (fmt));
|
||||
#endif /* DEBUG */
|
||||
|
||||
return(result);
|
||||
return (result);
|
||||
}
|
||||
|
||||
uword64
|
||||
Sub(op1,op2,fmt)
|
||||
Sub (op1, op2, fmt)
|
||||
uword64 op1;
|
||||
uword64 op2;
|
||||
FP_formats fmt;
|
||||
|
@ -591,14 +645,16 @@ Sub(op1,op2,fmt)
|
|||
uword64 result = 0;
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n", fpu_format_name (fmt),pr_addr(op1),pr_addr(op2));
|
||||
printf ("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",
|
||||
fpu_format_name (fmt), pr_addr (op1), pr_addr (op2));
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* The registers must specify FPRs valid for operands of type
|
||||
"fmt". If they are not valid, the result is undefined. */
|
||||
|
||||
/* The format type should already have been checked: */
|
||||
switch (fmt) {
|
||||
switch (fmt)
|
||||
{
|
||||
case fmt_single:
|
||||
{
|
||||
sim_fpu wop1;
|
||||
|
@ -631,14 +687,15 @@ Sub(op1,op2,fmt)
|
|||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result), fpu_format_name (fmt));
|
||||
printf ("DBG: Sub: returning 0x%s (format = %s)\n",
|
||||
pr_addr (result), fpu_format_name (fmt));
|
||||
#endif /* DEBUG */
|
||||
|
||||
return(result);
|
||||
return (result);
|
||||
}
|
||||
|
||||
uword64
|
||||
Multiply(op1,op2,fmt)
|
||||
Multiply (op1, op2, fmt)
|
||||
uword64 op1;
|
||||
uword64 op2;
|
||||
FP_formats fmt;
|
||||
|
@ -646,14 +703,16 @@ Multiply(op1,op2,fmt)
|
|||
uword64 result = 0;
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n", fpu_format_name (fmt),pr_addr(op1),pr_addr(op2));
|
||||
printf ("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",
|
||||
fpu_format_name (fmt), pr_addr (op1), pr_addr (op2));
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* The registers must specify FPRs valid for operands of type
|
||||
"fmt". If they are not valid, the result is undefined. */
|
||||
|
||||
/* The format type should already have been checked: */
|
||||
switch (fmt) {
|
||||
switch (fmt)
|
||||
{
|
||||
case fmt_single:
|
||||
{
|
||||
sim_fpu wop1;
|
||||
|
@ -686,14 +745,15 @@ Multiply(op1,op2,fmt)
|
|||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result), fpu_format_name (fmt));
|
||||
printf ("DBG: Multiply: returning 0x%s (format = %s)\n",
|
||||
pr_addr (result), fpu_format_name (fmt));
|
||||
#endif /* DEBUG */
|
||||
|
||||
return(result);
|
||||
return (result);
|
||||
}
|
||||
|
||||
uword64
|
||||
Divide(op1,op2,fmt)
|
||||
Divide (op1, op2, fmt)
|
||||
uword64 op1;
|
||||
uword64 op2;
|
||||
FP_formats fmt;
|
||||
|
@ -701,14 +761,16 @@ Divide(op1,op2,fmt)
|
|||
uword64 result = 0;
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n", fpu_format_name (fmt),pr_addr(op1),pr_addr(op2));
|
||||
printf ("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",
|
||||
fpu_format_name (fmt), pr_addr (op1), pr_addr (op2));
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* The registers must specify FPRs valid for operands of type
|
||||
"fmt". If they are not valid, the result is undefined. */
|
||||
|
||||
/* The format type should already have been checked: */
|
||||
switch (fmt) {
|
||||
switch (fmt)
|
||||
{
|
||||
case fmt_single:
|
||||
{
|
||||
sim_fpu wop1;
|
||||
|
@ -741,28 +803,31 @@ Divide(op1,op2,fmt)
|
|||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result), fpu_format_name (fmt));
|
||||
printf ("DBG: Divide: returning 0x%s (format = %s)\n",
|
||||
pr_addr (result), fpu_format_name (fmt));
|
||||
#endif /* DEBUG */
|
||||
|
||||
return(result);
|
||||
return (result);
|
||||
}
|
||||
|
||||
uword64 UNUSED
|
||||
Recip(op,fmt)
|
||||
Recip (op, fmt)
|
||||
uword64 op;
|
||||
FP_formats fmt;
|
||||
{
|
||||
uword64 result = 0;
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Recip: %s: op = 0x%s\n", fpu_format_name (fmt),pr_addr(op));
|
||||
printf ("DBG: Recip: %s: op = 0x%s\n",
|
||||
fpu_format_name (fmt), pr_addr (op));
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* The registers must specify FPRs valid for operands of type
|
||||
"fmt". If they are not valid, the result is undefined. */
|
||||
|
||||
/* The format type should already have been checked: */
|
||||
switch (fmt) {
|
||||
switch (fmt)
|
||||
{
|
||||
case fmt_single:
|
||||
{
|
||||
sim_fpu wop;
|
||||
|
@ -791,28 +856,31 @@ Recip(op,fmt)
|
|||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result), fpu_format_name (fmt));
|
||||
printf ("DBG: Recip: returning 0x%s (format = %s)\n",
|
||||
pr_addr (result), fpu_format_name (fmt));
|
||||
#endif /* DEBUG */
|
||||
|
||||
return(result);
|
||||
return (result);
|
||||
}
|
||||
|
||||
uword64
|
||||
SquareRoot(op,fmt)
|
||||
SquareRoot (op, fmt)
|
||||
uword64 op;
|
||||
FP_formats fmt;
|
||||
{
|
||||
uword64 result = 0;
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: SquareRoot: %s: op = 0x%s\n", fpu_format_name (fmt),pr_addr(op));
|
||||
printf ("DBG: SquareRoot: %s: op = 0x%s\n",
|
||||
fpu_format_name (fmt), pr_addr (op));
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* The registers must specify FPRs valid for operands of type
|
||||
"fmt". If they are not valid, the result is undefined. */
|
||||
|
||||
/* The format type should already have been checked: */
|
||||
switch (fmt) {
|
||||
switch (fmt)
|
||||
{
|
||||
case fmt_single:
|
||||
{
|
||||
sim_fpu wop;
|
||||
|
@ -841,10 +909,11 @@ SquareRoot(op,fmt)
|
|||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result), fpu_format_name (fmt));
|
||||
printf ("DBG: SquareRoot: returning 0x%s (format = %s)\n",
|
||||
pr_addr (result), fpu_format_name (fmt));
|
||||
#endif /* DEBUG */
|
||||
|
||||
return(result);
|
||||
return (result);
|
||||
}
|
||||
|
||||
#if 0
|
||||
|
@ -857,7 +926,8 @@ Max (uword64 op1,
|
|||
unsigned64 result;
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n", fpu_format_name (fmt),pr_addr(op1),pr_addr(op2));
|
||||
printf ("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",
|
||||
fpu_format_name (fmt), pr_addr (op1), pr_addr (op2));
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* The registers must specify FPRs valid for operands of type
|
||||
|
@ -910,10 +980,11 @@ Max (uword64 op1,
|
|||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result), fpu_format_name (fmt));
|
||||
printf ("DBG: Max: returning 0x%s (format = %s)\n",
|
||||
pr_addr (result), fpu_format_name (fmt));
|
||||
#endif /* DEBUG */
|
||||
|
||||
return(result);
|
||||
return (result);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
@ -927,7 +998,8 @@ Min (uword64 op1,
|
|||
unsigned64 result;
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n", fpu_format_name (fmt),pr_addr(op1),pr_addr(op2));
|
||||
printf ("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",
|
||||
fpu_format_name (fmt), pr_addr (op1), pr_addr (op2));
|
||||
#endif /* DEBUG */
|
||||
|
||||
/* The registers must specify FPRs valid for operands of type
|
||||
|
@ -980,10 +1052,11 @@ Min (uword64 op1,
|
|||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result), fpu_format_name (fmt));
|
||||
printf ("DBG: Min: returning 0x%s (format = %s)\n",
|
||||
pr_addr (result), fpu_format_name (fmt));
|
||||
#endif /* DEBUG */
|
||||
|
||||
return(result);
|
||||
return (result);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
@ -1003,7 +1076,9 @@ convert (SIM_DESC sd,
|
|||
|
||||
#ifdef DEBUG
|
||||
#if 0 /* FIXME: doesn't compile */
|
||||
printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n", fpu_rounding_mode_name (rm),pr_addr(op), fpu_format_name (from), fpu_format_name (to),pr_addr(IPC));
|
||||
printf ("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",
|
||||
fpu_rounding_mode_name (rm), pr_addr (op), fpu_format_name (from),
|
||||
fpu_format_name (to), pr_addr (IPC));
|
||||
#endif
|
||||
#endif /* DEBUG */
|
||||
|
||||
|
@ -1088,10 +1163,11 @@ convert (SIM_DESC sd,
|
|||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64), fpu_format_name (to));
|
||||
printf ("DBG: Convert: returning 0x%s (to format = %s)\n",
|
||||
pr_addr (result64), fpu_format_name (to));
|
||||
#endif /* DEBUG */
|
||||
|
||||
return(result64);
|
||||
return (result64);
|
||||
}
|
||||
|
||||
static const char *
|
||||
|
|
Loading…
Reference in New Issue