* config/tc-ppc.c (parse_cpu) <power6>: Accept Altivec instructions.
	<cell>: Likewise.

gas/testsuite/
	* gas/ppc/cell.s: Add altivec instructions.
	* gas/ppc/cell.d: Update expected output.
	* gas/ppc/power6.d: New.
	* gas/ppc/power6.s: Likewise.
	* gas/ppc/ppc.exp (powerpc64*-*-*): Move cell from here to...
	(powerpc*-*-*): Here.  Run power6 test.
This commit is contained in:
Peter Bergner 2008-08-01 02:44:12 +00:00
parent 6d76a53df9
commit 3823320924
8 changed files with 90 additions and 5 deletions

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@ -1,3 +1,8 @@
2008-07-31 Peter Bergner <bergner@vnet.ibm.com>
* config/tc-ppc.c (parse_cpu) <power6>: Accept Altivec instructions.
<cell>: Likewise.
2008-07-30 Michael J. Eager <eager@eagercon.com>
* config/tc-ppc.c (parse_cpu): Separate handling of -m403/405.

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@ -932,13 +932,14 @@ parse_cpu (const char *arg)
{
ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
| PPC_OPCODE_64 | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6);
| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
| PPC_OPCODE_ALTIVEC);
}
else if (strcmp (arg, "cell") == 0)
{
ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
| PPC_OPCODE_64 | PPC_OPCODE_POWER4
| PPC_OPCODE_CELL);
| PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC);
}
/* -mcom means assemble for the common intersection between Power
and PowerPC. At present, we just allow the union, rather

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@ -1,3 +1,12 @@
2008-07-31 Peter Bergner <bergner@vnet.ibm.com>
* gas/ppc/cell.s: Add altivec instructions.
* gas/ppc/cell.d: Update expected output.
* gas/ppc/power6.d: New.
* gas/ppc/power6.s: Likewise.
* gas/ppc/ppc.exp (powerpc64*-*-*): Move cell from here to...
(powerpc*-*-*): Here. Run power6 test.
2008-07-24 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/nops-1.d: Add -mtune=generic32.

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@ -1,6 +1,6 @@
#as: -mcell
#objdump: -dr -Mcell
#name: Cell tests
#name: Cell tests (includes Altivec)
.*: +file format elf(32)?(64)?-powerpc.*
@ -8,7 +8,7 @@
Disassembly of section \.text:
0000000000000000 <.text>:
0+00 <.text>:
0: 7c 01 14 0e lvlx v0,r1,r2
4: 7c 00 14 0e lvlx v0,0,r2
8: 7c 01 16 0e lvlxl v0,r1,r2
@ -29,3 +29,9 @@ Disassembly of section \.text:
44: 7c 01 14 28 ldbrx r0,r1,r2
48: 7c 00 0d 28 stdbrx r0,0,r1
4c: 7c 01 15 28 stdbrx r0,r1,r2
50: 7c 60 06 6c dss 3
54: 7e 00 06 6c dssall
58: 7c 25 22 ac dst r5,r4,1
5c: 7e 08 3a ac dstt r8,r7,0
60: 7c 65 32 ec dstst r5,r6,3
64: 7e 44 2a ec dststt r4,r5,2

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@ -22,3 +22,10 @@
stdbrx %r0, 0, %r1
stdbrx %r0, %r1, %r2
dss 3
dssall
dst 5,4,1
dstt 8,7,0
dstst 5,6,3
dststt 4,5,2

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@ -0,0 +1,31 @@
#as: -a32 -mpower6
#objdump: -dr -Mpower6
#name: POWER6 tests (includes DFP and Altivec)
.*: +file format elf32-powerpc.*
Disassembly of section \.text:
0+00 <start>:
0: 4c 00 03 24 doze
4: 4c 00 03 64 nap
8: 4c 00 03 a4 sleep
c: 4c 00 03 e4 rvwinkle
10: 7c 83 01 34 prtyw r3,r4
14: 7d cd 01 74 prtyd r13,r14
18: 7d 5c 02 a6 mfcfar r10
1c: 7d 7c 03 a6 mtcfar r11
20: 7c 83 2b f8 cmpb r3,r4,r5
24: 7c c0 3c be mffgpr f6,r7
28: 7d 00 4d be mftgpr r8,f9
2c: 7d 4b 66 2a lwzcix r10,r11,r12
30: 7d ae 7e 2e lfdpx f13,r14,r15
34: ee 11 90 04 dadd f16,f17,f18
38: fe 96 c0 04 daddq f20,f22,f24
3c: 7c 60 06 6c dss 3
40: 7e 00 06 6c dssall
44: 7c 25 22 ac dst r5,r4,1
48: 7e 08 3a ac dstt r8,r7,0
4c: 7c 65 32 ec dstst r5,r6,3
50: 7e 44 2a ec dststt r4,r5,2

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@ -0,0 +1,25 @@
# PowerPC POWER6 AltiVec tests
#as: -mpower6
.section ".text"
start:
doze
nap
sleep
rvwinkle
prtyw 3,4
prtyd 13,14
mfcfar 10
mtcfar 11
cmpb 3,4,5
mffgpr 6,7
mftgpr 8,9
lwzcix 10,11,12
lfdpx 13,14,15
dadd 16,17,18
daddq 20,22,24
dss 3
dssall
dst 5,4,1
dstt 8,7,0
dstst 5,6,3
dststt 4,5,2

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@ -11,7 +11,6 @@ if { [istarget powerpc64*-*-*] || [istarget *-*-elf64*]} then {
run_dump_test "astest2_64"
run_dump_test "test1elf64"
run_dump_test "power4"
run_dump_test "cell"
run_list_test "range64" "-a64"
} elseif { [istarget powerpc*-*aix*] } then {
run_dump_test "test1xcoff32"
@ -45,5 +44,7 @@ if { [istarget powerpc*-*-*] } then {
run_list_test "range" "-a32"
run_dump_test "ppc750ps"
run_dump_test "e500mc"
run_dump_test "cell"
run_dump_test "power6"
}
}