gas/
* config/tc-ppc.c (parse_cpu) <power6>: Accept Altivec instructions. <cell>: Likewise. gas/testsuite/ * gas/ppc/cell.s: Add altivec instructions. * gas/ppc/cell.d: Update expected output. * gas/ppc/power6.d: New. * gas/ppc/power6.s: Likewise. * gas/ppc/ppc.exp (powerpc64*-*-*): Move cell from here to... (powerpc*-*-*): Here. Run power6 test.
This commit is contained in:
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@ -1,3 +1,8 @@
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2008-07-31 Peter Bergner <bergner@vnet.ibm.com>
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* config/tc-ppc.c (parse_cpu) <power6>: Accept Altivec instructions.
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<cell>: Likewise.
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2008-07-30 Michael J. Eager <eager@eagercon.com>
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* config/tc-ppc.c (parse_cpu): Separate handling of -m403/405.
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@ -932,13 +932,14 @@ parse_cpu (const char *arg)
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{
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ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
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| PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6);
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| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
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| PPC_OPCODE_ALTIVEC);
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}
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else if (strcmp (arg, "cell") == 0)
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{
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ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
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| PPC_OPCODE_64 | PPC_OPCODE_POWER4
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| PPC_OPCODE_CELL);
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| PPC_OPCODE_CELL | PPC_OPCODE_ALTIVEC);
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}
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/* -mcom means assemble for the common intersection between Power
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and PowerPC. At present, we just allow the union, rather
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@ -1,3 +1,12 @@
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2008-07-31 Peter Bergner <bergner@vnet.ibm.com>
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* gas/ppc/cell.s: Add altivec instructions.
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* gas/ppc/cell.d: Update expected output.
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* gas/ppc/power6.d: New.
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* gas/ppc/power6.s: Likewise.
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* gas/ppc/ppc.exp (powerpc64*-*-*): Move cell from here to...
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(powerpc*-*-*): Here. Run power6 test.
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2008-07-24 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/nops-1.d: Add -mtune=generic32.
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@ -1,6 +1,6 @@
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#as: -mcell
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#objdump: -dr -Mcell
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#name: Cell tests
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#name: Cell tests (includes Altivec)
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.*: +file format elf(32)?(64)?-powerpc.*
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@ -8,7 +8,7 @@
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Disassembly of section \.text:
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0000000000000000 <.text>:
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0+00 <.text>:
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0: 7c 01 14 0e lvlx v0,r1,r2
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4: 7c 00 14 0e lvlx v0,0,r2
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8: 7c 01 16 0e lvlxl v0,r1,r2
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@ -29,3 +29,9 @@ Disassembly of section \.text:
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44: 7c 01 14 28 ldbrx r0,r1,r2
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48: 7c 00 0d 28 stdbrx r0,0,r1
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4c: 7c 01 15 28 stdbrx r0,r1,r2
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50: 7c 60 06 6c dss 3
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54: 7e 00 06 6c dssall
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58: 7c 25 22 ac dst r5,r4,1
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5c: 7e 08 3a ac dstt r8,r7,0
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60: 7c 65 32 ec dstst r5,r6,3
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64: 7e 44 2a ec dststt r4,r5,2
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@ -22,3 +22,10 @@
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stdbrx %r0, 0, %r1
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stdbrx %r0, %r1, %r2
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dss 3
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dssall
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dst 5,4,1
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dstt 8,7,0
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dstst 5,6,3
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dststt 4,5,2
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@ -0,0 +1,31 @@
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#as: -a32 -mpower6
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#objdump: -dr -Mpower6
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#name: POWER6 tests (includes DFP and Altivec)
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.*: +file format elf32-powerpc.*
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Disassembly of section \.text:
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0+00 <start>:
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0: 4c 00 03 24 doze
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4: 4c 00 03 64 nap
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8: 4c 00 03 a4 sleep
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c: 4c 00 03 e4 rvwinkle
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10: 7c 83 01 34 prtyw r3,r4
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14: 7d cd 01 74 prtyd r13,r14
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18: 7d 5c 02 a6 mfcfar r10
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1c: 7d 7c 03 a6 mtcfar r11
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20: 7c 83 2b f8 cmpb r3,r4,r5
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24: 7c c0 3c be mffgpr f6,r7
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28: 7d 00 4d be mftgpr r8,f9
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2c: 7d 4b 66 2a lwzcix r10,r11,r12
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30: 7d ae 7e 2e lfdpx f13,r14,r15
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34: ee 11 90 04 dadd f16,f17,f18
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38: fe 96 c0 04 daddq f20,f22,f24
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3c: 7c 60 06 6c dss 3
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40: 7e 00 06 6c dssall
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44: 7c 25 22 ac dst r5,r4,1
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48: 7e 08 3a ac dstt r8,r7,0
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4c: 7c 65 32 ec dstst r5,r6,3
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50: 7e 44 2a ec dststt r4,r5,2
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@ -0,0 +1,25 @@
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# PowerPC POWER6 AltiVec tests
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#as: -mpower6
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.section ".text"
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start:
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doze
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nap
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sleep
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rvwinkle
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prtyw 3,4
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prtyd 13,14
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mfcfar 10
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mtcfar 11
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cmpb 3,4,5
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mffgpr 6,7
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mftgpr 8,9
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lwzcix 10,11,12
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lfdpx 13,14,15
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dadd 16,17,18
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daddq 20,22,24
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dss 3
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dssall
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dst 5,4,1
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dstt 8,7,0
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dstst 5,6,3
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dststt 4,5,2
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@ -11,7 +11,6 @@ if { [istarget powerpc64*-*-*] || [istarget *-*-elf64*]} then {
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run_dump_test "astest2_64"
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run_dump_test "test1elf64"
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run_dump_test "power4"
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run_dump_test "cell"
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run_list_test "range64" "-a64"
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} elseif { [istarget powerpc*-*aix*] } then {
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run_dump_test "test1xcoff32"
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run_list_test "range" "-a32"
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run_dump_test "ppc750ps"
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run_dump_test "e500mc"
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run_dump_test "cell"
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run_dump_test "power6"
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}
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}
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