2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
* crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3, us4, us5 (respectively). Remove unsupported 'popa' instruction. Reverse operands order in store co-processor instructions.
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Tomer Levi
parent
645ea12c46
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396e337840
@ -84,24 +84,24 @@ const inst crx_instruction[] =
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/* Create a shift instruction. */
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#define SHIFT_INST(NAME, OPRD, OPC1, SHIFT1, OPC2) \
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/* OPRD=i3 -->> opc9 i3 r */ \
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/* OPRD=i4 -->> opc8 i4 r */ \
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/* OPRD=i5 -->> opc7 i5 r */ \
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/* OPRD=us3 -->> opc9 us3 r */ \
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/* OPRD=us4 -->> opc8 us4 r */ \
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/* OPRD=us5 -->> opc7 us5 r */ \
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{NAME, 1, OPC1, SHIFT1, SHIFT_INS, {{OPRD,20}, {regr,16}}}, \
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/* opc8 r r */ \
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{NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {regr,16}}}
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SHIFT_INST ("sllb", i3, 0x1F8, 23, 0x4D),
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SHIFT_INST ("srlb", i3, 0x1F9, 23, 0x4E),
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SHIFT_INST ("srab", i3, 0x1FA, 23, 0x4F),
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SHIFT_INST ("sllb", us3, 0x1F8, 23, 0x4D),
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SHIFT_INST ("srlb", us3, 0x1F9, 23, 0x4E),
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SHIFT_INST ("srab", us3, 0x1FA, 23, 0x4F),
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SHIFT_INST ("sllw", i4, 0xB6, 24, 0x5D),
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SHIFT_INST ("srlw", i4, 0xB7, 24, 0x5E),
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SHIFT_INST ("sraw", i4, 0xB8, 24, 0x5F),
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SHIFT_INST ("sllw", us4, 0xB6, 24, 0x5D),
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SHIFT_INST ("srlw", us4, 0xB7, 24, 0x5E),
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SHIFT_INST ("sraw", us4, 0xB8, 24, 0x5F),
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SHIFT_INST ("slld", i5, 0x78, 25, 0x6D),
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SHIFT_INST ("srld", i5, 0x79, 25, 0x6E),
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SHIFT_INST ("srad", i5, 0x7A, 25, 0x6F),
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SHIFT_INST ("slld", us5, 0x78, 25, 0x6D),
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SHIFT_INST ("srld", us5, 0x79, 25, 0x6E),
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SHIFT_INST ("srad", us5, 0x7A, 25, 0x6F),
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/* Create a conditional branch instruction. */
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#define BRANCH_INST(NAME, OPC) \
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@ -386,24 +386,24 @@ const inst crx_instruction[] =
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/* Store instructions (Immediate to Memory). */
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#define ST_I_INST(NAME, OPC) \
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/* opc12 i4 abs16 */ \
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{NAME, 2, 0x360+OPC, 20, STOR_IMM_INS, {{i4,16}, {abs16,0}}}, \
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/* opc12 i4 abs32 */ \
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{NAME, 3, 0x370+OPC, 20, STOR_IMM_INS, {{i4,16}, {abs32,0}}}, \
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/* opc12 i4 c4 rbase */ \
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{NAME, 1, 0x368+OPC, 20, LD_STOR_INS_INC, {{i4,16}, {rbase,12}}}, \
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/* opc12 i4 rbase disps12 */ \
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{NAME, 2, 0x368+OPC, 20, LD_STOR_INS_INC, {{i4,16}, {rbase_dispu12,12}}}, \
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/* opc4 i4 c4 rbase */ \
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{NAME, 1, 0x364+OPC, 20, STOR_IMM_INS, {{i4,16}, {rbase,12}}}, \
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/* opc12 i4 rbase disps12 */ \
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{NAME, 2, 0x364+OPC, 20, STOR_IMM_INS, {{i4,16}, {rbase_dispu12,12}}}, \
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/* opc12 i4 rbase disps28 */ \
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{NAME, 3, 0x374+OPC, 20, STOR_IMM_INS, {{i4,16}, {rbase_dispu28,12}}}, \
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/* opc12 i4 rbase ridx scl2 disps6 */ \
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{NAME, 2, 0x36C+OPC, 20, STOR_IMM_INS, {{i4,16}, {rbase_ridx_scl2_dispu6,0}}},\
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/* opc12 i4 rbase ridx scl2 disps22 */ \
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{NAME, 3, 0x37C+OPC, 20, STOR_IMM_INS, {{i4,16}, {rbase_ridx_scl2_dispu22,0}}}
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/* opc12 us4 abs16 */ \
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{NAME, 2, 0x360+OPC, 20, STOR_IMM_INS, {{us4,16}, {abs16,0}}}, \
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/* opc12 us4 abs32 */ \
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{NAME, 3, 0x370+OPC, 20, STOR_IMM_INS, {{us4,16}, {abs32,0}}}, \
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/* opc12 us4 c4 rbase */ \
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{NAME, 1, 0x368+OPC, 20, LD_STOR_INS_INC, {{us4,16}, {rbase,12}}}, \
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/* opc12 us4 rbase disps12 */ \
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{NAME, 2, 0x368+OPC, 20, LD_STOR_INS_INC, {{us4,16}, {rbase_dispu12,12}}}, \
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/* opc4 us4 c4 rbase */ \
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{NAME, 1, 0x364+OPC, 20, STOR_IMM_INS, {{us4,16}, {rbase,12}}}, \
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/* opc12 us4 rbase disps12 */ \
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{NAME, 2, 0x364+OPC, 20, STOR_IMM_INS, {{us4,16}, {rbase_dispu12,12}}}, \
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/* opc12 us4 rbase disps28 */ \
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{NAME, 3, 0x374+OPC, 20, STOR_IMM_INS, {{us4,16}, {rbase_dispu28,12}}}, \
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/* opc12 us4 rbase ridx scl2 disps6 */ \
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{NAME, 2, 0x36C+OPC, 20, STOR_IMM_INS, {{us4,16}, {rbase_ridx_scl2_dispu6,0}}}, \
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/* opc12 us4 rbase ridx scl2 disps22 */ \
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{NAME, 3, 0x37C+OPC, 20, STOR_IMM_INS, {{us4,16}, {rbase_ridx_scl2_dispu22,0}}}
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ST_REG_INST ("storb", 0x20, 0x4, DISPUB4),
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ST_I_INST ("storb", 0x0),
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@ -416,9 +416,9 @@ const inst crx_instruction[] =
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/* Create a bit instruction. */
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#define CSTBIT_INST(NAME, OP, OPC1, DIFF, SHIFT, OPC2) \
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/* OP=i3 -->> opc13 i3 */ \
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/* OP=i4 -->> opc12 i4 */ \
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/* OP=i5 -->> opc11 i5 */ \
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/* OP=us3 -->> opc13 us3 */ \
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/* OP=us4 -->> opc12 us4 */ \
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/* OP=us5 -->> opc11 us5 */ \
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\
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/* opcNN iN abs16 */ \
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{NAME, 2, OPC1+0*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {abs16,0}}}, \
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@ -435,28 +435,28 @@ const inst crx_instruction[] =
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/* opcNN iN rbase ridx scl2 disps22 */ \
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{NAME, 3, OPC1+5*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rbase_ridx_scl2_dispu22,0}}}
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CSTBIT_INST ("cbitb", i3, 0x700, 0x20, 19, 0x1FC),
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CSTBIT_INST ("cbitw", i4, 0x382, 0x10, 20, 0xBD),
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CSTBIT_INST ("cbitd", i5, 0x1C3, 0x8, 21, 0x7B),
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CSTBIT_INST ("cbitb", us3, 0x700, 0x20, 19, 0x1FC),
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CSTBIT_INST ("cbitw", us4, 0x382, 0x10, 20, 0xBD),
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CSTBIT_INST ("cbitd", us5, 0x1C3, 0x8, 21, 0x7B),
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{"cbitd", 2, 0x300838, 8, CSTBIT_INS, {{regr,4}, {regr,0}}},
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{"cbitd", 2, 0x18047B, 9, CSTBIT_INS, {{i5,4}, {regr,0}}},
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{"cbitd", 2, 0x18047B, 9, CSTBIT_INS, {{us5,4}, {regr,0}}},
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CSTBIT_INST ("sbitb", i3, 0x701, 0x20, 19, 0x1FD),
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CSTBIT_INST ("sbitw", i4, 0x383, 0x10, 20, 0xBE),
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CSTBIT_INST ("sbitd", i5, 0x1C4, 0x8, 21, 0x7C),
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CSTBIT_INST ("sbitb", us3, 0x701, 0x20, 19, 0x1FD),
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CSTBIT_INST ("sbitw", us4, 0x383, 0x10, 20, 0xBE),
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CSTBIT_INST ("sbitd", us5, 0x1C4, 0x8, 21, 0x7C),
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{"sbitd", 2, 0x300839, 8, CSTBIT_INS, {{regr,4}, {regr,0}}},
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{"sbitd", 2, 0x18047C, 9, CSTBIT_INS, {{i5,4}, {regr,0}}},
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{"sbitd", 2, 0x18047C, 9, CSTBIT_INS, {{us5,4}, {regr,0}}},
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CSTBIT_INST ("tbitb", i3, 0x702, 0x20, 19, 0x1FE),
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CSTBIT_INST ("tbitw", i4, 0x384, 0x10, 20, 0xBF),
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CSTBIT_INST ("tbitd", i5, 0x1C5, 0x8, 21, 0x7D),
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CSTBIT_INST ("tbitb", us3, 0x702, 0x20, 19, 0x1FE),
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CSTBIT_INST ("tbitw", us4, 0x384, 0x10, 20, 0xBF),
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CSTBIT_INST ("tbitd", us5, 0x1C5, 0x8, 21, 0x7D),
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{"tbitd", 2, 0x30083A, 8, CSTBIT_INS, {{regr,4}, {regr,0}}},
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{"tbitd", 2, 0x18047D, 9, CSTBIT_INS, {{i5,4}, {regr,0}}},
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{"tbitd", 2, 0x18047D, 9, CSTBIT_INS, {{us5,4}, {regr,0}}},
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/* Instructions including a register list (opcode is represented as a mask). */
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#define REGLIST_INST(NAME, OPC) \
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/* opc12 r mask16 */ \
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{NAME, 2, OPC, 20, REG_LIST, {{regr,16}, {i16,0}}}
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{NAME, 2, OPC, 20, REG_LIST, {{regr,16}, {us16,0}}}
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REG1_INST ("getrfid", 0xFF9),
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REG1_INST ("setrfid", 0xFFA),
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@ -474,7 +474,6 @@ const inst crx_instruction[] =
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REGLIST_INST ("loadm", 0x324),
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REGLIST_INST ("loadma", 0x325),
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REGLIST_INST ("popa", 0x325),
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REGLIST_INST ("storm", 0x344),
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REGLIST_INST ("storma", 0x345),
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@ -501,21 +500,21 @@ const inst crx_instruction[] =
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/* Create a CO-processor instruction. */
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#define COP_INST(NAME, OPC, TYPE, REG1, REG2) \
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/* opc12 c4 opc8 REG1 REG2 */ \
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{NAME, 2, 0x301030+OPC, 8, TYPE | FMT_2, {{i4,16}, {REG1,4}, {REG2,0}}}
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{NAME, 2, 0x301030+OPC, 8, TYPE | FMT_2, {{us4,16}, {REG1,4}, {REG2,0}}}
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COP_INST ("mtcr", 0, COP_REG_INS, regr, copregr),
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COP_INST ("mfcr", 1, COP_REG_INS, copregr, regr),
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COP_INST ("mtcsr", 2, COPS_REG_INS, regr, copsregr),
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COP_INST ("mfcsr", 3, COPS_REG_INS, copsregr, regr),
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COP_INST ("ldcr", 4, COP_REG_INS, regr, copregr),
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COP_INST ("stcr", 5, COP_REG_INS, regr, copregr),
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COP_INST ("stcr", 5, COP_REG_INS, copregr, regr),
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COP_INST ("ldcsr", 6, COPS_REG_INS, regr, copsregr),
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COP_INST ("stcsr", 7, COPS_REG_INS, regr, copsregr),
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COP_INST ("stcsr", 7, COPS_REG_INS, copsregr, regr),
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/* Create a memory-related CO-processor instruction. */
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#define COPMEM_INST(NAME, OPC, TYPE) \
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/* opc12 c4 opc12 r mask16 */ \
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{NAME, 3, 0x3110300+OPC, 4, TYPE | REG_LIST | FMT_5, {{i4,16}, {regr,0}, {i16,0}}}
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{NAME, 3, 0x3110300+OPC, 4, TYPE | REG_LIST | FMT_5, {{us4,16}, {regr,0}, {us16,0}}}
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COPMEM_INST("loadmcr", 0, COP_REG_INS),
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COPMEM_INST("stormcr", 1, COP_REG_INS),
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@ -523,35 +522,35 @@ const inst crx_instruction[] =
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COPMEM_INST("stormcsr", 3, COPS_REG_INS),
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/* CO-processor extensions. */
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/* opc12 c4 opc4 i4 disps9 */
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{"bcop", 2, 0x30107, 12, COP_BRANCH_INS | FMT_4, {{i4,16}, {i4,8}, {d9,0}}},
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/* opc12 c4 opc4 i4 disps25 */
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{"bcop", 3, 0x31107, 12, COP_BRANCH_INS | FMT_4, {{i4,16}, {i4,8}, {d25,0}}},
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/* opc12 c4 opc4 us4 disps9 */
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{"bcop", 2, 0x30107, 12, COP_BRANCH_INS | FMT_4, {{us4,16}, {us4,8}, {d9,0}}},
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/* opc12 c4 opc4 us4 disps25 */
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{"bcop", 3, 0x31107, 12, COP_BRANCH_INS | FMT_4, {{us4,16}, {us4,8}, {d25,0}}},
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/* opc12 c4 opc4 cpdo r r */
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{"cpdop", 2, 0x3010B, 12, COP_REG_INS | FMT_4, {{i4,16}, {i4,8}, {regr,4}, {regr,0}}},
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{"cpdop", 2, 0x3010B, 12, COP_REG_INS | FMT_4, {{us4,16}, {us4,8}, {regr,4}, {regr,0}}},
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/* opc12 c4 opc4 cpdo r r cpdo16 */
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{"cpdop", 3, 0x3110B, 12, COP_REG_INS | FMT_4, {{i4,16}, {i4,8}, {regr,4}, {regr,0}, {i16,0}}},
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{"cpdop", 3, 0x3110B, 12, COP_REG_INS | FMT_4, {{us4,16}, {us4,8}, {regr,4}, {regr,0}, {us16,0}}},
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/* esc16 r procreg */
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{"mtpr", 2, 0x3009, 16, 0, {{regr8,8}, {regr8,0}}},
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/* esc16 procreg r */
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{"mfpr", 2, 0x300A, 16, 0, {{regr8,8}, {regr8,0}}},
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/* Miscellaneous. */
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/* opc12 i4 */
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{"excp", 1, 0xFFF, 20, 0, {{i4,16}}},
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/* opc28 i4 */
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{"cinv", 2, 0x3010000, 4, 0, {{i4,0}}},
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/* opc12 us4 */
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{"excp", 1, 0xFFF, 20, 0, {{us4,16}}},
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/* opc28 us4 */
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{"cinv", 2, 0x3010000, 4, 0, {{us4,0}}},
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/* opc9 i5 i5 i5 r r */
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{"ram", 2, 0x7C, 23, 0, {{i5,18}, {i5,13}, {i5,8}, {regr,4}, {regr,0}}},
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{"rim", 2, 0x7D, 23, 0, {{i5,18}, {i5,13}, {i5,8}, {regr,4}, {regr,0}}},
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/* opc9 us5 us5 us5 r r */
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{"ram", 2, 0x7C, 23, 0, {{us5,18}, {us5,13}, {us5,8}, {regr,4}, {regr,0}}},
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{"rim", 2, 0x7D, 23, 0, {{us5,18}, {us5,13}, {us5,8}, {regr,4}, {regr,0}}},
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/* opc9 i3 r */
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{"rotb", 1, 0x1FB, 23, 0, {{i3,20}, {regr,16}}},
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/* opc8 i4 r */
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{"rotw", 1, 0xB9, 24, 0, {{i4,20}, {regr,16}}},
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/* opc23 i5 r */
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{"rotd", 2, 0x180478, 9, 0, {{i5,4}, {regr,0}}},
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/* opc9 us3 r */
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{"rotb", 1, 0x1FB, 23, 0, {{us3,20}, {regr,16}}},
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/* opc8 us4 r */
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{"rotw", 1, 0xB9, 24, 0, {{us4,20}, {regr,16}}},
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/* opc23 us5 r */
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{"rotd", 2, 0x180478, 9, 0, {{us5,4}, {regr,0}}},
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{NULL, 0, 0, 0, 0, {{0, 0}}}
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};
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@ -642,13 +641,12 @@ const operand_entry crx_optab[] =
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{0, nullargs}, /* dummy */
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{4, arg_ic}, /* cst4 */
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{8, arg_c}, /* disps9 */
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{3, arg_ic}, /* i3 */
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{4, arg_ic}, /* i4 */
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{5, arg_ic}, /* i5 */
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{8, arg_ic}, /* i8 */
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{12, arg_ic}, /* i12 */
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{16, arg_ic}, /* i16 */
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{32, arg_ic}, /* i32 */
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{3, arg_ic}, /* us3 */
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{4, arg_ic}, /* us4 */
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{5, arg_ic}, /* us5 */
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{16, arg_ic}, /* us16 */
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{4, arg_c}, /* d5 */
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{8, arg_c}, /* d9 */
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{16, arg_c}, /* d17 */
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