x86: fix operand size checking
Currently mov to/from control, debug, and test register insns accept any size GPR operand (general pattern: templates with D set and both operands being registers in distinct register files). This is due to improper checking of the reverse case, including not informing the caller whether a straight and/or reverse match was successful. The helper functions need to be told two indexes: One to index the given operand types array, and the other to index the template one. The caller must attempt a further straight match only if the function reported a straight match (and respectively for reverse matches).
This commit is contained in:
Jan Beulich
Jan Beulich
parent
4ad422a635
commit
3ac21baa84
@ -1,3 +1,19 @@
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2018-07-16 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (match_reg_size): Split second parameter
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into two.
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(match_simd_size): Likewise.
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(match_mem_size): Likewise.
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(MATCH_STRAIGHT, MATCH_REVERSE): Define.
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(operand_size_match): Change return type. New local variable
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"match". Always check for reverse match when opcode_modifier.d
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is set.
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(match_template) New local variable "size_match". Skip further
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matching if operand_size_match() did not report a respective
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match.
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* testsuite/gas/i386/inval.s: Add control register reads/writes.
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* testsuite/gas/i386/inval.l: Adjust expectations.
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2018-07-13 Nick Clifton <nickc@redhat.com>
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* testsuite/gas/elf/missing-build-notes.s: New test. Checks that
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@ -1901,70 +1901,74 @@ operand_type_check (i386_operand_type t, enum operand_type c)
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operand J for instruction template T. */
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static INLINE int
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match_reg_size (const insn_template *t, unsigned int j)
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match_reg_size (const insn_template *t, unsigned int wanted, unsigned int given)
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{
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return !((i.types[j].bitfield.byte
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&& !t->operand_types[j].bitfield.byte)
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|| (i.types[j].bitfield.word
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&& !t->operand_types[j].bitfield.word)
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|| (i.types[j].bitfield.dword
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&& !t->operand_types[j].bitfield.dword)
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|| (i.types[j].bitfield.qword
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&& !t->operand_types[j].bitfield.qword)
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|| (i.types[j].bitfield.tbyte
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&& !t->operand_types[j].bitfield.tbyte));
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return !((i.types[given].bitfield.byte
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&& !t->operand_types[wanted].bitfield.byte)
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|| (i.types[given].bitfield.word
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&& !t->operand_types[wanted].bitfield.word)
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|| (i.types[given].bitfield.dword
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&& !t->operand_types[wanted].bitfield.dword)
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|| (i.types[given].bitfield.qword
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&& !t->operand_types[wanted].bitfield.qword)
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|| (i.types[given].bitfield.tbyte
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&& !t->operand_types[wanted].bitfield.tbyte));
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}
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/* Return 1 if there is no conflict in SIMD register on
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operand J for instruction template T. */
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static INLINE int
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match_simd_size (const insn_template *t, unsigned int j)
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match_simd_size (const insn_template *t, unsigned int wanted, unsigned int given)
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{
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return !((i.types[j].bitfield.xmmword
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&& !t->operand_types[j].bitfield.xmmword)
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|| (i.types[j].bitfield.ymmword
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&& !t->operand_types[j].bitfield.ymmword)
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|| (i.types[j].bitfield.zmmword
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&& !t->operand_types[j].bitfield.zmmword));
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return !((i.types[given].bitfield.xmmword
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&& !t->operand_types[wanted].bitfield.xmmword)
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|| (i.types[given].bitfield.ymmword
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&& !t->operand_types[wanted].bitfield.ymmword)
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|| (i.types[given].bitfield.zmmword
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&& !t->operand_types[wanted].bitfield.zmmword));
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}
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/* Return 1 if there is no conflict in any size on operand J for
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instruction template T. */
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static INLINE int
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match_mem_size (const insn_template *t, unsigned int j)
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match_mem_size (const insn_template *t, unsigned int wanted, unsigned int given)
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{
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return (match_reg_size (t, j)
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&& !((i.types[j].bitfield.unspecified
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return (match_reg_size (t, wanted, given)
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&& !((i.types[given].bitfield.unspecified
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&& !i.broadcast
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&& !t->operand_types[j].bitfield.unspecified)
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|| (i.types[j].bitfield.fword
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&& !t->operand_types[j].bitfield.fword)
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&& !t->operand_types[wanted].bitfield.unspecified)
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|| (i.types[given].bitfield.fword
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&& !t->operand_types[wanted].bitfield.fword)
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/* For scalar opcode templates to allow register and memory
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operands at the same time, some special casing is needed
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here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
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down-conversion vpmov*. */
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|| ((t->operand_types[j].bitfield.regsimd
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|| ((t->operand_types[wanted].bitfield.regsimd
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&& !t->opcode_modifier.broadcast
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&& (t->operand_types[j].bitfield.byte
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|| t->operand_types[j].bitfield.word
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|| t->operand_types[j].bitfield.dword
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|| t->operand_types[j].bitfield.qword))
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? (i.types[j].bitfield.xmmword
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|| i.types[j].bitfield.ymmword
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|| i.types[j].bitfield.zmmword)
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: !match_simd_size(t, j))));
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&& (t->operand_types[wanted].bitfield.byte
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|| t->operand_types[wanted].bitfield.word
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|| t->operand_types[wanted].bitfield.dword
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|| t->operand_types[wanted].bitfield.qword))
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? (i.types[given].bitfield.xmmword
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|| i.types[given].bitfield.ymmword
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|| i.types[given].bitfield.zmmword)
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: !match_simd_size(t, wanted, given))));
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}
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/* Return 1 if there is no size conflict on any operands for
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instruction template T. */
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/* Return value has MATCH_STRAIGHT set if there is no size conflict on any
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operands for instruction template T, and it has MATCH_REVERSE set if there
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is no size conflict on any operands for the template with operands reversed
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(and the template allows for reversing in the first place). */
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static INLINE int
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#define MATCH_STRAIGHT 1
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#define MATCH_REVERSE 2
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static INLINE unsigned int
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operand_size_match (const insn_template *t)
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{
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unsigned int j;
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int match = 1;
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unsigned int j, match = MATCH_STRAIGHT;
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/* Don't check jump instructions. */
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if (t->opcode_modifier.jump
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@ -1981,59 +1985,57 @@ operand_size_match (const insn_template *t)
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continue;
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if (t->operand_types[j].bitfield.reg
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&& !match_reg_size (t, j))
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&& !match_reg_size (t, j, j))
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{
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match = 0;
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break;
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}
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if (t->operand_types[j].bitfield.regsimd
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&& !match_simd_size (t, j))
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&& !match_simd_size (t, j, j))
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{
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match = 0;
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break;
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}
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if (t->operand_types[j].bitfield.acc
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&& (!match_reg_size (t, j) || !match_simd_size (t, j)))
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&& (!match_reg_size (t, j, j) || !match_simd_size (t, j, j)))
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{
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match = 0;
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break;
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}
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if (i.types[j].bitfield.mem && !match_mem_size (t, j))
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if (i.types[j].bitfield.mem && !match_mem_size (t, j, j))
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{
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match = 0;
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break;
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}
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}
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if (match)
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return match;
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else if (!t->opcode_modifier.d)
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if (!t->opcode_modifier.d)
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{
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mismatch:
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i.error = operand_size_mismatch;
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return 0;
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if (!match)
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i.error = operand_size_mismatch;
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return match;
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}
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/* Check reverse. */
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gas_assert (i.operands == 2);
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match = 1;
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for (j = 0; j < 2; j++)
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{
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if ((t->operand_types[j].bitfield.reg
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|| t->operand_types[j].bitfield.acc)
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&& !match_reg_size (t, j ? 0 : 1))
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&& !match_reg_size (t, j, !j))
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goto mismatch;
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if (i.types[j].bitfield.mem
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&& !match_mem_size (t, j ? 0 : 1))
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if (i.types[!j].bitfield.mem
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&& !match_mem_size (t, j, !j))
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goto mismatch;
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}
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return match;
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return match | MATCH_REVERSE;
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}
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static INLINE int
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@ -5286,7 +5288,7 @@ match_template (char mnem_suffix)
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i386_operand_type operand_types [MAX_OPERANDS];
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int addr_prefix_disp;
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unsigned int j;
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unsigned int found_cpu_match;
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unsigned int found_cpu_match, size_match;
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unsigned int check_register;
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enum i386_error specific_error = 0;
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@ -5375,7 +5377,8 @@ match_template (char mnem_suffix)
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|| (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
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continue;
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if (!operand_size_match (t))
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size_match = operand_size_match (t);
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if (!size_match)
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continue;
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for (j = 0; j < MAX_OPERANDS; j++)
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@ -5502,6 +5505,8 @@ match_template (char mnem_suffix)
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&& i.types[0].bitfield.acc
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&& operand_type_check (i.types[1], anymem))
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continue;
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if (!(size_match & MATCH_STRAIGHT))
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goto check_reverse;
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/* If we want store form, we reverse direction of operands. */
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if (i.dir_encoding == dir_encoding_store
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&& t->opcode_modifier.d)
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@ -5531,6 +5536,8 @@ match_template (char mnem_suffix)
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continue;
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check_reverse:
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if (!(size_match & MATCH_REVERSE))
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continue;
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/* Try reversing direction of operands. */
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overlap0 = operand_type_and (i.types[0], operand_types[1]);
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overlap1 = operand_type_and (i.types[1], operand_types[0]);
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@ -59,11 +59,10 @@
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.*:63: Error: .*
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.*:64: Error: .*
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.*:65: Error: .*
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.*:68: Error: .*
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.*:69: Error: .*
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.*:70: Error: .*
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.*:71: Error: .*
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.*:72: Error: .*
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.*:67: Error: .*mov.*
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.*:68: Error: .*mov.*
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.*:69: Error: .*mov.*
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.*:70: Error: .*mov.*
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.*:73: Error: .*
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.*:74: Error: .*
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.*:75: Error: .*
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@ -75,14 +74,19 @@
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.*:81: Error: .*
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.*:82: Error: .*
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.*:83: Error: .*
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.*:84: Error: .*
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.*:85: Error: .*
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.*:86: Error: .*
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.*:87: Error: .*
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.*:88: Error: .*
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.*:90: Error: .*
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.*:92: Error: .*shl.*
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.*:93: Error: .*rol.*
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.*:94: Error: .*rcl.*
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.*:91: Error: .*
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.*:92: Error: .*
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.*:93: Error: .*
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.*:95: Error: .*
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.*:97: Error: .*shl.*
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.*:98: Error: .*rol.*
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.*:99: Error: .*rcl.*
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GAS LISTING .*
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@ -155,30 +159,35 @@ GAS LISTING .*
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[ ]*64[ ]+add \(%eiz\), %eax
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[ ]*65[ ]+add \(%eax\), %eiz
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[ ]*66[ ]+
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[ ]*67[ ]+\.intel_syntax noprefix
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[ ]*68[ ]+cvtsi2ss xmm1,QWORD PTR \[eax\]
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[ ]*69[ ]+cvtsi2sd xmm1,QWORD PTR \[eax\]
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[ ]*70[ ]+cvtsi2ssq xmm1,QWORD PTR \[eax\]
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[ ]*71[ ]+cvtsi2sdq xmm1,QWORD PTR \[eax\]
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[ ]*72[ ]+movq xmm1, XMMWORD PTR \[esp\]
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[ ]*73[ ]+movq xmm1, DWORD PTR \[esp\]
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[ ]*74[ ]+movq xmm1, WORD PTR \[esp\]
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[ ]*75[ ]+movq xmm1, BYTE PTR \[esp\]
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[ ]*76[ ]+movq XMMWORD PTR \[esp\],xmm1
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[ ]*77[ ]+movq DWORD PTR \[esp\],xmm1
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[ ]*78[ ]+movq WORD PTR \[esp\],xmm1
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[ ]*79[ ]+movq BYTE PTR \[esp\],xmm1
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[ ]*80[ ]+fnstsw eax
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[ ]*81[ ]+fnstsw al
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[ ]*82[ ]+fstsw eax
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[ ]*83[ ]+fstsw al
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[ ]*84[ ]+
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[ ]*85[ ]+movsx ax, \[eax\]
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[ ]*86[ ]+movsx eax, \[eax\]
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[ ]*87[ ]+movzx ax, \[eax\]
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[ ]*88[ ]+movzx eax, \[eax\]
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[ ]*89[ ]+
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[ ]*90[ ]+movnti word ptr \[eax\], ax
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[ ]*[1-9][0-9]*[ ]+mov %cr0, %di
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[ ]*[1-9][0-9]*[ ]+mov %ax, %cr7
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[ ]*[1-9][0-9]*[ ]+mov %cr0, %bh
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[ ]*[1-9][0-9]*[ ]+mov %al, %cr7
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[ ]*[1-9][0-9]*[ ]+
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[ ]*[1-9][0-9]*[ ]+\.intel_syntax noprefix
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[ ]*[1-9][0-9]*[ ]+cvtsi2ss xmm1,QWORD PTR \[eax\]
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[ ]*[1-9][0-9]*[ ]+cvtsi2sd xmm1,QWORD PTR \[eax\]
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[ ]*[1-9][0-9]*[ ]+cvtsi2ssq xmm1,QWORD PTR \[eax\]
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[ ]*[1-9][0-9]*[ ]+cvtsi2sdq xmm1,QWORD PTR \[eax\]
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[ ]*[1-9][0-9]*[ ]+movq xmm1, XMMWORD PTR \[esp\]
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[ ]*[1-9][0-9]*[ ]+movq xmm1, DWORD PTR \[esp\]
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[ ]*[1-9][0-9]*[ ]+movq xmm1, WORD PTR \[esp\]
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[ ]*[1-9][0-9]*[ ]+movq xmm1, BYTE PTR \[esp\]
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[ ]*[1-9][0-9]*[ ]+movq XMMWORD PTR \[esp\],xmm1
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[ ]*[1-9][0-9]*[ ]+movq DWORD PTR \[esp\],xmm1
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[ ]*[1-9][0-9]*[ ]+movq WORD PTR \[esp\],xmm1
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[ ]*[1-9][0-9]*[ ]+movq BYTE PTR \[esp\],xmm1
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[ ]*[1-9][0-9]*[ ]+fnstsw eax
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[ ]*[1-9][0-9]*[ ]+fnstsw al
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[ ]*[1-9][0-9]*[ ]+fstsw eax
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[ ]*[1-9][0-9]*[ ]+fstsw al
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[ ]*[1-9][0-9]*[ ]+
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[ ]*[1-9][0-9]*[ ]+movsx ax, \[eax\]
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[ ]*[1-9][0-9]*[ ]+movsx eax, \[eax\]
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[ ]*[1-9][0-9]*[ ]+movzx ax, \[eax\]
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[ ]*[1-9][0-9]*[ ]+movzx eax, \[eax\]
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[ ]*[1-9][0-9]*[ ]+
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[ ]*[1-9][0-9]*[ ]+movnti word ptr \[eax\], ax
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[ ]*[1-9][0-9]*[ ]+
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[ ]*[1-9][0-9]*[ ]+shl \[eax\], 1
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[ ]*[1-9][0-9]*[ ]+rol \[ecx\], 2
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@ -64,6 +64,11 @@ movntiw %ax, (%eax)
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add (%eiz), %eax
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add (%eax), %eiz
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mov %cr0, %di
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mov %ax, %cr7
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mov %cr0, %bh
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mov %al, %cr7
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.intel_syntax noprefix
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cvtsi2ss xmm1,QWORD PTR [eax]
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cvtsi2sd xmm1,QWORD PTR [eax]
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