* sim-if.c (sim_do_command): Handle "sim info reg {bbpsw,bbpc}".
Bring over from branch.
This commit is contained in:
Doug Evans
parent
84e42e1daf
commit
3afece8646
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@ -1,5 +1,12 @@
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Mon Oct 19 14:13:05 1998 Doug Evans <devans@seba.cygnus.com>
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* sim-main.h: #include cpu-opc.h.
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* arch.c,arch.h,decode.c,extract.c,model.c,sem.c: Regenerate
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to get #include cleanup.
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start-sanitize-m32rx
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* decodex.c,extractx.c,modelx.c: Ditto.
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end-sanitize-m32rx
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* Makefile.in (SIM_EXTRA_DEPS): Replace cgen headers with
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CGEN_INCLUDE_DEPS.
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(M32RBF_INCLUDE_DEPS): Define.
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@ -16,6 +23,10 @@ start-sanitize-m32rx
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* cpux.h: Regenerate.
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end-sanitize-m32rx
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Fri Oct 16 09:15:29 1998 Doug Evans <devans@charmed.cygnus.com>
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* sim-if.c (sim_do_command): Handle "sim info reg {bbpsw,bbpc}".
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Wed Oct 14 14:49:50 1998 Doug Evans <devans@canuck.cygnus.com>
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* Makefile.in (mloop.o): Don't depend on stamp-cpu, depend on
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@ -1,4 +1,4 @@
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/* Main simulator entry points for the M32R.
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/* Main simulator entry points specific to the M32R.
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Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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@ -51,6 +51,7 @@ sim_open (kind, callback, abfd, argv)
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struct _bfd *abfd;
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char **argv;
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{
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char c;
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SIM_DESC sd = sim_state_alloc (kind, callback);
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/* The cpu data is kept in a separately allocated chunk of memory. */
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@ -83,21 +84,6 @@ sim_open (kind, callback, abfd, argv)
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sim_add_option_table (sd, extra_options);
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#endif
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/* Allocate core managed memory */
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sim_do_commandf (sd, "memory region 0,0x%lx", M32R_DEFAULT_MEM_SIZE);
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/* Allocate a handler for the control registers and other devices.
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All are allocated in one chunk to keep things from being
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unnecessarily complicated. */
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sim_core_attach (sd, NULL,
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0 /*level*/,
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access_read_write,
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0 /*space ???*/,
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M32R_DEVICE_ADDR, M32R_DEVICE_LEN /*nr_bytes*/,
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0 /*modulo*/,
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&m32r_devices,
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NULL /*buffer*/);
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/* getopt will print the error message so we just have to exit if this fails.
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FIXME: Hmmm... in the case of gdb we need getopt to call
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print_filtered. */
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@ -107,6 +93,25 @@ sim_open (kind, callback, abfd, argv)
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return 0;
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}
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/* Allocate a handler for the control registers and other devices
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if no memory for that range has been allocated by the user.
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All are allocated in one chunk to keep things from being
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unnecessarily complicated. */
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if (sim_core_read_buffer (sd, NULL, read_map, &c, M32R_DEVICE_ADDR, 1) == 0)
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sim_core_attach (sd, NULL,
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0 /*level*/,
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access_read_write,
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0 /*space ???*/,
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M32R_DEVICE_ADDR, M32R_DEVICE_LEN /*nr_bytes*/,
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0 /*modulo*/,
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&m32r_devices,
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NULL /*buffer*/);
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/* Allocate core managed memory if none specified by user.
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Use address 4 here in case the user wanted address 0 unmapped. */
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if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
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sim_do_commandf (sd, "memory region 0,0x%lx", M32R_DEFAULT_MEM_SIZE);
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/* check for/establish the reference program image */
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if (sim_analyze_program (sd,
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(STATE_PROG_ARGV (sd) != NULL
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@ -186,8 +191,8 @@ sim_open (kind, callback, abfd, argv)
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for (c = 0; c < MAX_NR_PROCESSORS; ++c)
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{
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/* Only needed for profiling, but the structure member is small. */
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memset (& CPU_M32R_MISC_PROFILE (STATE_CPU (sd, c)), 0,
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sizeof (CPU_M32R_MISC_PROFILE (STATE_CPU (sd, c))));
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memset (CPU_M32R_MISC_PROFILE (STATE_CPU (sd, c)), 0,
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sizeof (* CPU_M32R_MISC_PROFILE (STATE_CPU (sd, c))));
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/* Hook in callback for reporting these stats */
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PROFILE_INFO_CPU_CALLBACK (CPU_PROFILE_DATA (STATE_CPU (sd, c)))
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= print_m32r_misc_cpu;
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@ -234,73 +239,6 @@ sim_create_inferior (sd, abfd, argv, envp)
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return SIM_RC_OK;
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}
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int
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sim_stop (SIM_DESC sd)
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{
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switch (STATE_ARCHITECTURE (sd)->mach)
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{
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case bfd_mach_m32r :
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return m32r_engine_stop (sd, NULL, NULL_CIA, sim_stopped, SIM_SIGINT);
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/* start-sanitize-m32rx */
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#ifdef HAVE_CPU_M32RX
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case bfd_mach_m32rx :
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return m32rx_engine_stop (sd, NULL, NULL_CIA, sim_stopped, SIM_SIGINT);
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#endif
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/* end-sanitize-m32rx */
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default :
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abort ();
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}
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}
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/* This isn't part of the official interface.
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This is just a good place to put this for now. */
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void
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sim_sync_stop (SIM_DESC sd, SIM_CPU *cpu, PCADDR pc, enum sim_stop reason, int sigrc)
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{
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switch (STATE_ARCHITECTURE (sd)->mach)
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{
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case bfd_mach_m32r :
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(void) m32r_engine_stop (sd, cpu, pc, reason, sigrc);
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break;
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/* start-sanitize-m32rx */
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#ifdef HAVE_CPU_M32RX
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case bfd_mach_m32rx :
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(void) m32rx_engine_stop (sd, cpu, pc, reason, sigrc);
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break;
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#endif
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/* end-sanitize-m32rx */
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default :
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abort ();
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}
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}
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void
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sim_resume (sd, step, siggnal)
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SIM_DESC sd;
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int step, siggnal;
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{
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sim_module_resume (sd);
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switch (STATE_ARCHITECTURE (sd)->mach)
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{
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case bfd_mach_m32r :
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m32r_engine_run (sd, step, siggnal);
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break;
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/* start-sanitize-m32rx */
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#ifdef HAVE_CPU_M32RX
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case bfd_mach_m32rx :
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m32rx_engine_run (sd, step, siggnal);
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break;
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#endif
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/* end-sanitize-m32rx */
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default :
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abort ();
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}
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sim_module_suspend (sd);
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}
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/* PROFILE_CPU_CALLBACK */
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static void
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@ -315,88 +253,59 @@ print_m32r_misc_cpu (SIM_CPU *cpu, int verbose)
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sim_io_printf (sd, " %-*s %s\n\n",
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PROFILE_LABEL_WIDTH, "Fill nops:",
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sim_add_commas (buf, sizeof (buf),
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CPU_M32R_MISC_PROFILE (cpu).fillnop_count));
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CPU_M32R_MISC_PROFILE (cpu)->fillnop_count));
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if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32rx)
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sim_io_printf (sd, " %-*s %s\n\n",
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PROFILE_LABEL_WIDTH, "Parallel insns:",
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sim_add_commas (buf, sizeof (buf),
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CPU_M32R_MISC_PROFILE (cpu).parallel_count));
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CPU_M32R_MISC_PROFILE (cpu)->parallel_count));
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}
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}
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/* The contents of BUF are in target byte order. */
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int
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sim_fetch_register (sd, rn, buf, length)
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SIM_DESC sd;
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int rn;
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unsigned char *buf;
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int length;
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{
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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return (* CPU_REG_FETCH (cpu)) (cpu, rn, buf, length);
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}
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/* The contents of BUF are in target byte order. */
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int
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sim_store_register (sd, rn, buf, length)
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SIM_DESC sd;
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int rn;
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unsigned char *buf;
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int length;
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{
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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return (* CPU_REG_STORE (cpu)) (cpu, rn, buf, length);
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}
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void
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sim_do_command (sd, cmd)
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SIM_DESC sd;
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char *cmd;
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{
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if (sim_args_command (sd, cmd) != SIM_RC_OK)
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sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
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}
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/* Utility fns to access registers, without knowing the current mach. */
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char **argv;
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SI
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h_gr_get (SIM_CPU *current_cpu, UINT regno)
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{
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switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
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{
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case bfd_mach_m32r :
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return m32r_h_gr_get (current_cpu, regno);
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/* start-sanitize-m32rx */
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#ifdef HAVE_CPU_M32RX
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case bfd_mach_m32rx :
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return m32rx_h_gr_get (current_cpu, regno);
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#endif
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/* end-sanitize-m32rx */
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default :
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abort ();
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}
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}
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if (cmd == NULL)
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return;
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void
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h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
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{
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switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
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argv = buildargv (cmd);
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if (argv[0] != NULL
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&& strcasecmp (argv[0], "info") == 0
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&& argv[1] != NULL
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&& strncasecmp (argv[1], "reg", 3) == 0)
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{
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case bfd_mach_m32r :
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m32r_h_gr_set (current_cpu, regno, newval);
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break;
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/* start-sanitize-m32rx */
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#ifdef HAVE_CPU_M32RX
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case bfd_mach_m32rx :
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m32rx_h_gr_set (current_cpu, regno, newval);
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break;
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#endif
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/* end-sanitize-m32rx */
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default :
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abort ();
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SI val;
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/* We only support printing bbpsw,bbpc here as there is no equivalent
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functionality in gdb. */
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if (argv[2] == NULL)
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sim_io_eprintf (sd, "Missing register in `%s'\n", cmd);
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else if (argv[3] != NULL)
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sim_io_eprintf (sd, "Too many arguments in `%s'\n", cmd);
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else if (strcasecmp (argv[2], "bbpsw") == 0)
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{
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val = a_m32r_h_cr_get (STATE_CPU (sd, 0), H_CR_BBPSW);
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sim_io_printf (sd, "bbpsw 0x%x %d\n", val, val);
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}
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else if (strcasecmp (argv[2], "bbpc") == 0)
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{
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val = a_m32r_h_cr_get (STATE_CPU (sd, 0), H_CR_BBPC);
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sim_io_printf (sd, "bbpc 0x%x %d\n", val, val);
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}
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else
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sim_io_eprintf (sd, "Printing of register `%s' not supported with `sim info'\n",
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argv[2]);
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}
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else
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{
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if (sim_args_command (sd, cmd) != SIM_RC_OK)
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sim_io_eprintf (sd, "Unknown sim command `%s'\n", cmd);
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}
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freeargv (argv);
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}
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