OpenE2K/binutils-gdb
12
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

2007-04-04 Paul Brook <paul@codesourcery.com>

Browse Source 
gas/
	* config/tc-arm.c (do_neon_ext): Enforce immediate range.
	(insns): Use I15 for vext.

	gas/testsute/
	* gas/arm/neon-cov.s: Add new vext test.
	* gas/arm/neon-cov.d: Ditto.
This commit is contained in:
Paul Brook 2007-04-04 19:21:24 +00:00
parent 9fcfe2ed35
commit 3b8d421e14
5 changed files with 15 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
gas/ChangeLog
View File

@ -1,3 +1,8 @@
2007-04-04 Paul Brook <paul@codesourcery.com>
* config/tc-arm.c (do_neon_ext): Enforce immediate range.
(insns): Use I15 for vext.
2007-04-04 Paul Brook <paul@codesourcery.com> 2007-04-04 Paul Brook <paul@codesourcery.com>
* configure.tgt: Loosen checks for arm uclinux eabi targets. * configure.tgt: Loosen checks for arm uclinux eabi targets.

5
gas/config/tc-arm.c
View File

@ -12815,6 +12815,7 @@ do_neon_ext (void)
struct neon_type_el et = neon_check_type (3, rs, struct neon_type_el et = neon_check_type (3, rs,
N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY); N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
unsigned imm = (inst.operands[3].imm * et.size) / 8; unsigned imm = (inst.operands[3].imm * et.size) / 8;
constraint (imm >= (neon_quad (rs) ? 16 : 8), _("shift out of range"));
inst.instruction |= LOW4 (inst.operands[0].reg) << 12; inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
inst.instruction |= HI1 (inst.operands[0].reg) << 22; inst.instruction |= HI1 (inst.operands[0].reg) << 22;
inst.instruction |= LOW4 (inst.operands[1].reg) << 16; inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
@ -15927,8 +15928,8 @@ static const struct asm_opcode insns[] =
nUF(vmull, vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull), nUF(vmull, vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
/* Extract. Size 8. */ /* Extract. Size 8. */
NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I7), neon_ext), NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I7), neon_ext), NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
/* Two registers, miscellaneous. */ /* Two registers, miscellaneous. */
/* Reverse. Sizes 8 16 32 (must be < size in opcode). */ /* Reverse. Sizes 8 16 32 (must be < size in opcode). */

5
gas/testsuite/ChangeLog
View File

@ -1,3 +1,8 @@
2007-04-04 Paul Brook <paul@codesourcery.com>
* gas/arm/neon-cov.s: Add new vext test.
* gas/arm/neon-cov.d: Ditto.
2007-04-01 Christian Groessler <chris@groessler.org> 2007-04-01 Christian Groessler <chris@groessler.org>
* gas/z8k/calr.d: Fix for 64bit bfd. * gas/z8k/calr.d: Fix for 64bit bfd.

1
gas/testsuite/gas/arm/neon-cov.d
View File

@ -1338,6 +1338,7 @@ Disassembly of section \.text:
0[0-9a-f]+ <[^>]+> f2b00040 vext\.8 q0, q0, q0, #0 0[0-9a-f]+ <[^>]+> f2b00040 vext\.8 q0, q0, q0, #0
0[0-9a-f]+ <[^>]+> f2b00040 vext\.8 q0, q0, q0, #0 0[0-9a-f]+ <[^>]+> f2b00040 vext\.8 q0, q0, q0, #0
0[0-9a-f]+ <[^>]+> f2b00000 vext\.8 d0, d0, d0, #0 0[0-9a-f]+ <[^>]+> f2b00000 vext\.8 d0, d0, d0, #0
0[0-9a-f]+ <[^>]+> f2b00840 vext\.8 q0, q0, q0, #8
0[0-9a-f]+ <[^>]+> f3b00040 vrev64\.8 q0, q0 0[0-9a-f]+ <[^>]+> f3b00040 vrev64\.8 q0, q0
0[0-9a-f]+ <[^>]+> f3b00040 vrev64\.8 q0, q0 0[0-9a-f]+ <[^>]+> f3b00040 vrev64\.8 q0, q0
0[0-9a-f]+ <[^>]+> f3b00000 vrev64\.8 d0, d0 0[0-9a-f]+ <[^>]+> f3b00000 vrev64\.8 d0, d0

1
gas/testsuite/gas/arm/neon-cov.s
View File

@ -561,6 +561,7 @@
vext.8 q0,q0,q0,0 vext.8 q0,q0,q0,0
vextq.8 q0,q0,q0,0 vextq.8 q0,q0,q0,0
vext.8 d0,d0,d0,0 vext.8 d0,d0,d0,0
vext.8 q0,q0,q0,8
.macro revs op opq vtype .macro revs op opq vtype
\op\vtype q0,q0 \op\vtype q0,q0