Thu Dec 3 14:20:03 1998 Dave Brolley <brolley@cygnus.com>
* sim/fr30: New Directory.
This commit is contained in:
Dave Brolley
parent
37b0c1aa72
commit
3bf9790595
|
|
@ -1,3 +1,13 @@
|
|||
Thu Dec 3 14:20:03 1998 Dave Brolley <brolley@cygnus.com>
|
||||
|
||||
* sim/fr30: New Directory.
|
||||
|
||||
Wed Nov 18 10:50:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
|
||||
|
||||
* common/bits-gen.c (main): Add BYTE_ORDER so that it matches
|
||||
recent sim/common/sim-basics.h changes.
|
||||
* common/Makefile.in: Update.
|
||||
|
||||
Fri Oct 30 00:37:31 1998 Felix Lee <flee@cygnus.com>
|
||||
|
||||
* lib/sim-defs.exp (sim_run): download target program to remote
|
||||
|
|
|
|||
|
|
@ -0,0 +1,75 @@
|
|||
# .Sanitize for devo/sim/testsuite/sim/m32r
|
||||
|
||||
# Each directory to survive it's way into a release will need a file
|
||||
# like this one called "./.Sanitize". All keyword lines must exist,
|
||||
# and must exist in the order specified by this file. Each directory
|
||||
# in the tree will be processed, top down, in the following order.
|
||||
|
||||
# Hash started lines like this one are comments and will be deleted
|
||||
# before anything else is done. Blank lines will also be squashed
|
||||
# out.
|
||||
|
||||
# The lines between the "Do-first:" line and the "Things-to-keep:"
|
||||
# line are executed as a /bin/sh shell script before anything else is
|
||||
# done in this
|
||||
|
||||
Do-first:
|
||||
|
||||
Things-to-keep:
|
||||
|
||||
allinsn.exp
|
||||
testutils.inc
|
||||
|
||||
add.cgs
|
||||
add.ms
|
||||
add2.cgs
|
||||
addc.cgs
|
||||
addn.cgs
|
||||
addn2.cgs
|
||||
and.cgs
|
||||
andb.cgs
|
||||
andh.cgs
|
||||
asr.cgs
|
||||
asr2.cgs
|
||||
bandh.cgs
|
||||
bandl.cgs
|
||||
beorh.cgs
|
||||
beorl.cgs
|
||||
borh.cgs
|
||||
borl.cgs
|
||||
btsth.cgs
|
||||
btstl.cgs
|
||||
cmp.cgs
|
||||
cmp2.cgs
|
||||
eor.cgs
|
||||
eorb.cgs
|
||||
eorh.cgs
|
||||
hello.ms
|
||||
hello.ms
|
||||
ld.cgs
|
||||
ldi20.cgs
|
||||
ldi32.cgs
|
||||
ldi8.cgs
|
||||
ldub.cgs
|
||||
lduh.cgs
|
||||
lsl.cgs
|
||||
lsl2.cgs
|
||||
lsr.cgs
|
||||
lsr2.cgs
|
||||
misc.exp
|
||||
mul.cgs
|
||||
mulh.cgs
|
||||
mulu.cgs
|
||||
muluh.cgs
|
||||
or.cgs
|
||||
orb.cgs
|
||||
orh.cgs
|
||||
sub.cgs
|
||||
subc.cgs
|
||||
subn.cgs
|
||||
|
||||
Things-to-lose:
|
||||
|
||||
Do-last:
|
||||
|
||||
# End of file.
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
# fr30 testcase for add $Rj,$Ri, add $u4,$Rj
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global add
|
||||
add:
|
||||
; Test add $Rj,$Ri
|
||||
mvi_h_gr 1,r7
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0f ; Set mask opposite of expected
|
||||
add r7,r8
|
||||
test_cc 0 0 0 0
|
||||
test_h_gr 3,r8
|
||||
|
||||
mvi_h_gr 0x7fffffff,r7
|
||||
mvi_h_gr 1,r8
|
||||
set_cc 0x05 ; Set mask opposite of expected
|
||||
add r7,r8
|
||||
test_cc 1 0 1 0
|
||||
test_h_gr 0x80000000,r8
|
||||
|
||||
set_cc 0x08 ; Set mask opposite of expected
|
||||
add r8,r8
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr 0,r8
|
||||
|
||||
; Test add $u4Ri
|
||||
mvi_h_gr 4,r8
|
||||
set_cc 0x0f ; Set mask opposite of expected
|
||||
add 0,r8
|
||||
test_cc 0 0 0 0
|
||||
test_h_gr 4,r8
|
||||
set_cc 0x0f ; Set mask opposite of expected
|
||||
add 1,r8
|
||||
test_cc 0 0 0 0
|
||||
test_h_gr 5,r8
|
||||
set_cc 0x0f ; Set mask opposite of expected
|
||||
add 15,r8
|
||||
test_cc 0 0 0 0
|
||||
test_h_gr 20,r8
|
||||
mvi_h_gr 0x7fffffff,r8 ; test neg and overflow bits
|
||||
set_cc 0x05 ; Set mask opposite of expected
|
||||
add 1,r8
|
||||
test_cc 1 0 1 0
|
||||
test_h_gr 0x80000000,r8
|
||||
set_cc 0x08 ; Set mask opposite of expected
|
||||
add r8,r8 ; test zero, carry and overflow bits
|
||||
test_cc 0 1 1 1;
|
||||
test_h_gr 0,r8
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
# fr30 testcase for add $Rj,$Ri
|
||||
# cpu {}
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global add
|
||||
add:
|
||||
add ac,ac
|
||||
fail
|
||||
EXIT 0
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
# fr30 testcase for add2 $m4,$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global add
|
||||
add:
|
||||
mvi_h_gr 30,r8
|
||||
set_cc 0x0e ; Set mask opposite of expected
|
||||
add2 -16,r8 ; Max value of immediate field
|
||||
test_cc 0 0 0 1
|
||||
test_h_gr 14,r8
|
||||
|
||||
set_cc 0x0e ; Set mask opposite of expected
|
||||
add2 -3,r8 ; Mid value of immediate field
|
||||
test_cc 0 0 0 1
|
||||
test_h_gr 11,r8
|
||||
|
||||
set_cc 0x0e ; Set mask opposite of expected
|
||||
add2 -1,r8 ; Min value of immediate field
|
||||
test_cc 0 0 0 1
|
||||
test_h_gr 10,r8
|
||||
|
||||
set_cc 0x0a ; Set mask opposite of expected
|
||||
add2 -10,r8 ; Test zero and carry bits
|
||||
test_cc 0 1 0 1
|
||||
test_h_gr 0,r8
|
||||
|
||||
set_cc 0x07 ; Set mask opposite of expected
|
||||
add2 -16,r8 ; Test negative bit
|
||||
test_cc 1 0 0 0
|
||||
test_h_gr -16,r8
|
||||
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x0c ; Set mask opposite of expected
|
||||
add2 -1,r8 ; Test overflow bit
|
||||
test_cc 0 0 1 1
|
||||
test_h_gr 0x7fffffff,r8
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
# fr30 testcase for addc $Rj,$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global add
|
||||
add:
|
||||
mvi_h_gr 1,r7
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0e ; Make sure carry bit is off
|
||||
addc r7,r8
|
||||
test_cc 0 0 0 0
|
||||
test_h_gr 3,r8
|
||||
|
||||
mvi_h_gr 0x7fffffff,r7
|
||||
mvi_h_gr 1,r8
|
||||
set_cc 0x04 ; Make sure carry bit is off
|
||||
addc r7,r8
|
||||
test_cc 1 0 1 0
|
||||
test_h_gr 0x80000000,r8
|
||||
|
||||
set_cc 0x08 ; Make sure carry bit is off
|
||||
addc r8,r8
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr 0,r8
|
||||
|
||||
mvi_h_gr 1,r7
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0f ; Make sure carry bit is on
|
||||
addc r7,r8
|
||||
test_cc 0 0 0 0
|
||||
test_h_gr 4,r8
|
||||
|
||||
mvi_h_gr 0x7fffffff,r7
|
||||
mvi_h_gr 0,r8
|
||||
set_cc 0x05 ; Make sure carry bit is on
|
||||
addc r7,r8
|
||||
test_cc 1 0 1 0
|
||||
test_h_gr 0x80000000,r8
|
||||
|
||||
mvi_h_gr 0x7fffffff,r7
|
||||
set_cc 0x0b ; Make sure carry bit is on
|
||||
addc r7,r8
|
||||
test_cc 0 1 0 1;
|
||||
test_h_gr 0,r8
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
# fr30 testcase for addn $Rj,$Ri, addn $u4,$Rj
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global addn
|
||||
addn:
|
||||
; Test addn $Rj,$Ri
|
||||
mvi_h_gr 1,r7
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0f ; Set mask opposite of normal result
|
||||
addn r7,r8
|
||||
test_cc 1 1 1 1
|
||||
test_h_gr 3,r8
|
||||
|
||||
mvi_h_gr 0x7fffffff,r7
|
||||
mvi_h_gr 1,r8
|
||||
set_cc 0x05 ; Set mask opposite of normal result
|
||||
addn r7,r8
|
||||
test_cc 0 1 0 1
|
||||
test_h_gr 0x80000000,r8
|
||||
|
||||
set_cc 0x08 ; Set mask opposite of normal result
|
||||
addn r8,r8
|
||||
test_cc 1 0 0 0
|
||||
test_h_gr 0,r8
|
||||
|
||||
; Test addn $u4Ri
|
||||
mvi_h_gr 4,r8
|
||||
set_cc 0x0f ; Set mask opposite of normal result
|
||||
addn 0,r8
|
||||
test_cc 1 1 1 1
|
||||
test_h_gr 4,r8
|
||||
set_cc 0x0f ; Set mask opposite of normal result
|
||||
addn 1,r8
|
||||
test_cc 1 1 1 1
|
||||
test_h_gr 5,r8
|
||||
set_cc 0x0f ; Set mask opposite of normal result
|
||||
addn 15,r8
|
||||
test_cc 1 1 1 1
|
||||
test_h_gr 20,r8
|
||||
mvi_h_gr 0x7fffffff,r8 ; test neg and overflow bits
|
||||
set_cc 0x05 ; Set mask opposite of normal result
|
||||
addn 1,r8
|
||||
test_cc 0 1 0 1
|
||||
test_h_gr 0x80000000,r8
|
||||
set_cc 0x08 ; Set mask opposite of normal result
|
||||
addn r8,r8 ; test zero, carry and overflow bits
|
||||
test_cc 1 0 0 0;
|
||||
test_h_gr 0,r8
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
# fr30 testcase for addn2 $m4,$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global add
|
||||
add:
|
||||
mvi_h_gr 30,r8
|
||||
set_cc 0x0e ; Set mask opposite of normal result
|
||||
addn2 -16,r8 ; Max value of immediate field
|
||||
test_cc 1 1 1 0
|
||||
test_h_gr 14,r8
|
||||
|
||||
set_cc 0x0e ; Set mask opposite of normal result
|
||||
addn2 -3,r8 ; Mid value of immediate field
|
||||
test_cc 1 1 1 0
|
||||
test_h_gr 11,r8
|
||||
|
||||
set_cc 0x0e ; Set mask opposite of normal result
|
||||
addn2 -1,r8 ; Min value of immediate field
|
||||
test_cc 1 1 1 0
|
||||
test_h_gr 10,r8
|
||||
|
||||
set_cc 0x0a ; Set mask opposite of normal result
|
||||
addn2 -10,r8 ; Test zero and carry bits
|
||||
test_cc 1 0 1 0
|
||||
test_h_gr 0,r8
|
||||
|
||||
set_cc 0x07 ; Set mask opposite of normal result
|
||||
addn2 -16,r8 ; Test negative bit
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr -16,r8
|
||||
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x0c ; Set mask opposite of normal result
|
||||
addn2 -1,r8 ; Test overflow bit
|
||||
test_cc 1 1 0 0
|
||||
test_h_gr 0x7fffffff,r8
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
# FR30 simulator testsuite.
|
||||
|
||||
if [istarget fr30*-*-*] {
|
||||
# load support procs
|
||||
# load_lib cgen.exp
|
||||
|
||||
foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] {
|
||||
# If we're only testing specific files and this isn't one of them,
|
||||
# skip it.
|
||||
if ![runtest_file_p $runtests $src] {
|
||||
continue
|
||||
}
|
||||
|
||||
run_sim_test $src
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
# fr30 testcase for and $Rj,$Ri, and $Rj,@$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global and
|
||||
and:
|
||||
; Test and $Rj,$Ri
|
||||
mvi_h_gr 0xaaaaaaaa,r7
|
||||
mvi_h_gr 0x55555555,r8
|
||||
set_cc 0x0b ; Set mask opposite of expected
|
||||
and r7,r8
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr 0,r8
|
||||
|
||||
mvi_h_gr 0xffff0000,r8
|
||||
set_cc 0x04 ; Set mask opposite of expected
|
||||
and r7,r8
|
||||
test_cc 1 0 0 0
|
||||
test_h_gr 0xaaaa0000,r8
|
||||
|
||||
mvi_h_gr 0xffff,r8
|
||||
set_cc 0x0d ; Set mask opposite of expected
|
||||
and r7,r8
|
||||
test_cc 0 0 0 1
|
||||
test_h_gr 0xaaaa,r8
|
||||
|
||||
; Test and $Rj,@$Ri
|
||||
mvi_h_gr 0xaaaaaaaa,r7
|
||||
mvi_h_mem 0x55555555,sp
|
||||
set_cc 0x0b ; Set mask opposite of expected
|
||||
and r7,@sp
|
||||
test_cc 0 1 1 1
|
||||
test_h_mem 0,sp
|
||||
|
||||
mvi_h_mem 0xffff0000,sp
|
||||
set_cc 0x04 ; Set mask opposite of expected
|
||||
and r7,@sp
|
||||
test_cc 1 0 0 0
|
||||
test_h_mem 0xaaaa0000,sp
|
||||
|
||||
mvi_h_mem 0xffff,sp
|
||||
set_cc 0x0d ; Set mask opposite of expected
|
||||
and r7,@sp
|
||||
test_cc 0 0 0 1
|
||||
test_h_mem 0xaaaa,sp
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
# fr30 testcase for andb $Rj,@$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global andb
|
||||
andb:
|
||||
; Test andb $Rj,@$Ri
|
||||
mvi_h_gr 0xaaaaaaaa,r7
|
||||
mvi_h_mem 0x55555555,sp
|
||||
set_cc 0x0b ; Set mask opposite of expected
|
||||
andb r7,@sp
|
||||
test_cc 0 1 1 1
|
||||
test_h_mem 0x00555555,sp
|
||||
|
||||
mvi_h_mem 0xffffffff,sp
|
||||
set_cc 0x04 ; Set mask opposite of expected
|
||||
andb r7,@sp
|
||||
test_cc 1 0 0 0
|
||||
test_h_mem 0xaaffffff,sp
|
||||
|
||||
mvi_h_mem 0x0fffffff,sp
|
||||
set_cc 0x0d ; Set mask opposite of expected
|
||||
andb r7,@sp
|
||||
test_cc 0 0 0 1
|
||||
test_h_mem 0x0affffff,sp
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
# fr30 testcase for andh $Rj,@$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global andh
|
||||
andh:
|
||||
; Test andh $Rj,@$Ri
|
||||
mvi_h_gr 0xaaaaaaaa,r7
|
||||
mvi_h_mem 0x55555555,sp
|
||||
set_cc 0x0b ; Set mask opposite of expected
|
||||
andh r7,@sp
|
||||
test_cc 0 1 1 1
|
||||
test_h_mem 0x00005555,sp
|
||||
|
||||
mvi_h_mem 0xffffffff,sp
|
||||
set_cc 0x04 ; Set mask opposite of expected
|
||||
andh r7,@sp
|
||||
test_cc 1 0 0 0
|
||||
test_h_mem 0xaaaaffff,sp
|
||||
|
||||
mvi_h_mem 0x00ffffff,sp
|
||||
set_cc 0x0d ; Set mask opposite of expected
|
||||
andh r7,@sp
|
||||
test_cc 0 0 0 1
|
||||
test_h_mem 0x00aaffff,sp
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
# fr30 testcase for asr $Rj,$Ri, asr $u4,$Rj
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global asr
|
||||
asr:
|
||||
; Test asr $Rj,$Ri
|
||||
mvi_h_gr 0xdeadbee0,r7 ; Shift by 0
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x05 ; Set mask opposite of expected
|
||||
asr r7,r8
|
||||
test_cc 1 0 0 0
|
||||
test_h_gr 0x80000000,r8
|
||||
|
||||
mvi_h_gr 0xdeadbee1,r7 ; Shift by 1
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x07 ; Set mask opposite of expected
|
||||
asr r7,r8
|
||||
test_cc 1 0 1 0
|
||||
test_h_gr 0xc0000000,r8
|
||||
|
||||
mvi_h_gr 0xdeadbeff,r7 ; Shift by 31
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x07 ; Set mask opposite of expected
|
||||
asr r7,r8
|
||||
test_cc 1 0 1 0
|
||||
test_h_gr -1,r8
|
||||
|
||||
mvi_h_gr 0xdeadbeff,r7 ; clear register
|
||||
mvi_h_gr 0x40000000,r8
|
||||
set_cc 0x0a ; Set mask opposite of expected
|
||||
asr r7,r8
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr 0x00000000,r8
|
||||
|
||||
; Test asr $u4Ri
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x05 ; Set mask opposite of expected
|
||||
asr 0,r8
|
||||
test_cc 1 0 0 0
|
||||
test_h_gr 0x80000000,r8
|
||||
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x07 ; Set mask opposite of expected
|
||||
asr 1,r8
|
||||
test_cc 1 0 1 0
|
||||
test_h_gr 0xc0000000,r8
|
||||
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x07 ; Set mask opposite of expected
|
||||
asr 15,r8
|
||||
test_cc 1 0 1 0
|
||||
test_h_gr 0xffff0000,r8
|
||||
|
||||
mvi_h_gr 0x00004000,r8
|
||||
set_cc 0x0a ; Set mask opposite of expected
|
||||
asr 15,r8
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr 0x00000000,r8
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
# fr30 testcase for asr2 $u4,$Rj
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global asr2
|
||||
asr2:
|
||||
; Test asr2 $u4Ri
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x05 ; Set mask opposite of expected
|
||||
asr2 0,r8
|
||||
test_cc 1 0 0 0
|
||||
test_h_gr 0xffff8000,r8
|
||||
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x07 ; Set mask opposite of expected
|
||||
asr2 1,r8
|
||||
test_cc 1 0 1 0
|
||||
test_h_gr 0xffffc000,r8
|
||||
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x07 ; Set mask opposite of expected
|
||||
asr2 15,r8
|
||||
test_cc 1 0 1 0
|
||||
test_h_gr -1,r8
|
||||
|
||||
mvi_h_gr 0x40000000,r8
|
||||
set_cc 0x0a ; Set mask opposite of expected
|
||||
asr2 15,r8
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr 0x00000000,r8
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
# fr30 testcase for bandh $Rj,@$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global bandh
|
||||
bandh:
|
||||
; Test bandh $Rj,@$Ri
|
||||
mvi_h_mem 0x55555555,sp
|
||||
set_cc 0x0f ; Condition codes should not change
|
||||
bandh 0x0a,@sp
|
||||
test_cc 1 1 1 1
|
||||
test_h_mem 0x05555555,sp
|
||||
|
||||
mvi_h_mem 0xffffffff,sp
|
||||
set_cc 0x04 ; Condition codes should not change
|
||||
bandh 0x0a,@sp
|
||||
test_cc 0 1 0 0
|
||||
test_h_mem 0xafffffff,sp
|
||||
|
||||
mvi_h_mem 0xe5ffffff,sp
|
||||
set_cc 0x0a ; Condition codes should not change
|
||||
bandh 0x07,@sp
|
||||
test_cc 1 0 1 0
|
||||
test_h_mem 0x65ffffff,sp
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
# fr30 testcase for bandl $Rj,@$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global bandl
|
||||
bandl:
|
||||
; Test bandl $Rj,@$Ri
|
||||
mvi_h_mem 0x55555555,sp
|
||||
set_cc 0x0f ; Condition codes should not change
|
||||
bandl 0x0a,@sp
|
||||
test_cc 1 1 1 1
|
||||
test_h_mem 0x50555555,sp
|
||||
|
||||
mvi_h_mem 0xffffffff,sp
|
||||
set_cc 0x04 ; Condition codes should not change
|
||||
bandl 0x0a,@sp
|
||||
test_cc 0 1 0 0
|
||||
test_h_mem 0xfaffffff,sp
|
||||
|
||||
mvi_h_mem 0x5effffff,sp
|
||||
set_cc 0x0a ; Condition codes should not change
|
||||
bandl 0x07,@sp
|
||||
test_cc 1 0 1 0
|
||||
test_h_mem 0x56ffffff,sp
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
# fr30 testcase for beorh $Rj,@$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global beorh
|
||||
beorh:
|
||||
; Test beorh $Rj,@$Ri
|
||||
mvi_h_mem 0x55555555,sp
|
||||
set_cc 0x0f ; Condition codes should not change
|
||||
beorh 0x0a,@sp
|
||||
test_cc 1 1 1 1
|
||||
test_h_mem 0xf5555555,sp
|
||||
|
||||
mvi_h_mem 0x0fffffff,sp
|
||||
set_cc 0x04 ; Condition codes should not change
|
||||
beorh 0x00,@sp
|
||||
test_cc 0 1 0 0
|
||||
test_h_mem 0x0fffffff,sp
|
||||
|
||||
mvi_h_mem 0xffffffff,sp
|
||||
set_cc 0x0a ; Condition codes should not change
|
||||
beorh 0x0f,@sp
|
||||
test_cc 1 0 1 0
|
||||
test_h_mem 0x0fffffff,sp
|
||||
|
||||
mvi_h_mem 0x9eadbeef,sp
|
||||
set_cc 0x09 ; Condition codes should not change
|
||||
beorh 0x04,@sp
|
||||
test_cc 1 0 0 1
|
||||
test_h_mem 0xdeadbeef,sp
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
# fr30 testcase for beorl $Rj,@$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global beorl
|
||||
beorl:
|
||||
; Test beorl $Rj,@$Ri
|
||||
mvi_h_mem 0x55555555,sp
|
||||
set_cc 0x0f ; Condition codes should not change
|
||||
beorl 0x0a,@sp
|
||||
test_cc 1 1 1 1
|
||||
test_h_mem 0x5f555555,sp
|
||||
|
||||
mvi_h_mem 0xf0ffffff,sp
|
||||
set_cc 0x04 ; Condition codes should not change
|
||||
beorl 0x00,@sp
|
||||
test_cc 0 1 0 0
|
||||
test_h_mem 0xf0ffffff,sp
|
||||
|
||||
mvi_h_mem 0xffffffff,sp
|
||||
set_cc 0x0a ; Condition codes should not change
|
||||
beorl 0x0f,@sp
|
||||
test_cc 1 0 1 0
|
||||
test_h_mem 0xf0ffffff,sp
|
||||
|
||||
mvi_h_mem 0xddadbeef,sp
|
||||
set_cc 0x09 ; Condition codes should not change
|
||||
beorl 0x03,@sp
|
||||
test_cc 1 0 0 1
|
||||
test_h_mem 0xdeadbeef,sp
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
# fr30 testcase for borh $Rj,@$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global borh
|
||||
borh:
|
||||
; Test borh $Rj,@$Ri
|
||||
mvi_h_mem 0x55555555,sp
|
||||
set_cc 0x0f ; Condition codes should not change
|
||||
borh 0x0a,@sp
|
||||
test_cc 1 1 1 1
|
||||
test_h_mem 0xf5555555,sp
|
||||
|
||||
mvi_h_mem 0x0fffffff,sp
|
||||
set_cc 0x04 ; Condition codes should not change
|
||||
borh 0x00,@sp
|
||||
test_cc 0 1 0 0
|
||||
test_h_mem 0x0fffffff,sp
|
||||
|
||||
mvi_h_mem 0xceadbeef,sp
|
||||
set_cc 0x09 ; Condition codes should not change
|
||||
borh 0x01,@sp
|
||||
test_cc 1 0 0 1
|
||||
test_h_mem 0xdeadbeef,sp
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
# fr30 testcase for borl $Rj,@$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global borl
|
||||
borl:
|
||||
; Test borl $Rj,@$Ri
|
||||
mvi_h_mem 0x55555555,sp
|
||||
set_cc 0x0f ; Condition codes should not change
|
||||
borl 0x0a,@sp
|
||||
test_cc 1 1 1 1
|
||||
test_h_mem 0x5f555555,sp
|
||||
|
||||
mvi_h_mem 0xf0ffffff,sp
|
||||
set_cc 0x04 ; Condition codes should not change
|
||||
borl 0x00,@sp
|
||||
test_cc 0 1 0 0
|
||||
test_h_mem 0xf0ffffff,sp
|
||||
|
||||
mvi_h_mem 0xdcadbeef,sp
|
||||
set_cc 0x09 ; Condition codes should not change
|
||||
borl 0x02,@sp
|
||||
test_cc 1 0 0 1
|
||||
test_h_mem 0xdeadbeef,sp
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
# fr30 testcase for btsth $Rj,@$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global btsth
|
||||
btsth:
|
||||
; Test btsth $Rj,@$Ri
|
||||
mvi_h_mem 0x55555555,sp
|
||||
set_cc 0x0b ; Set mask opposite of expected
|
||||
btsth 0x0a,@sp
|
||||
test_cc 0 1 1 1
|
||||
test_h_mem 0x55555555,sp
|
||||
|
||||
mvi_h_mem 0xffffffff,sp
|
||||
set_cc 0x04 ; Set mask opposite of expected
|
||||
btsth 0x0a,@sp
|
||||
test_cc 1 0 0 0
|
||||
test_h_mem 0xffffffff,sp
|
||||
|
||||
mvi_h_mem 0xe5ffffff,sp
|
||||
set_cc 0x0e ; Set mask opposite of expected
|
||||
btsth 0x07,@sp
|
||||
test_cc 0 0 1 0
|
||||
test_h_mem 0xe5ffffff,sp
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
# fr30 testcase for btstl $Rj,@$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global btstl
|
||||
btstl:
|
||||
; Test btstl $Rj,@$Ri
|
||||
mvi_h_mem 0x55555555,sp
|
||||
set_cc 0x0b ; Set mask opposite of expected
|
||||
btstl 0x0a,@sp
|
||||
test_cc 0 1 1 1
|
||||
test_h_mem 0x55555555,sp
|
||||
|
||||
mvi_h_mem 0xffffffff,sp
|
||||
set_cc 0x0c ; Set mask opposite of expected
|
||||
btstl 0x0a,@sp
|
||||
test_cc 0 0 0 0
|
||||
test_h_mem 0xffffffff,sp
|
||||
|
||||
mvi_h_mem 0x5effffff,sp
|
||||
set_cc 0x0e ; Set mask opposite of expected
|
||||
btstl 0x07,@sp
|
||||
test_cc 0 0 1 0
|
||||
test_h_mem 0x5effffff,sp
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
# fr30 testcase for cmp $Rj,$Ri, cmp $u4,$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global cmp
|
||||
cmp:
|
||||
; Test cmp $Rj,$Ri
|
||||
mvi_h_gr 1,r7
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0f ; Set mask opposite of expected
|
||||
cmp r7,r8
|
||||
test_cc 0 0 0 0
|
||||
|
||||
mvi_h_gr 1,r7
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x0d ; Set mask opposite of expected
|
||||
cmp r7,r8
|
||||
test_cc 0 0 1 0
|
||||
|
||||
set_cc 0x0b ; Set mask opposite of expected
|
||||
cmp r8,r8
|
||||
test_cc 0 1 0 0
|
||||
|
||||
mvi_h_gr 0,r8
|
||||
set_cc 0x06 ; Set mask opposite of expected
|
||||
cmp r7,r8
|
||||
test_cc 1 0 0 1
|
||||
|
||||
; Test cmp $u4,$Ri
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0f ; Set mask opposite of expected
|
||||
cmp 1,r8
|
||||
test_cc 0 0 0 0
|
||||
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x0d ; Set mask opposite of expected
|
||||
cmp 1,r8
|
||||
test_cc 0 0 1 0
|
||||
|
||||
mvi_h_gr 0,r8
|
||||
set_cc 0x0b ; Set mask opposite of expected
|
||||
cmp 0,r8
|
||||
test_cc 0 1 0 0
|
||||
|
||||
set_cc 0x06 ; Set mask opposite of expected
|
||||
cmp 15,r8
|
||||
test_cc 1 0 0 1
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
# fr30 testcase for cmp2 $u4,$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global cmp2
|
||||
cmp2:
|
||||
; Test cmp2 $u4,$Ri
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0e ; Set mask opposite of expected
|
||||
cmp2 -1,r8
|
||||
test_cc 0 0 0 1
|
||||
|
||||
mvi_h_gr 0x7ffffffe,r8
|
||||
set_cc 0x04 ; Set mask opposite of expected
|
||||
cmp2 -2,r8
|
||||
test_cc 1 0 1 1
|
||||
|
||||
mvi_h_gr -16,r8
|
||||
set_cc 0x0b ; Set mask opposite of expected
|
||||
cmp2 -16,r8
|
||||
test_cc 0 1 0 0
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
# fr30 testcase for eor $Rj,$Ri, eor $Rj,@$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global eor
|
||||
eor:
|
||||
; Test eor $Rj,$Ri
|
||||
mvi_h_gr 0xaaaaaaaa,r7
|
||||
mvi_h_gr 0x55555555,r8
|
||||
set_cc 0x07 ; Set mask opposite of expected
|
||||
eor r7,r8
|
||||
test_cc 1 0 1 1
|
||||
test_h_gr 0xffffffff,r8
|
||||
|
||||
mvi_h_gr 0x00000000,r7
|
||||
mvi_h_gr 0x00000000,r8
|
||||
set_cc 0x08 ; Set mask opposite of expected
|
||||
eor r7,r8
|
||||
test_cc 0 1 0 0
|
||||
test_h_gr 0x00000000,r8
|
||||
|
||||
mvi_h_gr 0xaaaaaaaa,r7
|
||||
mvi_h_gr 0xaaaaaaaa,r8
|
||||
set_cc 0x0b ; Set mask opposite of expected
|
||||
eor r7,r8
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr 0x00000000,r8
|
||||
|
||||
mvi_h_gr 0xdead0000,r7
|
||||
mvi_h_gr 0x0000beef,r8
|
||||
set_cc 0x05 ; Set mask opposite of expected
|
||||
eor r7,r8
|
||||
test_cc 1 0 0 1
|
||||
test_h_gr 0xdeadbeef,r8
|
||||
|
||||
; Test eor $Rj,@$Ri
|
||||
mvi_h_gr 0xaaaaaaaa,r7
|
||||
mvi_h_mem 0x55555555,sp
|
||||
set_cc 0x07 ; Set mask opposite of expected
|
||||
eor r7,@sp
|
||||
test_cc 1 0 1 1
|
||||
test_h_mem 0xffffffff,sp
|
||||
|
||||
mvi_h_gr 0x00000000,r7
|
||||
mvi_h_mem 0x00000000,sp
|
||||
set_cc 0x08 ; Set mask opposite of expected
|
||||
eor r7,@sp
|
||||
test_cc 0 1 0 0
|
||||
test_h_mem 0x00000000,sp
|
||||
|
||||
mvi_h_gr 0xaaaaaaaa,r7
|
||||
mvi_h_mem 0xaaaaaaaa,sp
|
||||
set_cc 0x0b ; Set mask opposite of expected
|
||||
eor r7,@sp
|
||||
test_cc 0 1 1 1
|
||||
test_h_mem 0x00000000,sp
|
||||
|
||||
mvi_h_gr 0xdead0000,r7
|
||||
mvi_h_mem 0x0000beef,sp
|
||||
set_cc 0x05 ; Set mask opposite of expected
|
||||
eor r7,@sp
|
||||
test_cc 1 0 0 1
|
||||
test_h_mem 0xdeadbeef,sp
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
# fr30 testcase for eorb $Rj,$Ri, eorb $Rj,@$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global eorb
|
||||
eorb:
|
||||
; Test eorb $Rj,@$Ri
|
||||
mvi_h_gr 0xaaaaaaaa,r7
|
||||
mvi_h_mem 0x55555555,sp
|
||||
set_cc 0x07 ; Set mask opposite of expected
|
||||
eorb r7,@sp
|
||||
test_cc 1 0 1 1
|
||||
test_h_mem 0xff555555,sp
|
||||
|
||||
mvi_h_gr 0xaaaaaa00,r7
|
||||
mvi_h_mem 0x00555555,sp
|
||||
set_cc 0x08 ; Set mask opposite of expected
|
||||
eorb r7,@sp
|
||||
test_cc 0 1 0 0
|
||||
test_h_mem 0x00555555,sp
|
||||
|
||||
mvi_h_gr 0xaaaaaa55,r7
|
||||
mvi_h_mem 0x55aaaaaa,sp
|
||||
set_cc 0x0b ; Set mask opposite of expected
|
||||
eorb r7,@sp
|
||||
test_cc 0 1 1 1
|
||||
test_h_mem 0x00aaaaaa,sp
|
||||
|
||||
mvi_h_gr 0x000000d0,r7
|
||||
mvi_h_mem 0x0eadbeef,sp
|
||||
set_cc 0x05 ; Set mask opposite of expected
|
||||
eorb r7,@sp
|
||||
test_cc 1 0 0 1
|
||||
test_h_mem 0xdeadbeef,sp
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
# fr30 testcase for eorh $Rj,$Ri, eorh $Rj,@$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global eorh
|
||||
eorh:
|
||||
; Test eorh $Rj,@$Ri
|
||||
mvi_h_gr 0xaaaaaaaa,r7
|
||||
mvi_h_mem 0x55555555,sp
|
||||
set_cc 0x07 ; Set mask opposite of expected
|
||||
eorh r7,@sp
|
||||
test_cc 1 0 1 1
|
||||
test_h_mem 0xffff5555,sp
|
||||
|
||||
mvi_h_gr 0xaaaa0000,r7
|
||||
mvi_h_mem 0x00005555,sp
|
||||
set_cc 0x08 ; Set mask opposite of expected
|
||||
eorh r7,@sp
|
||||
test_cc 0 1 0 0
|
||||
test_h_mem 0x00005555,sp
|
||||
|
||||
mvi_h_gr 0xaaaa5555,r7
|
||||
mvi_h_mem 0x5555aaaa,sp
|
||||
set_cc 0x0b ; Set mask opposite of expected
|
||||
eorh r7,@sp
|
||||
test_cc 0 1 1 1
|
||||
test_h_mem 0x0000aaaa,sp
|
||||
|
||||
mvi_h_gr 0x0000de00,r7
|
||||
mvi_h_mem 0x00adbeef,sp
|
||||
set_cc 0x05 ; Set mask opposite of expected
|
||||
eorh r7,@sp
|
||||
test_cc 1 0 0 1
|
||||
test_h_mem 0xdeadbeef,sp
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
# output: Hello world!
|
||||
# mach(): fr30
|
||||
|
||||
.global _start
|
||||
_start:
|
||||
|
||||
; write (hello world)
|
||||
ldi32 #14,r6
|
||||
ldi32 #hello,r5
|
||||
ldi32 #1,r4
|
||||
ldi32 #5,r0
|
||||
int #10
|
||||
; exit (0)
|
||||
ldi32 #0,r4
|
||||
ldi32 #1,r0
|
||||
int #10
|
||||
|
||||
length: .long 14
|
||||
hello: .ascii "Hello world!\r\n"
|
||||
|
|
@ -0,0 +1,158 @@
|
|||
# fr30 testcase for
|
||||
# mach(): fr30
|
||||
# ld $Rj,$Ri
|
||||
# ld @($R13,$Rj),$Ri
|
||||
# ld @($R14,$disp10),$Ri
|
||||
# ld @($R15,$udisp6),$Ri
|
||||
# ld @$R15+,$Ri
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global ld
|
||||
ld:
|
||||
; Test ld $Rj,$Ri
|
||||
mvi_h_mem #0x00000000,sp
|
||||
set_cc 0x0f ; condition codes should not change
|
||||
ld @sp,r7
|
||||
test_cc 1 1 1 1
|
||||
test_h_gr 0,r7
|
||||
|
||||
mvi_h_mem #0x00000001,sp
|
||||
set_cc 0x07 ; condition codes should not change
|
||||
ld @sp,r7
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr 1,r7
|
||||
|
||||
mvi_h_mem #0x7fffffff,sp
|
||||
set_cc 0x0b ; condition codes should not change
|
||||
ld @sp,r7
|
||||
test_cc 1 0 1 1
|
||||
test_h_gr 0x7fffffff,r7
|
||||
|
||||
mvi_h_mem #0x80000000,sp
|
||||
set_cc 0x0d ; condition codes should not change
|
||||
ld @sp,r7
|
||||
test_cc 1 1 0 1
|
||||
test_h_gr 0x80000000,r7
|
||||
|
||||
mvi_h_mem #0xffffffff,sp
|
||||
set_cc 0x0e ; condition codes should not change
|
||||
ld @sp,r7
|
||||
test_cc 1 1 1 0
|
||||
test_h_gr -1,r7
|
||||
|
||||
; Test ld @($R13,$Rj),$Ri
|
||||
mvr_h_gr sp,r13
|
||||
inci_h_gr -8,r13
|
||||
mvi_h_gr 8,r8
|
||||
|
||||
mvi_h_mem #0x00000000,sp
|
||||
set_cc 0x0f ; condition codes should not change
|
||||
ld @(r13,r8),r7
|
||||
test_cc 1 1 1 1
|
||||
test_h_gr 0,r7
|
||||
|
||||
mvi_h_mem #0x00000001,sp
|
||||
set_cc 0x07 ; condition codes should not change
|
||||
ld @(r13,r8),r7
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr 1,r7
|
||||
|
||||
mvi_h_mem #0x7fffffff,sp
|
||||
set_cc 0x0b ; condition codes should not change
|
||||
ld @(r13,r8),r7
|
||||
test_cc 1 0 1 1
|
||||
test_h_gr 0x7fffffff,r7
|
||||
|
||||
mvi_h_mem #0x80000000,sp
|
||||
set_cc 0x0d ; condition codes should not change
|
||||
ld @(r13,r8),r7
|
||||
test_cc 1 1 0 1
|
||||
test_h_gr 0x80000000,r7
|
||||
|
||||
mvi_h_mem #0xffffffff,sp
|
||||
set_cc 0x0e ; condition codes should not change
|
||||
ld @(r13,r8),r7
|
||||
test_cc 1 1 1 0
|
||||
test_h_gr -1,r7
|
||||
|
||||
; Test ld @($R14,$disp10),$Ri
|
||||
mvi_h_mem #0xdeadbeef,sp
|
||||
mvr_h_gr sp,r14
|
||||
mvi_h_gr -0x1fc,r8
|
||||
add_h_gr r8,r14
|
||||
|
||||
set_cc 0x0f ; condition codes should not change
|
||||
ld @(r14,0x1fc),r7
|
||||
test_cc 1 1 1 1
|
||||
test_h_gr 0xdeadbeef,r7
|
||||
|
||||
inci_h_gr 0xfc,r14
|
||||
set_cc 0x07 ; condition codes should not change
|
||||
ld @(r14,0x100),r7
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr 0xdeadbeef,r7
|
||||
|
||||
inci_h_gr 0x100,r14
|
||||
set_cc 0x0b ; condition codes should not change
|
||||
ld @(r14,0x0),r7
|
||||
test_cc 1 0 1 1
|
||||
test_h_gr 0xdeadbeef,r7
|
||||
|
||||
inci_h_gr 0x100,r14
|
||||
set_cc 0x0d ; condition codes should not change
|
||||
ld @(r14,-0x100),r7
|
||||
test_cc 1 1 0 1
|
||||
test_h_gr 0xdeadbeef,r7
|
||||
|
||||
inci_h_gr 0x100,r14
|
||||
set_cc 0x0e ; condition codes should not change
|
||||
ld @(r14,-0x200),r7
|
||||
test_cc 1 1 1 0
|
||||
test_h_gr 0xdeadbeef,r7
|
||||
|
||||
; Test ld @($R15,$udisp6),$Ri
|
||||
mvi_h_mem #0xdeadbeef,sp
|
||||
mvr_h_gr sp,r14
|
||||
mvi_h_gr -0x3c,r8
|
||||
add_h_gr r8,r14
|
||||
|
||||
set_cc 0x0f ; condition codes should not change
|
||||
ld @(r14,0x3c),r7
|
||||
test_cc 1 1 1 1
|
||||
test_h_gr 0xdeadbeef,r7
|
||||
|
||||
inci_h_gr 0x1c,r14
|
||||
set_cc 0x07 ; condition codes should not change
|
||||
ld @(r14,0x20),r7
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr 0xdeadbeef,r7
|
||||
|
||||
inci_h_gr 0x20,r14
|
||||
set_cc 0x0b ; condition codes should not change
|
||||
ld @(r14,0x0),r7
|
||||
test_cc 1 0 1 1
|
||||
test_h_gr 0xdeadbeef,r7
|
||||
|
||||
; Test ld @$R15+,$Ri
|
||||
mvr_h_gr sp,r8 ; save original stack pointer
|
||||
mvr_h_gr r8,r9
|
||||
inci_h_gr 4,r9 ; original stack pointer + 4
|
||||
mvi_h_mem #0xdeadbeef,sp ; prime memory
|
||||
|
||||
set_cc 0x0f ; condition codes should not change
|
||||
ld @r15+,r7
|
||||
test_cc 1 1 1 1
|
||||
test_h_gr 0xdeadbeef,r7
|
||||
testr_h_gr sp,r9 ; should have been incremented
|
||||
|
||||
mvr_h_gr r8,sp ; save original stack pointer
|
||||
ld @r15+,sp
|
||||
test_cc 1 1 1 1
|
||||
test_h_gr 0xdeadbeef,sp
|
||||
testr_h_gr sp,r8 ; should not have been incremented
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
# fr30 testcase for ldi20 $i20,$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global ldi20
|
||||
ldi20:
|
||||
; Test ldi20 $i20,$Ri
|
||||
set_cc 0x0f ; condition codes should not change
|
||||
ldi20 #0x00000000,r7
|
||||
test_cc 1 1 1 1
|
||||
test_h_gr 0,r7
|
||||
|
||||
set_cc 0x07 ; condition codes should not change
|
||||
ldi:20 1,r7
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr 1,r7
|
||||
|
||||
set_cc 0x0b ; condition codes should not change
|
||||
ldi20 0x7ffff,r7
|
||||
test_cc 1 0 1 1
|
||||
test_h_gr 0x0007ffff,r7
|
||||
|
||||
set_cc 0x0d ; condition codes should not change
|
||||
ldi:20 0x80000,r7
|
||||
test_cc 1 1 0 1
|
||||
test_h_gr 0x00080000,r7
|
||||
|
||||
set_cc 0x0e ; condition codes should not change
|
||||
ldi20 0xfffff,r7
|
||||
test_cc 1 1 1 0
|
||||
test_h_gr 0x000fffff,r7
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
# fr30 testcase for ldi32 $i32,$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global ldi32
|
||||
ldi32:
|
||||
; Test ldi32 $i32,$Ri
|
||||
set_cc 0x0f ; condition codes should not change
|
||||
ldi32 #0x00000000,r7
|
||||
test_cc 1 1 1 1
|
||||
test_h_gr 0,r7
|
||||
|
||||
set_cc 0x07 ; condition codes should not change
|
||||
ldi:32 1,r7
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr 1,r7
|
||||
|
||||
set_cc 0x0b ; condition codes should not change
|
||||
ldi32 0x7fffffff,r7
|
||||
test_cc 1 0 1 1
|
||||
test_h_gr 0x7fffffff,r7
|
||||
|
||||
set_cc 0x0d ; condition codes should not change
|
||||
ldi:32 0x80000000,r7
|
||||
test_cc 1 1 0 1
|
||||
test_h_gr 0x80000000,r7
|
||||
|
||||
set_cc 0x0e ; condition codes should not change
|
||||
ldi32 0xffffffff,r7
|
||||
test_cc 1 1 1 0
|
||||
test_h_gr -1,r7
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
# fr30 testcase for ldi8 $i8,$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global ldi8
|
||||
ldi8:
|
||||
; Test ldi8 $i8,$Ri
|
||||
set_cc 0x0f ; condition codes should not change
|
||||
ldi8 #0x00000000,r7
|
||||
test_cc 1 1 1 1
|
||||
test_h_gr 0,r7
|
||||
|
||||
set_cc 0x07 ; condition codes should not change
|
||||
ldi:20 1,r7
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr 1,r7
|
||||
|
||||
set_cc 0x0b ; condition codes should not change
|
||||
ldi8 0x7f,r7
|
||||
test_cc 1 0 1 1
|
||||
test_h_gr 0x0000007f,r7
|
||||
|
||||
set_cc 0x0d ; condition codes should not change
|
||||
ldi:20 0x80,r7
|
||||
test_cc 1 1 0 1
|
||||
test_h_gr 0x00000080,r7
|
||||
|
||||
set_cc 0x0e ; condition codes should not change
|
||||
ldi8 0xff,r7
|
||||
test_cc 1 1 1 0
|
||||
test_h_gr 0x000000ff,r7
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,115 @@
|
|||
# fr30 testcase for
|
||||
# mach(): fr30
|
||||
# ldub $Rj,$Ri
|
||||
# ldub @($R13,$Rj),$Ri
|
||||
# ldub @($R14,$disp8),$Ri
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global ldub
|
||||
ldub:
|
||||
; Test ldub $Rj,$Ri
|
||||
mvi_h_mem #0x00adbeef,sp
|
||||
set_cc 0x0f ; condition codes should not change
|
||||
ldub @sp,r7
|
||||
test_cc 1 1 1 1
|
||||
test_h_gr 0,r7
|
||||
|
||||
mvi_h_mem #0x01adbeef,sp
|
||||
set_cc 0x07 ; condition codes should not change
|
||||
ldub @sp,r7
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr 1,r7
|
||||
|
||||
mvi_h_mem #0x7fadbeef,sp
|
||||
set_cc 0x0b ; condition codes should not change
|
||||
ldub @sp,r7
|
||||
test_cc 1 0 1 1
|
||||
test_h_gr 0x7f,r7
|
||||
|
||||
mvi_h_mem #0x80adbeef,sp
|
||||
set_cc 0x0d ; condition codes should not change
|
||||
ldub @sp,r7
|
||||
test_cc 1 1 0 1
|
||||
test_h_gr 0x80,r7
|
||||
|
||||
mvi_h_mem #0xffadbeef,sp
|
||||
set_cc 0x0e ; condition codes should not change
|
||||
ldub @sp,r7
|
||||
test_cc 1 1 1 0
|
||||
test_h_gr 0xff,r7
|
||||
|
||||
; Test ldub @($R13,$Rj),$Ri
|
||||
mvr_h_gr sp,r13
|
||||
inci_h_gr -8,r13
|
||||
mvi_h_gr 8,r8
|
||||
|
||||
mvi_h_mem #0x00adbeef,sp
|
||||
set_cc 0x0f ; condition codes should not change
|
||||
ldub @(r13,r8),r7
|
||||
test_cc 1 1 1 1
|
||||
test_h_gr 0,r7
|
||||
|
||||
mvi_h_mem #0x01adbeef,sp
|
||||
set_cc 0x07 ; condition codes should not change
|
||||
ldub @(r13,r8),r7
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr 1,r7
|
||||
|
||||
mvi_h_mem #0x7fadbeef,sp
|
||||
set_cc 0x0b ; condition codes should not change
|
||||
ldub @(r13,r8),r7
|
||||
test_cc 1 0 1 1
|
||||
test_h_gr 0x7f,r7
|
||||
|
||||
mvi_h_mem #0x80adbeef,sp
|
||||
set_cc 0x0d ; condition codes should not change
|
||||
ldub @(r13,r8),r7
|
||||
test_cc 1 1 0 1
|
||||
test_h_gr 0x80,r7
|
||||
|
||||
mvi_h_mem #0xffadbeef,sp
|
||||
set_cc 0x0e ; condition codes should not change
|
||||
ldub @(r13,r8),r7
|
||||
test_cc 1 1 1 0
|
||||
test_h_gr 0xff,r7
|
||||
|
||||
; Test ldub @($R14,$disp8),$Ri
|
||||
mvi_h_mem #0xdeadbeef,sp
|
||||
mvr_h_gr sp,r14
|
||||
mvi_h_gr -0x7f,r8
|
||||
add_h_gr r8,r14
|
||||
|
||||
set_cc 0x0f ; condition codes should not change
|
||||
lduh @(r14,0x7f),r7
|
||||
test_cc 1 1 1 1
|
||||
test_h_gr 0xde,r7
|
||||
|
||||
inci_h_gr 0x3e,r14
|
||||
set_cc 0x07 ; condition codes should not change
|
||||
lduh @(r14,0x40),r7
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr 0xde,r7
|
||||
|
||||
inci_h_gr 0x40,r14
|
||||
set_cc 0x0b ; condition codes should not change
|
||||
lduh @(r14,0x0),r7
|
||||
test_cc 1 0 1 1
|
||||
test_h_gr 0xde,r7
|
||||
|
||||
inci_h_gr 0x40,r14
|
||||
set_cc 0x0d ; condition codes should not change
|
||||
lduh @(r14,-0x40),r7
|
||||
test_cc 1 1 0 1
|
||||
test_h_gr 0xde,r7
|
||||
|
||||
inci_h_gr 0x40,r14
|
||||
set_cc 0x0e ; condition codes should not change
|
||||
lduh @(r14,-0x80),r7
|
||||
test_cc 1 1 1 0
|
||||
test_h_gr 0xde,r7
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,115 @@
|
|||
# fr30 testcase for
|
||||
# mach(): fr30
|
||||
# lduh $Rj,$Ri
|
||||
# lduh @($R13,$Rj),$Ri
|
||||
# lduh @($R14,$disp9),$Ri
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global lduh
|
||||
lduh:
|
||||
; Test lduh $Rj,$Ri
|
||||
mvi_h_mem #0x0000beef,sp
|
||||
set_cc 0x0f ; condition codes should not change
|
||||
lduh @sp,r7
|
||||
test_cc 1 1 1 1
|
||||
test_h_gr 0,r7
|
||||
|
||||
mvi_h_mem #0x0001beef,sp
|
||||
set_cc 0x07 ; condition codes should not change
|
||||
lduh @sp,r7
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr 1,r7
|
||||
|
||||
mvi_h_mem #0x7fffbeef,sp
|
||||
set_cc 0x0b ; condition codes should not change
|
||||
lduh @sp,r7
|
||||
test_cc 1 0 1 1
|
||||
test_h_gr 0x7fff,r7
|
||||
|
||||
mvi_h_mem #0x8000beef,sp
|
||||
set_cc 0x0d ; condition codes should not change
|
||||
lduh @sp,r7
|
||||
test_cc 1 1 0 1
|
||||
test_h_gr 0x8000,r7
|
||||
|
||||
mvi_h_mem #0xffffbeef,sp
|
||||
set_cc 0x0e ; condition codes should not change
|
||||
lduh @sp,r7
|
||||
test_cc 1 1 1 0
|
||||
test_h_gr 0xffff,r7
|
||||
|
||||
; Test lduh @($R13,$Rj),$Ri
|
||||
mvr_h_gr sp,r13
|
||||
inci_h_gr -8,r13
|
||||
mvi_h_gr 8,r8
|
||||
|
||||
mvi_h_mem #0x0000beef,sp
|
||||
set_cc 0x0f ; condition codes should not change
|
||||
lduh @(r13,r8),r7
|
||||
test_cc 1 1 1 1
|
||||
test_h_gr 0,r7
|
||||
|
||||
mvi_h_mem #0x0001beef,sp
|
||||
set_cc 0x07 ; condition codes should not change
|
||||
lduh @(r13,r8),r7
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr 1,r7
|
||||
|
||||
mvi_h_mem #0x7fffbeef,sp
|
||||
set_cc 0x0b ; condition codes should not change
|
||||
lduh @(r13,r8),r7
|
||||
test_cc 1 0 1 1
|
||||
test_h_gr 0x7fff,r7
|
||||
|
||||
mvi_h_mem #0x8000beef,sp
|
||||
set_cc 0x0d ; condition codes should not change
|
||||
lduh @(r13,r8),r7
|
||||
test_cc 1 1 0 1
|
||||
test_h_gr 0x8000,r7
|
||||
|
||||
mvi_h_mem #0xffffbeef,sp
|
||||
set_cc 0x0e ; condition codes should not change
|
||||
lduh @(r13,r8),r7
|
||||
test_cc 1 1 1 0
|
||||
test_h_gr 0xffff,r7
|
||||
|
||||
; Test lduh @($R14,$disp9),$Ri
|
||||
mvi_h_mem #0xdeadbeef,sp
|
||||
mvr_h_gr sp,r14
|
||||
mvi_h_gr -0xfe,r8
|
||||
add_h_gr r8,r14
|
||||
|
||||
set_cc 0x0f ; condition codes should not change
|
||||
lduh @(r14,0xfe),r7
|
||||
test_cc 1 1 1 1
|
||||
test_h_gr 0xdead,r7
|
||||
|
||||
inci_h_gr 0x7e,r14
|
||||
set_cc 0x07 ; condition codes should not change
|
||||
lduh @(r14,0x80),r7
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr 0xdead,r7
|
||||
|
||||
inci_h_gr 0x80,r14
|
||||
set_cc 0x0b ; condition codes should not change
|
||||
lduh @(r14,0x0),r7
|
||||
test_cc 1 0 1 1
|
||||
test_h_gr 0xdead,r7
|
||||
|
||||
inci_h_gr 0x80,r14
|
||||
set_cc 0x0d ; condition codes should not change
|
||||
lduh @(r14,-0x80),r7
|
||||
test_cc 1 1 0 1
|
||||
test_h_gr 0xdead,r7
|
||||
|
||||
inci_h_gr 0x80,r14
|
||||
set_cc 0x0e ; condition codes should not change
|
||||
lduh @(r14,-0x100),r7
|
||||
test_cc 1 1 1 0
|
||||
test_h_gr 0xdead,r7
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
# fr30 testcase for lsl $Rj,$Ri, lsl $u4,$Rj
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global lsl
|
||||
lsl:
|
||||
; Test lsl $Rj,$Ri
|
||||
mvi_h_gr 0xdeadbee0,r7 ; Shift by 0
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0d ; Set mask opposite of expected
|
||||
lsl r7,r8
|
||||
test_cc 0 0 0 0
|
||||
test_h_gr 2,r8
|
||||
|
||||
mvi_h_gr 0xdeadbee1,r7 ; Shift by 1
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0f ; Set mask opposite of expected
|
||||
lsl r7,r8
|
||||
test_cc 0 0 1 0
|
||||
test_h_gr 4,r8
|
||||
|
||||
mvi_h_gr 0xdeadbeff,r7 ; Shift by 31
|
||||
mvi_h_gr 1,r8
|
||||
set_cc 0x07 ; Set mask opposite of expected
|
||||
lsl r7,r8
|
||||
test_cc 1 0 1 0
|
||||
test_h_gr 0x80000000,r8
|
||||
|
||||
mvi_h_gr 0xdeadbeff,r7 ; clear register
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0a ; Set mask opposite of expected
|
||||
lsl r7,r8
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr 0x00000000,r8
|
||||
|
||||
; Test lsl $u4Ri
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0d ; Set mask opposite of expected
|
||||
lsl 0,r8
|
||||
test_cc 0 0 0 0
|
||||
test_h_gr 2,r8
|
||||
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0f ; Set mask opposite of expected
|
||||
lsl 1,r8
|
||||
test_cc 0 0 1 0
|
||||
test_h_gr 4,r8
|
||||
|
||||
mvi_h_gr 1,r8
|
||||
set_cc 0x0e ; Set mask opposite of expected
|
||||
lsl 15,r8
|
||||
test_cc 0 0 1 0
|
||||
test_h_gr 0x00008000,r8
|
||||
|
||||
mvi_h_gr 0x00020000,r8
|
||||
set_cc 0x0a ; Set mask opposite of expected
|
||||
lsl 15,r8
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr 0x00000000,r8
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
# fr30 testcase for lsl2 $Rj,$Ri, lsl2 $u4,$Rj
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global lsl2
|
||||
lsl2:
|
||||
; Test lsl2 $u4Ri
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0d ; Set mask opposite of expected
|
||||
lsl2 0,r8
|
||||
test_cc 0 0 0 0
|
||||
test_h_gr 0x20000,r8
|
||||
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0f ; Set mask opposite of expected
|
||||
lsl2 1,r8
|
||||
test_cc 0 0 1 0
|
||||
test_h_gr 0x40000,r8
|
||||
|
||||
mvi_h_gr 1,r8
|
||||
set_cc 0x07 ; Set mask opposite of expected
|
||||
lsl2 15,r8
|
||||
test_cc 1 0 1 0
|
||||
test_h_gr 0x80000000,r8
|
||||
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0a ; Set mask opposite of expected
|
||||
lsl2 15,r8
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr 0x00000000,r8
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
# fr30 testcase for lsr $Rj,$Ri, lsr $u4,$Rj
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global lsr
|
||||
lsr:
|
||||
; Test lsr $Rj,$Ri
|
||||
mvi_h_gr 0xdeadbee0,r7 ; Shift by 0
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x05 ; Set mask opposite of expected
|
||||
lsr r7,r8
|
||||
test_cc 1 0 0 0
|
||||
test_h_gr 0x80000000,r8
|
||||
|
||||
mvi_h_gr 0xdeadbee1,r7 ; Shift by 1
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x0f ; Set mask opposite of expected
|
||||
lsr r7,r8
|
||||
test_cc 0 0 1 0
|
||||
test_h_gr 0x40000000,r8
|
||||
|
||||
mvi_h_gr 0xdeadbeff,r7 ; Shift by 31
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x0f ; Set mask opposite of expected
|
||||
lsr r7,r8
|
||||
test_cc 0 0 1 0
|
||||
test_h_gr 1,r8
|
||||
|
||||
mvi_h_gr 0xdeadbeff,r7 ; clear register
|
||||
mvi_h_gr 0x40000000,r8
|
||||
set_cc 0x0a ; Set mask opposite of expected
|
||||
lsr r7,r8
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr 0x00000000,r8
|
||||
|
||||
; Test lsr $u4Ri
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x05 ; Set mask opposite of expected
|
||||
lsr 0,r8
|
||||
test_cc 1 0 0 0
|
||||
test_h_gr 0x80000000,r8
|
||||
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x0f ; Set mask opposite of expected
|
||||
lsr 1,r8
|
||||
test_cc 0 0 1 0
|
||||
test_h_gr 0x40000000,r8
|
||||
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x0e ; Set mask opposite of expected
|
||||
lsr 15,r8
|
||||
test_cc 0 0 1 0
|
||||
test_h_gr 0x00010000,r8
|
||||
|
||||
mvi_h_gr 0x00004000,r8
|
||||
set_cc 0x0a ; Set mask opposite of expected
|
||||
lsr 15,r8
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr 0x00000000,r8
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
# fr30 testcase for lsr2 $u4,$Rj
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global lsr2
|
||||
lsr2:
|
||||
; Test lsr2 $u4Ri
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x0d ; Set mask opposite of expected
|
||||
lsr2 0,r8
|
||||
test_cc 0 0 0 0
|
||||
test_h_gr 0x00008000,r8
|
||||
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x0f ; Set mask opposite of expected
|
||||
lsr2 1,r8
|
||||
test_cc 0 0 1 0
|
||||
test_h_gr 0x00004000,r8
|
||||
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x0e ; Set mask opposite of expected
|
||||
lsr2 15,r8
|
||||
test_cc 0 0 1 0
|
||||
test_h_gr 1,r8
|
||||
|
||||
mvi_h_gr 0x40000000,r8
|
||||
set_cc 0x0a ; Set mask opposite of expected
|
||||
lsr2 15,r8
|
||||
test_cc 0 1 1 1
|
||||
test_h_gr 0x00000000,r8
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
# Miscellaneous FR30 simulator testcases
|
||||
|
||||
if [istarget fr30*-*-*] {
|
||||
# load support procs
|
||||
# load_lib cgen.exp
|
||||
|
||||
# The .ms suffix is for "miscellaneous .s".
|
||||
foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] {
|
||||
# If we're only testing specific files and this isn't one of them,
|
||||
# skip it.
|
||||
if ![runtest_file_p $runtests $src] {
|
||||
continue
|
||||
}
|
||||
|
||||
run_sim_test $src
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,240 @@
|
|||
# fr30 testcase for mul $Rj,$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global mul
|
||||
mul:
|
||||
; Test mul $Rj,$Ri
|
||||
; Positive operands
|
||||
mvi_h_gr 3,r7 ; multiply small numbers
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0f ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 0 0 0 1
|
||||
test_h_dr 0,mdh
|
||||
test_h_dr 6,mdl
|
||||
|
||||
mvi_h_gr 1,r7 ; multiply by 1
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0e ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 0 0 0 0
|
||||
test_h_dr 0,mdh
|
||||
test_h_dr 2,mdl
|
||||
|
||||
mvi_h_gr 2,r7 ; multiply by 1
|
||||
mvi_h_gr 1,r8
|
||||
set_cc 0x0f ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 0 0 0 1
|
||||
test_h_dr 0,mdh
|
||||
test_h_dr 2,mdl
|
||||
|
||||
mvi_h_gr 0,r7 ; multiply by 0
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0b ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 0 1 0 1
|
||||
test_h_dr 0,mdh
|
||||
test_h_dr 0,mdl
|
||||
|
||||
mvi_h_gr 2,r7 ; multiply by 0
|
||||
mvi_h_gr 0,r8
|
||||
set_cc 0x0a ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 0 1 0 0
|
||||
test_h_dr 0,mdh
|
||||
test_h_dr 0,mdl
|
||||
|
||||
mvi_h_gr 0x3fffffff,r7 ; 31 bit result
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0f ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 0 0 0 1
|
||||
test_h_dr 0,mdh
|
||||
test_h_dr 0x7ffffffe,mdl
|
||||
|
||||
mvi_h_gr 0x40000000,r7 ; 32 bit result
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x04 ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 1 0 1 0
|
||||
test_h_dr 0,mdh
|
||||
test_h_dr 0x80000000,mdl
|
||||
|
||||
mvi_h_gr 0x40000000,r7 ; 33 bit result
|
||||
mvi_h_gr 4,r8
|
||||
set_cc 0x0d ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 0 0 1 1
|
||||
test_h_dr 1,mdh
|
||||
test_h_dr 0x00000000,mdl
|
||||
|
||||
mvi_h_gr 0x7fffffff,r7 ; max positive result
|
||||
mvi_h_gr 0x7fffffff,r8
|
||||
set_cc 0x0d ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 0 0 1 1
|
||||
test_h_dr 0x3fffffff,mdh
|
||||
test_h_dr 0x00000001,mdl
|
||||
|
||||
; Mixed operands
|
||||
mvi_h_gr -3,r7 ; multiply small numbers
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x07 ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 1 0 0 1
|
||||
test_h_dr -1,mdh
|
||||
test_h_dr -6,mdl
|
||||
|
||||
mvi_h_gr 3,r7 ; multiply small numbers
|
||||
mvi_h_gr -2,r8
|
||||
set_cc 0x07 ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 1 0 0 1
|
||||
test_h_dr -1,mdh
|
||||
test_h_dr -6,mdl
|
||||
|
||||
mvi_h_gr 1,r7 ; multiply by 1
|
||||
mvi_h_gr -2,r8
|
||||
set_cc 0x06 ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 1 0 0 0
|
||||
test_h_dr -1,mdh
|
||||
test_h_dr -2,mdl
|
||||
|
||||
mvi_h_gr -2,r7 ; multiply by 1
|
||||
mvi_h_gr 1,r8
|
||||
set_cc 0x07 ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 1 0 0 1
|
||||
test_h_dr -1,mdh
|
||||
test_h_dr -2,mdl
|
||||
|
||||
mvi_h_gr 0,r7 ; multiply by 0
|
||||
mvi_h_gr -2,r8
|
||||
set_cc 0x0b ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 0 1 0 1
|
||||
test_h_dr 0,mdh
|
||||
test_h_dr 0,mdl
|
||||
|
||||
mvi_h_gr -2,r7 ; multiply by 0
|
||||
mvi_h_gr 0,r8
|
||||
set_cc 0x0a ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 0 1 0 0
|
||||
test_h_dr 0,mdh
|
||||
test_h_dr 0,mdl
|
||||
|
||||
mvi_h_gr 0x20000001,r7 ; 31 bit result
|
||||
mvi_h_gr -2,r8
|
||||
set_cc 0x07 ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 1 0 0 1
|
||||
test_h_dr 0xffffffff,mdh
|
||||
test_h_dr 0xbffffffe,mdl
|
||||
|
||||
mvi_h_gr 0x40000000,r7 ; 32 bit result
|
||||
mvi_h_gr -2,r8
|
||||
set_cc 0x06 ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 1 0 0 0
|
||||
test_h_dr 0xffffffff,mdh
|
||||
test_h_dr 0x80000000,mdl
|
||||
|
||||
mvi_h_gr 0x40000001,r7 ; 32 bit result
|
||||
mvi_h_gr -2,r8
|
||||
set_cc 0x0c ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 0 0 1 0
|
||||
test_h_dr 0xffffffff,mdh
|
||||
test_h_dr 0x7ffffffe,mdl
|
||||
|
||||
mvi_h_gr 0x40000000,r7 ; 33 bit result
|
||||
mvi_h_gr -4,r8
|
||||
set_cc 0x0d ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 0 0 1 1
|
||||
test_h_dr 0xffffffff,mdh
|
||||
test_h_dr 0x00000000,mdl
|
||||
|
||||
mvi_h_gr 0x7fffffff,r7 ; max negative result
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x05 ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 1 0 1 1
|
||||
test_h_dr 0xc0000000,mdh
|
||||
test_h_dr 0x80000000,mdl
|
||||
|
||||
; Negative operands
|
||||
mvi_h_gr -3,r7 ; multiply small numbers
|
||||
mvi_h_gr -2,r8
|
||||
set_cc 0x0f ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 0 0 0 1
|
||||
test_h_dr 0,mdh
|
||||
test_h_dr 6,mdl
|
||||
|
||||
mvi_h_gr -1,r7 ; multiply by 1
|
||||
mvi_h_gr -2,r8
|
||||
set_cc 0x0e ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 0 0 0 0
|
||||
test_h_dr 0,mdh
|
||||
test_h_dr 2,mdl
|
||||
|
||||
mvi_h_gr -2,r7 ; multiply by 1
|
||||
mvi_h_gr -1,r8
|
||||
set_cc 0x0f ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 0 0 0 1
|
||||
test_h_dr 0,mdh
|
||||
test_h_dr 2,mdl
|
||||
|
||||
mvi_h_gr 0xc0000001,r7 ; 31 bit result
|
||||
mvi_h_gr -2,r8
|
||||
set_cc 0x0f ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 0 0 0 1
|
||||
test_h_dr 0,mdh
|
||||
test_h_dr 0x7ffffffe,mdl
|
||||
|
||||
mvi_h_gr 0xc0000000,r7 ; 32 bit result
|
||||
mvi_h_gr -2,r8
|
||||
set_cc 0x04 ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 1 0 1 0
|
||||
test_h_dr 0,mdh
|
||||
test_h_dr 0x80000000,mdl
|
||||
|
||||
mvi_h_gr 0xc0000000,r7 ; 33 bit result
|
||||
mvi_h_gr -4,r8
|
||||
set_cc 0x0d ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 0 0 1 1
|
||||
test_h_dr 1,mdh
|
||||
test_h_dr 0x00000000,mdl
|
||||
|
||||
mvi_h_gr 0x80000001,r7 ; almost max positive result
|
||||
mvi_h_gr 0x80000001,r8
|
||||
set_cc 0x0d ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 0 0 1 1
|
||||
test_h_dr 0x3fffffff,mdh
|
||||
test_h_dr 0x00000001,mdl
|
||||
|
||||
|
||||
mvi_h_gr 0x80000000,r7 ; max positive result
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x0d ; Set mask opposite of expected
|
||||
mul r7,r8
|
||||
test_cc 0 0 1 1
|
||||
test_h_dr 0x40000000,mdh
|
||||
test_h_dr 0x00000000,mdl
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,211 @@
|
|||
# fr30 testcase for mulh $Rj,$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global mulh
|
||||
mulh:
|
||||
; Test mulh $Rj,$Ri
|
||||
; Positive operands
|
||||
mvi_h_gr 0xdead0003,r7 ; multiply small numbers
|
||||
mvi_h_gr 0xbeef0002,r8
|
||||
set_cc 0x09 ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 0 1 0 1
|
||||
test_h_dr 6,mdl
|
||||
|
||||
mvi_h_gr 0xdead0001,r7 ; multiply by 1
|
||||
mvi_h_gr 0xbeef0002,r8
|
||||
set_cc 0x08 ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 0 1 0 0
|
||||
test_h_dr 2,mdl
|
||||
|
||||
mvi_h_gr 0xdead0002,r7 ; multiply by 1
|
||||
mvi_h_gr 0xbeef0001,r8
|
||||
set_cc 0x09 ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 0 1 0 1
|
||||
test_h_dr 2,mdl
|
||||
|
||||
mvi_h_gr 0xdead0000,r7 ; multiply by 0
|
||||
mvi_h_gr 0xbeef0002,r8
|
||||
set_cc 0x09 ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 0 1 0 1
|
||||
test_h_dr 0,mdl
|
||||
|
||||
mvi_h_gr 0xdead0002,r7 ; multiply by 0
|
||||
mvi_h_gr 0xbeef0000,r8
|
||||
set_cc 0x08 ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 0 1 0 0
|
||||
test_h_dr 0,mdl
|
||||
|
||||
mvi_h_gr 0xdead3fff,r7 ; 15 bit result
|
||||
mvi_h_gr 0xbeef0002,r8
|
||||
set_cc 0x09 ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 0 1 0 1
|
||||
test_h_dr 0x00007ffe,mdl
|
||||
|
||||
mvi_h_gr 0xdead4000,r7 ; 16 bit result
|
||||
mvi_h_gr 0xbeef0002,r8
|
||||
set_cc 0x0a ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 0 1 1 0
|
||||
test_h_dr 0x00008000,mdl
|
||||
|
||||
mvi_h_gr 0xdead4000,r7 ; 17 bit result
|
||||
mvi_h_gr 0xbeef0004,r8
|
||||
set_cc 0x0b ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 0 1 1 1
|
||||
test_h_dr 0x00010000,mdl
|
||||
|
||||
mvi_h_gr 0xdead7fff,r7 ; max positive result
|
||||
mvi_h_gr 0xbeef7fff,r8
|
||||
set_cc 0x0b ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 0 1 1 1
|
||||
test_h_dr 0x3fff0001,mdl
|
||||
|
||||
; Mixed operands
|
||||
mvi_h_gr -3,r7 ; multiply small numbers
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x05 ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 1 0 0 1
|
||||
test_h_dr -6,mdl
|
||||
|
||||
mvi_h_gr 3,r7 ; multiply small numbers
|
||||
mvi_h_gr -2,r8
|
||||
set_cc 0x05 ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 1 0 0 1
|
||||
test_h_dr -6,mdl
|
||||
|
||||
mvi_h_gr 1,r7 ; multiply by 1
|
||||
mvi_h_gr -2,r8
|
||||
set_cc 0x04 ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 1 0 0 0
|
||||
test_h_dr -2,mdl
|
||||
|
||||
mvi_h_gr -2,r7 ; multiply by 1
|
||||
mvi_h_gr 1,r8
|
||||
set_cc 0x05 ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 1 0 0 1
|
||||
test_h_dr -2,mdl
|
||||
|
||||
mvi_h_gr 0,r7 ; multiply by 0
|
||||
mvi_h_gr -2,r8
|
||||
set_cc 0x09 ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 0 1 0 1
|
||||
test_h_dr 0,mdl
|
||||
|
||||
mvi_h_gr -2,r7 ; multiply by 0
|
||||
mvi_h_gr 0,r8
|
||||
set_cc 0x08 ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 0 1 0 0
|
||||
test_h_dr 0,mdl
|
||||
|
||||
mvi_h_gr 0xdead2001,r7 ; 15 bit result
|
||||
mvi_h_gr -2,r8
|
||||
set_cc 0x05 ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 1 0 0 1
|
||||
test_h_dr 0xffffbffe,mdl
|
||||
|
||||
mvi_h_gr 0xdead4000,r7 ; 16 bit result
|
||||
mvi_h_gr -2,r8
|
||||
set_cc 0x04 ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 1 0 0 0
|
||||
test_h_dr 0xffff8000,mdl
|
||||
|
||||
mvi_h_gr 0xdead4001,r7 ; 16 bit result
|
||||
mvi_h_gr -2,r8
|
||||
set_cc 0x06 ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 1 0 1 0
|
||||
test_h_dr 0xffff7ffe,mdl
|
||||
|
||||
mvi_h_gr 0xdead4000,r7 ; 17 bit result
|
||||
mvi_h_gr -4,r8
|
||||
set_cc 0x07 ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 1 0 1 1
|
||||
test_h_dr 0xffff0000,mdl
|
||||
|
||||
mvi_h_gr 0xdead7fff,r7 ; max negative result
|
||||
mvi_h_gr 0xbeef8000,r8
|
||||
set_cc 0x07 ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 1 0 1 1
|
||||
test_h_dr 0xc0008000,mdl
|
||||
|
||||
; Negative operands
|
||||
mvi_h_gr -3,r7 ; multiply small numbers
|
||||
mvi_h_gr -2,r8
|
||||
set_cc 0x09 ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 0 1 0 1
|
||||
test_h_dr 6,mdl
|
||||
|
||||
mvi_h_gr -1,r7 ; multiply by 1
|
||||
mvi_h_gr -2,r8
|
||||
set_cc 0x08 ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 0 1 0 0
|
||||
test_h_dr 2,mdl
|
||||
|
||||
mvi_h_gr -2,r7 ; multiply by 1
|
||||
mvi_h_gr -1,r8
|
||||
set_cc 0x09 ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 0 1 0 1
|
||||
test_h_dr 2,mdl
|
||||
|
||||
mvi_h_gr 0xdeadc001,r7 ; 15 bit result
|
||||
mvi_h_gr -2,r8
|
||||
set_cc 0x09 ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 0 1 0 1
|
||||
test_h_dr 0x00007ffe,mdl
|
||||
|
||||
mvi_h_gr 0xdeadc000,r7 ; 16 bit result
|
||||
mvi_h_gr -2,r8
|
||||
set_cc 0x0a ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 0 1 1 0
|
||||
test_h_dr 0x00008000,mdl
|
||||
|
||||
mvi_h_gr 0xdeadc000,r7 ; 17 bit result
|
||||
mvi_h_gr -4,r8
|
||||
set_cc 0x0b ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 0 1 1 1
|
||||
test_h_dr 0x00010000,mdl
|
||||
|
||||
mvi_h_gr 0xdead8001,r7 ; almost max positive result
|
||||
mvi_h_gr 0xbeef8001,r8
|
||||
set_cc 0x0b ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 0 1 1 1
|
||||
test_h_dr 0x3fff0001,mdl
|
||||
|
||||
mvi_h_gr 0xdead8000,r7 ; max positive result
|
||||
mvi_h_gr 0xbeef8000,r8
|
||||
set_cc 0x0b ; Set mask opposite of expected
|
||||
mulh r7,r8
|
||||
test_cc 0 1 1 1
|
||||
test_h_dr 0x40000000,mdl
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,101 @@
|
|||
# fr30 testcase for mulu $Rj,$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global mulu
|
||||
mulu:
|
||||
; Test mulu $Rj,$Ri
|
||||
; Positive operands
|
||||
mvi_h_gr 3,r7 ; multiply small numbers
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0f ; Set mask opposite of expected
|
||||
mulu r7,r8
|
||||
test_cc 0 0 0 1
|
||||
test_h_dr 0,mdh
|
||||
test_h_dr 6,mdl
|
||||
|
||||
mvi_h_gr 1,r7 ; multiply by 1
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0e ; Set mask opposite of expected
|
||||
mulu r7,r8
|
||||
test_cc 0 0 0 0
|
||||
test_h_dr 0,mdh
|
||||
test_h_dr 2,mdl
|
||||
|
||||
mvi_h_gr 2,r7 ; multiply by 1
|
||||
mvi_h_gr 1,r8
|
||||
set_cc 0x0f ; Set mask opposite of expected
|
||||
mulu r7,r8
|
||||
test_cc 0 0 0 1
|
||||
test_h_dr 0,mdh
|
||||
test_h_dr 2,mdl
|
||||
|
||||
mvi_h_gr 0,r7 ; multiply by 0
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0b ; Set mask opposite of expected
|
||||
mulu r7,r8
|
||||
test_cc 0 1 0 1
|
||||
test_h_dr 0,mdh
|
||||
test_h_dr 0,mdl
|
||||
|
||||
mvi_h_gr 2,r7 ; multiply by 0
|
||||
mvi_h_gr 0,r8
|
||||
set_cc 0x0a ; Set mask opposite of expected
|
||||
mulu r7,r8
|
||||
test_cc 0 1 0 0
|
||||
test_h_dr 0,mdh
|
||||
test_h_dr 0,mdl
|
||||
|
||||
mvi_h_gr 0x3fffffff,r7 ; 31 bit result
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0f ; Set mask opposite of expected
|
||||
mulu r7,r8
|
||||
test_cc 0 0 0 1
|
||||
test_h_dr 0,mdh
|
||||
test_h_dr 0x7ffffffe,mdl
|
||||
|
||||
mvi_h_gr 0x40000000,r7 ; 32 bit result
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0e ; Set mask opposite of expected
|
||||
mulu r7,r8
|
||||
test_cc 0 0 0 0
|
||||
test_h_dr 0,mdh
|
||||
test_h_dr 0x80000000,mdl
|
||||
|
||||
mvi_h_gr 0x80000000,r7 ; 33 bit result
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x09 ; Set mask opposite of expected
|
||||
mulu r7,r8
|
||||
test_cc 0 1 1 1
|
||||
test_h_dr 1,mdh
|
||||
test_h_dr 0x00000000,mdl
|
||||
|
||||
mvi_h_gr 0x7fffffff,r7 ; max positive result
|
||||
mvi_h_gr 0x7fffffff,r8
|
||||
set_cc 0x0d ; Set mask opposite of expected
|
||||
mulu r7,r8
|
||||
test_cc 0 0 1 1
|
||||
test_h_dr 0x3fffffff,mdh
|
||||
test_h_dr 0x00000001,mdl
|
||||
|
||||
mvi_h_gr 0x80000000,r7 ; max positive result
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x09 ; Set mask opposite of expected
|
||||
mulu r7,r8
|
||||
test_cc 0 1 1 1
|
||||
test_h_dr 0x40000000,mdh
|
||||
test_h_dr 0x00000000,mdl
|
||||
|
||||
mvi_h_gr 0xffffffff,r7 ; max positive result
|
||||
mvi_h_gr 0xffffffff,r8
|
||||
set_cc 0x05 ; Set mask opposite of expected
|
||||
mulu r7,r8
|
||||
test_cc 1 0 1 1
|
||||
test_h_dr 0xfffffffe,mdh
|
||||
test_h_dr 0x00000001,mdl
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,90 @@
|
|||
# fr30 testcase for muluh $Rj,$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global muluh
|
||||
muluh:
|
||||
; Test muluh $Rj,$Ri
|
||||
; Positive operands
|
||||
mvi_h_gr 0xdead0003,r7 ; multiply small numbers
|
||||
mvi_h_gr 0xbeef0002,r8
|
||||
set_cc 0x09 ; Set mask opposite of expected
|
||||
muluh r7,r8
|
||||
test_cc 0 1 0 1
|
||||
test_h_dr 6,mdl
|
||||
|
||||
mvi_h_gr 0xdead0001,r7 ; multiply by 1
|
||||
mvi_h_gr 0xbeef0002,r8
|
||||
set_cc 0x08 ; Set mask opposite of expected
|
||||
muluh r7,r8
|
||||
test_cc 0 1 0 0
|
||||
test_h_dr 2,mdl
|
||||
|
||||
mvi_h_gr 0xdead0002,r7 ; multiply by 1
|
||||
mvi_h_gr 0xbeef0001,r8
|
||||
set_cc 0x09 ; Set mask opposite of expected
|
||||
muluh r7,r8
|
||||
test_cc 0 1 0 1
|
||||
test_h_dr 2,mdl
|
||||
|
||||
mvi_h_gr 0xdead0000,r7 ; multiply by 0
|
||||
mvi_h_gr 0xbeef0002,r8
|
||||
set_cc 0x09 ; Set mask opposite of expected
|
||||
muluh r7,r8
|
||||
test_cc 0 1 0 1
|
||||
test_h_dr 0,mdl
|
||||
|
||||
mvi_h_gr 0xdead0002,r7 ; multiply by 0
|
||||
mvi_h_gr 0xbeef0000,r8
|
||||
set_cc 0x08 ; Set mask opposite of expected
|
||||
muluh r7,r8
|
||||
test_cc 0 1 0 0
|
||||
test_h_dr 0,mdl
|
||||
|
||||
mvi_h_gr 0xdead3fff,r7 ; 15 bit result
|
||||
mvi_h_gr 0xbeef0002,r8
|
||||
set_cc 0x09 ; Set mask opposite of expected
|
||||
muluh r7,r8
|
||||
test_cc 0 1 0 1
|
||||
test_h_dr 0x00007ffe,mdl
|
||||
|
||||
mvi_h_gr 0xdead4000,r7 ; 16 bit result
|
||||
mvi_h_gr 0xbeef0002,r8
|
||||
set_cc 0x08 ; Set mask opposite of expected
|
||||
muluh r7,r8
|
||||
test_cc 0 1 0 0
|
||||
test_h_dr 0x00008000,mdl
|
||||
|
||||
mvi_h_gr 0xdead8000,r7 ; 17 bit result
|
||||
mvi_h_gr 0xbeef0002,r8
|
||||
set_cc 0x0b ; Set mask opposite of expected
|
||||
muluh r7,r8
|
||||
test_cc 0 1 1 1
|
||||
test_h_dr 0x00010000,mdl
|
||||
|
||||
mvi_h_gr 0xdead7fff,r7 ; max positive result
|
||||
mvi_h_gr 0xbeef7fff,r8
|
||||
set_cc 0x0b ; Set mask opposite of expected
|
||||
muluh r7,r8
|
||||
test_cc 0 1 1 1
|
||||
test_h_dr 0x3fff0001,mdl
|
||||
|
||||
mvi_h_gr 0xdead8000,r7 ; max positive result
|
||||
mvi_h_gr 0xbeef8000,r8
|
||||
set_cc 0x0b ; Set mask opposite of expected
|
||||
muluh r7,r8
|
||||
test_cc 0 1 1 1
|
||||
test_h_dr 0x40000000,mdl
|
||||
|
||||
mvi_h_gr 0xdeadffff,r7 ; max positive result
|
||||
mvi_h_gr 0xbeefffff,r8
|
||||
set_cc 0x07 ; Set mask opposite of expected
|
||||
muluh r7,r8
|
||||
test_cc 1 0 1 1
|
||||
test_h_dr 0xfffe0001,mdl
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
# fr30 testcase for or $Rj,$Ri, or $Rj,@$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global or
|
||||
or:
|
||||
; Test or $Rj,$Ri
|
||||
mvi_h_gr 0xaaaaaaaa,r7
|
||||
mvi_h_gr 0x55555555,r8
|
||||
set_cc 0x07 ; Set mask opposite of expected
|
||||
or r7,r8
|
||||
test_cc 1 0 1 1
|
||||
test_h_gr 0xffffffff,r8
|
||||
|
||||
mvi_h_gr 0x00000000,r7
|
||||
mvi_h_gr 0x00000000,r8
|
||||
set_cc 0x08 ; Set mask opposite of expected
|
||||
or r7,r8
|
||||
test_cc 0 1 0 0
|
||||
test_h_gr 0x00000000,r8
|
||||
|
||||
mvi_h_gr 0xdead0000,r7
|
||||
mvi_h_gr 0x0000beef,r8
|
||||
set_cc 0x05 ; Set mask opposite of expected
|
||||
or r7,r8
|
||||
test_cc 1 0 0 1
|
||||
test_h_gr 0xdeadbeef,r8
|
||||
|
||||
; Test or $Rj,@$Ri
|
||||
mvi_h_gr 0xaaaaaaaa,r7
|
||||
mvi_h_mem 0x55555555,sp
|
||||
set_cc 0x07 ; Set mask opposite of expected
|
||||
or r7,@sp
|
||||
test_cc 1 0 1 1
|
||||
test_h_mem 0xffffffff,sp
|
||||
|
||||
mvi_h_gr 0x00000000,r7
|
||||
mvi_h_mem 0x00000000,sp
|
||||
set_cc 0x08 ; Set mask opposite of expected
|
||||
or r7,@sp
|
||||
test_cc 0 1 0 0
|
||||
test_h_mem 0x00000000,sp
|
||||
|
||||
mvi_h_gr 0xdead0000,r7
|
||||
mvi_h_mem 0x0000beef,sp
|
||||
set_cc 0x05 ; Set mask opposite of expected
|
||||
or r7,@sp
|
||||
test_cc 1 0 0 1
|
||||
test_h_mem 0xdeadbeef,sp
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
# fr30 testcase for orb $Rj,$Ri, orb $Rj,@$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global orb
|
||||
orb:
|
||||
; Test orb $Rj,@$Ri
|
||||
mvi_h_gr 0xaaaaaaaa,r7
|
||||
mvi_h_mem 0x55555555,sp
|
||||
set_cc 0x07 ; Set mask opposite of expected
|
||||
orb r7,@sp
|
||||
test_cc 1 0 1 1
|
||||
test_h_mem 0xff555555,sp
|
||||
|
||||
mvi_h_gr 0xffffff00,r7
|
||||
mvi_h_mem 0x00ffffff,sp
|
||||
set_cc 0x08 ; Set mask opposite of expected
|
||||
orb r7,@sp
|
||||
test_cc 0 1 0 0
|
||||
test_h_mem 0x00ffffff,sp
|
||||
|
||||
mvi_h_gr 0x000000d0,r7
|
||||
mvi_h_mem 0x0eadbeef,sp
|
||||
set_cc 0x05 ; Set mask opposite of expected
|
||||
orb r7,@sp
|
||||
test_cc 1 0 0 1
|
||||
test_h_mem 0xdeadbeef,sp
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
# fr30 testcase for orh $Rj,$Ri, orh $Rj,@$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global orh
|
||||
orh:
|
||||
; Test orh $Rj,@$Ri
|
||||
mvi_h_gr 0xaaaaaaaa,r7
|
||||
mvi_h_mem 0x55555555,sp
|
||||
set_cc 0x07 ; Set mask opposite of expected
|
||||
orh r7,@sp
|
||||
test_cc 1 0 1 1
|
||||
test_h_mem 0xffff5555,sp
|
||||
|
||||
mvi_h_gr 0xffff0000,r7
|
||||
mvi_h_mem 0x0000ffff,sp
|
||||
set_cc 0x08 ; Set mask opposite of expected
|
||||
orh r7,@sp
|
||||
test_cc 0 1 0 0
|
||||
test_h_mem 0x0000ffff,sp
|
||||
|
||||
mvi_h_gr 0x0000de00,r7
|
||||
mvi_h_mem 0x00adbeef,sp
|
||||
set_cc 0x05 ; Set mask opposite of expected
|
||||
orh r7,@sp
|
||||
test_cc 1 0 0 1
|
||||
test_h_mem 0xdeadbeef,sp
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
# fr30 testcase for sub $Rj,$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global sub
|
||||
sub:
|
||||
; Test sub $Rj,$Ri
|
||||
mvi_h_gr 1,r7
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0f ; Set mask opposite of expected
|
||||
sub r7,r8
|
||||
test_cc 0 0 0 0
|
||||
test_h_gr 1,r8
|
||||
|
||||
mvi_h_gr 1,r7
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x0d ; Set mask opposite of expected
|
||||
sub r7,r8
|
||||
test_cc 0 0 1 0
|
||||
test_h_gr 0x7fffffff,r8
|
||||
|
||||
set_cc 0x0b ; Set mask opposite of expected
|
||||
sub r8,r8
|
||||
test_cc 0 1 0 0
|
||||
test_h_gr 0,r8
|
||||
|
||||
set_cc 0x06 ; Set mask opposite of expected
|
||||
sub r7,r8
|
||||
test_cc 1 0 0 1
|
||||
test_h_gr 0xffffffff,r8
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
# fr30 testcase for subc $Rj,$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global subc
|
||||
subc:
|
||||
; Test subc $Rj,$Ri
|
||||
mvi_h_gr 1,r7
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0e ; Make sure carry is off
|
||||
subc r7,r8
|
||||
test_cc 0 0 0 0
|
||||
test_h_gr 1,r8
|
||||
|
||||
mvi_h_gr 1,r7
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x0c ; Make sure carry is off
|
||||
subc r7,r8
|
||||
test_cc 0 0 1 0
|
||||
test_h_gr 0x7fffffff,r8
|
||||
|
||||
set_cc 0x0a ; Make sure carry is off
|
||||
subc r8,r8
|
||||
test_cc 0 1 0 0
|
||||
test_h_gr 0,r8
|
||||
|
||||
set_cc 0x06 ; Make sure carry is off
|
||||
subc r7,r8
|
||||
test_cc 1 0 0 1
|
||||
test_h_gr 0xffffffff,r8
|
||||
|
||||
mvi_h_gr 1,r7
|
||||
mvi_h_gr 3,r8
|
||||
set_cc 0x0f ; Make sure carry is on
|
||||
subc r7,r8
|
||||
test_cc 0 0 0 0
|
||||
test_h_gr 1,r8
|
||||
|
||||
mvi_h_gr 0,r7
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x0d ; Make sure carry is on
|
||||
subc r7,r8
|
||||
test_cc 0 0 1 0
|
||||
test_h_gr 0x7fffffff,r8
|
||||
|
||||
mvi_h_gr 0x7ffffffe,r7
|
||||
set_cc 0x0b ; Make sure carry is on
|
||||
subc r7,r8
|
||||
test_cc 0 1 0 0
|
||||
test_h_gr 0,r8
|
||||
|
||||
mvi_h_gr 0,r7
|
||||
set_cc 0x07 ; Make sure carry is on
|
||||
subc r7,r8
|
||||
test_cc 1 0 0 1
|
||||
test_h_gr 0xffffffff,r8
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
# fr30 testcase for subn $Rj,$Ri
|
||||
# mach(): fr30
|
||||
|
||||
.include "testutils.inc"
|
||||
|
||||
START
|
||||
|
||||
.text
|
||||
.global subn
|
||||
subn:
|
||||
; Test subn $Rj,$Ri
|
||||
mvi_h_gr 1,r7
|
||||
mvi_h_gr 2,r8
|
||||
set_cc 0x0f ; Set mask opposite of usual result
|
||||
subn r7,r8
|
||||
test_cc 1 1 1 1
|
||||
test_h_gr 1,r8
|
||||
|
||||
mvi_h_gr 1,r7
|
||||
mvi_h_gr 0x80000000,r8
|
||||
set_cc 0x0d ; Set mask opposite of usual result
|
||||
subn r7,r8
|
||||
test_cc 1 1 0 1
|
||||
test_h_gr 0x7fffffff,r8
|
||||
|
||||
set_cc 0x0b ; Set mask opposite of usual result
|
||||
subn r8,r8
|
||||
test_cc 1 0 1 1
|
||||
test_h_gr 0,r8
|
||||
|
||||
set_cc 0x06 ; Set mask opposite of usual result
|
||||
subn r7,r8
|
||||
test_cc 0 1 1 0
|
||||
test_h_gr 0xffffffff,r8
|
||||
|
||||
pass
|
||||
|
|
@ -0,0 +1,149 @@
|
|||
# r0, r4-r6 are used as tmps, consider them call clobbered by these macros.
|
||||
|
||||
.macro start
|
||||
.data
|
||||
failmsg:
|
||||
.ascii "fail\n"
|
||||
passmsg:
|
||||
.ascii "pass\n"
|
||||
.text
|
||||
.global _start
|
||||
_start:
|
||||
ldi32 0x7fffc,sp ; TODO -- what's a good value for this?
|
||||
.endm
|
||||
|
||||
; Exit with return code
|
||||
.macro exit rc
|
||||
ldi32 \rc,r4
|
||||
ldi32 #1,r0
|
||||
int #10
|
||||
.endm
|
||||
|
||||
; Pass the test case
|
||||
.macro pass
|
||||
ldi32 #5,r6
|
||||
ldi32 #passmsg,r5
|
||||
ldi32 #1,r4
|
||||
ldi32 #5,r0
|
||||
int #10
|
||||
exit #0
|
||||
.endm
|
||||
|
||||
; Fail the testcase
|
||||
.macro fail
|
||||
ldi32 #5,r6
|
||||
ldi32 #failmsg,r5
|
||||
ldi32 #1,r4
|
||||
ldi32 #5,r0
|
||||
int #10
|
||||
exit #1
|
||||
.endm
|
||||
|
||||
; Load an immediate value into a general register
|
||||
; TODO: use minimal sized insn
|
||||
.macro mvi_h_gr val reg
|
||||
ldi32 \val,\reg
|
||||
.endm
|
||||
|
||||
; Load a general register into another general register
|
||||
.macro mvr_h_gr src targ
|
||||
mov \src,\targ
|
||||
.endm
|
||||
|
||||
; Store an immediate into a word in memory
|
||||
.macro mvi_h_mem val addr
|
||||
mvi_h_gr \val r4
|
||||
mvr_h_mem r4,\addr
|
||||
.endm
|
||||
|
||||
; Store a register into a word in memory
|
||||
.macro mvr_h_mem reg addr
|
||||
st \reg,@\addr
|
||||
.endm
|
||||
|
||||
; Load a word value from memory
|
||||
.macro ldmem_h_gr addr reg
|
||||
ld @\addr,\reg
|
||||
.endm
|
||||
|
||||
; Add 2 general registers
|
||||
.macro add_h_gr reg1 reg2
|
||||
add \reg1,\reg2
|
||||
.endm
|
||||
|
||||
; Increment a register by and immediate
|
||||
.macro inci_h_gr inc reg
|
||||
mvi_h_gr \inc,r4
|
||||
add r4,\reg
|
||||
.endm
|
||||
|
||||
; Test the value of an immediate against a general register
|
||||
.macro test_h_gr val reg
|
||||
.if (\val >= 0) && (\val <= 15)
|
||||
cmp \val,\reg
|
||||
.else
|
||||
.if (\val < 0) && (\val >= -16)
|
||||
cmp2 \val,\reg
|
||||
.else
|
||||
ldi32 \val,r4
|
||||
cmp r4,\reg
|
||||
.endif
|
||||
.endif
|
||||
beq test_gr\@
|
||||
fail
|
||||
test_gr\@:
|
||||
.endm
|
||||
|
||||
; compare two general registers
|
||||
.macro testr_h_gr reg1 reg2
|
||||
cmp \reg1,\reg2
|
||||
beq testr_gr\@
|
||||
fail
|
||||
testr_gr\@:
|
||||
.endm
|
||||
|
||||
; Test the value of an immediate against a dedicated register
|
||||
.macro test_h_dr val reg
|
||||
mov \reg,r5
|
||||
test_h_gr \val r5
|
||||
.endm
|
||||
|
||||
; Compare an immediate with word in memory
|
||||
.macro test_h_mem val addr
|
||||
ldmem_h_gr \addr r5
|
||||
test_h_gr \val r5
|
||||
.endm
|
||||
|
||||
; Set the condition codes
|
||||
.macro set_cc mask
|
||||
andccr 0xf0
|
||||
orccr \mask
|
||||
.endm
|
||||
|
||||
; Test the condition codes
|
||||
.macro test_cc N Z V C
|
||||
.if (\N == 1)
|
||||
bp fail\@
|
||||
.else
|
||||
bn fail\@
|
||||
.endif
|
||||
.if (\Z == 1)
|
||||
bne fail\@
|
||||
.else
|
||||
beq fail\@
|
||||
.endif
|
||||
.if (\V == 1)
|
||||
bnv fail\@
|
||||
.else
|
||||
bv fail\@
|
||||
.endif
|
||||
.if (\C == 1)
|
||||
bnc fail\@
|
||||
.else
|
||||
bc fail\@
|
||||
.endif
|
||||
bra test_cc\@
|
||||
fail\@:
|
||||
fail
|
||||
test_cc\@:
|
||||
.endm
|
||||
Loading…
Reference in New Issue