Power10 dcbf, sync, and wait extensions.
opcodes/ * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new WC values on POWER10 sync, dcbf and wait instructions. (insert_pl, extract_pl): New functions. (L2OPT, LS, WC): Use insert_ls and extract_ls. (LS3): New , 3-bit L for sync. (LS3, L3OPT): New, 3-bit L for sync and dcbf. (SC2, PL): New, 2-bit SC and PL for sync and wait. (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks. (XOPL3, XWCPL, XSYNCLS): New opcode macros. (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync, plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics. <wait>: Enable PL operand on POWER10. <dcbf>: Enable L3OPT operand on POWER10. <sync>: Enable SC2 operand on POWER10. gas/ * testsuite/gas/ppc/power9.s <dcbf, dcbfl, dcbflp>: Add tests. * testsuite/gas/ppc/power9.d: Likewise. * testsuite/gas/ppc/power10.s <dcbf, dcbfps, dcbstps, hwsync, lwsync, pause_short, phwsync, plwsync, ptesync, stcisync, stncisync, stsync, sync, wait, waitrsv>: Add tests. * testsuite/gas/ppc/power10.d: Likewise.
This commit is contained in:
Peter Bergner
parent
3c568b8afa
commit
3d205eb448
@ -1,3 +1,12 @@
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2020-05-19 Peter Bergner <bergner@linux.ibm.com>
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* testsuite/gas/ppc/power9.s <dcbf, dcbfl, dcbflp>: Add tests.
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* testsuite/gas/ppc/power9.d: Likewise.
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* testsuite/gas/ppc/power10.s <dcbf, dcbfps, dcbstps, hwsync, lwsync,
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pause_short, phwsync, plwsync, ptesync, stcisync, stncisync, stsync,
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sync, wait, waitrsv>: Add tests.
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* testsuite/gas/ppc/power10.d: Likewise.
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2020-05-19 Alexander Fedotov <alfedotov@gmail.com>
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PR 25992
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@ -13,4 +13,39 @@ Disassembly of section \.text:
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.*: (7c 2a 5f 0d|0d 5f 2a 7c) paste\. r10,r11
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.*: (7c 2a 5f 0d|0d 5f 2a 7c) paste\. r10,r11
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.*: (7c 0a 5f 0d|0d 5f 0a 7c) paste\. r10,r11,0
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.*: (7c 80 18 ac|ac 18 80 7c) dcbfps 0,r3
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.*: (7c 80 18 ac|ac 18 80 7c) dcbfps 0,r3
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.*: (7c c0 18 ac|ac 18 c0 7c) dcbstps 0,r3
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.*: (7c c0 18 ac|ac 18 c0 7c) dcbstps 0,r3
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.*: (7c 00 04 ac|ac 04 00 7c) hwsync
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.*: (7c 00 04 ac|ac 04 00 7c) hwsync
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.*: (7c 00 04 ac|ac 04 00 7c) hwsync
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.*: (7c 00 04 ac|ac 04 00 7c) hwsync
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.*: (7c 20 04 ac|ac 04 20 7c) lwsync
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.*: (7c 20 04 ac|ac 04 20 7c) lwsync
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.*: (7c 20 04 ac|ac 04 20 7c) lwsync
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.*: (7c 40 04 ac|ac 04 40 7c) ptesync
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.*: (7c 40 04 ac|ac 04 40 7c) ptesync
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.*: (7c 40 04 ac|ac 04 40 7c) ptesync
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.*: (7c 80 04 ac|ac 04 80 7c) phwsync
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.*: (7c 80 04 ac|ac 04 80 7c) phwsync
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.*: (7c 80 04 ac|ac 04 80 7c) phwsync
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.*: (7c a0 04 ac|ac 04 a0 7c) plwsync
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.*: (7c a0 04 ac|ac 04 a0 7c) plwsync
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.*: (7c a0 04 ac|ac 04 a0 7c) plwsync
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.*: (7c 21 04 ac|ac 04 21 7c) stncisync
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.*: (7c 21 04 ac|ac 04 21 7c) stncisync
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.*: (7c 02 04 ac|ac 04 02 7c) stcisync
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.*: (7c 02 04 ac|ac 04 02 7c) stcisync
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.*: (7c 03 04 ac|ac 04 03 7c) stsync
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.*: (7c 03 04 ac|ac 04 03 7c) stsync
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.*: (7c 00 00 3c|3c 00 00 7c) wait
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.*: (7c 00 00 3c|3c 00 00 7c) wait
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.*: (7c 00 00 3c|3c 00 00 7c) wait
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.*: (7c 20 00 3c|3c 00 20 7c) waitrsv
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.*: (7c 20 00 3c|3c 00 20 7c) waitrsv
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.*: (7c 20 00 3c|3c 00 20 7c) waitrsv
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.*: (7c 40 00 3c|3c 00 40 7c) pause_short
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.*: (7c 40 00 3c|3c 00 40 7c) pause_short
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.*: (7c 40 00 3c|3c 00 40 7c) pause_short
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#pass
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@ -6,3 +6,38 @@ _start:
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paste. 10,11
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paste. 10,11,1
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paste. 10,11,0
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dcbfps 0,3
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dcbf 0,3,4
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dcbstps 0,3
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dcbf 0,3,6
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hwsync
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sync
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sync 0
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sync 0,0
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lwsync
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sync 1
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sync 1,0
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ptesync
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sync 2
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sync 2,0
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phwsync
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sync 4
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sync 4,0
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plwsync
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sync 5
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sync 5,0
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stncisync
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sync 1,1
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stcisync
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sync 0,2
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stsync
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sync 0,3
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wait
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wait 0
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wait 0,0
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waitrsv
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wait 1
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wait 1,0
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pause_short
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wait 2
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wait 2,0
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@ -393,4 +393,10 @@ Disassembly of section \.text:
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.*: (01 00 00 44|44 00 00 01) scv 0
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.*: (e1 0f 00 44|44 00 0f e1) scv 127
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.*: (a4 00 00 4c|4c 00 00 a4) rfscv
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.*: (7c 00 18 ac|ac 18 00 7c) dcbf 0,r3
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.*: (7c 00 18 ac|ac 18 00 7c) dcbf 0,r3
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.*: (7c 20 20 ac|ac 20 20 7c) dcbfl 0,r4
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.*: (7c 20 20 ac|ac 20 20 7c) dcbfl 0,r4
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.*: (7c 60 28 ac|ac 28 60 7c) dcbflp 0,r5
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.*: (7c 60 28 ac|ac 28 60 7c) dcbflp 0,r5
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#pass
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@ -384,3 +384,9 @@ power9:
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scv 0
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scv 127
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rfscv
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dcbf 0,3
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dcbf 0,3,0
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dcbfl 0,4
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dcbf 0,4,1
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dcbflp 0,5
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dcbf 0,5,3
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@ -1,3 +1,20 @@
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2020-05-19 Peter Bergner <bergner@linux.ibm.com>
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* ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
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WC values on POWER10 sync, dcbf and wait instructions.
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(insert_pl, extract_pl): New functions.
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(L2OPT, LS, WC): Use insert_ls and extract_ls.
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(LS3): New , 3-bit L for sync.
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(LS3, L3OPT): New, 3-bit L for sync and dcbf.
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(SC2, PL): New, 2-bit SC and PL for sync and wait.
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(XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
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(XOPL3, XWCPL, XSYNCLS): New opcode macros.
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(powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
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plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
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<wait>: Enable PL operand on POWER10.
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<dcbf>: Enable L3OPT operand on POWER10.
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<sync>: Enable SC2 operand on POWER10.
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2020-05-19 Stafford Horne <shorne@gmail.com>
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PR 25184
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@ -835,10 +835,16 @@ extract_li20 (uint64_t insn,
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| (insn & 0x7ff)) ^ 0x80000) - 0x80000;
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}
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/* The 2-bit L field in a SYNC or WC field in a WAIT instruction.
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/* The 2-bit/3-bit L or 2-bit WC field in a SYNC, DCBF or WAIT instruction.
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For SYNC, some L values are reserved:
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* Value 3 is reserved on newer server cpus.
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* Values 2 and 3 are reserved on all other cpus. */
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* Values 6 and 7 are reserved on newer server cpus.
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* Value 3 is reserved on all server cpus.
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* Value 2 is reserved on all other cpus.
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For DCBF, some L values are reserved:
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* Values 2, 5 and 7 are reserved on all cpus.
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For WAIT, some WC values are reserved:
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* Value 3 is reserved on all server cpus.
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* Values 1 and 2 are reserved on older server cpus. */
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static uint64_t
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insert_ls (uint64_t insn,
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@ -846,15 +852,73 @@ insert_ls (uint64_t insn,
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ppc_cpu_t dialect,
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const char **errmsg)
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{
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/* For SYNC, some L values are illegal. */
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int64_t mask;
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if (((insn >> 1) & 0x3ff) == 598)
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{
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int64_t max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1;
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if (value > max_lvalue)
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*errmsg = _("illegal L operand value");
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/* For SYNC, some L values are illegal. */
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mask = (dialect & PPC_OPCODE_POWER10) ? 0x7 : 0x3;
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/* If the value is within range, check for other illegal values. */
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if ((value & mask) == value)
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switch (value)
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{
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case 2:
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if (dialect & PPC_OPCODE_POWER4)
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break;
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/* Fall through. */
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case 3:
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case 6:
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case 7:
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*errmsg = _("illegal L operand value");
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break;
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default:
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break;
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}
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}
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else if (((insn >> 1) & 0x3ff) == 86)
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{
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/* For DCBF, some L values are illegal. */
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mask = (dialect & PPC_OPCODE_POWER10) ? 0x7 : 0x3;
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/* If the value is within range, check for other illegal values. */
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if ((value & mask) == value)
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switch (value)
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{
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case 2:
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case 5:
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case 7:
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*errmsg = _("illegal L operand value");
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break;
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default:
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break;
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}
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}
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else
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{
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/* For WAIT, some WC values are illegal. */
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mask = 0x3;
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/* If the value is within range, check for other illegal values. */
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if ((dialect & PPC_OPCODE_A2) == 0
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&& (dialect & PPC_OPCODE_E500MC) == 0
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&& (value & mask) == value)
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switch (value)
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{
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case 1:
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case 2:
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if (dialect & PPC_OPCODE_POWER10)
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break;
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/* Fall through. */
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case 3:
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*errmsg = _("illegal WC operand value");
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break;
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default:
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break;
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}
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}
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return insn | ((value & 0x3) << 21);
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return insn | ((value & mask) << 21);
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}
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static int64_t
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@ -862,18 +926,72 @@ extract_ls (uint64_t insn,
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ppc_cpu_t dialect,
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int *invalid)
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{
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uint64_t value;
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/* Missing optional operands have a value of zero. */
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if (*invalid < 0)
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return 0;
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uint64_t lvalue = (insn >> 21) & 3;
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if (((insn >> 1) & 0x3ff) == 598)
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{
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uint64_t max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1;
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if (lvalue > max_lvalue)
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*invalid = 1;
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/* For SYNC, some L values are illegal. */
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int64_t mask = (dialect & PPC_OPCODE_POWER10) ? 0x7 : 0x3;
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value = (insn >> 21) & mask;
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switch (value)
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{
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case 2:
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if (dialect & PPC_OPCODE_POWER4)
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break;
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/* Fall through. */
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case 3:
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case 6:
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case 7:
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*invalid = 1;
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break;
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default:
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break;
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}
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}
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return lvalue;
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else if (((insn >> 1) & 0x3ff) == 86)
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{
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/* For DCBF, some L values are illegal. */
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int64_t mask = (dialect & PPC_OPCODE_POWER10) ? 0x7 : 0x3;
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value = (insn >> 21) & mask;
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switch (value)
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{
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case 2:
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case 5:
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case 7:
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*invalid = 1;
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break;
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default:
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break;
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}
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}
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else
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{
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/* For WAIT, some WC values are illegal. */
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value = (insn >> 21) & 0x3;
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if ((dialect & PPC_OPCODE_A2) == 0
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&& (dialect & PPC_OPCODE_E500MC) == 0)
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switch (value)
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{
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case 1:
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case 2:
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if (dialect & PPC_OPCODE_POWER10)
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break;
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/* Fall through. */
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case 3:
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*invalid = 1;
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break;
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default:
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break;
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}
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}
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return value;
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}
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/* The 4-bit E field in a sync instruction that accepts 2 operands.
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@ -1079,6 +1197,41 @@ extract_nsi (uint64_t insn,
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return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
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}
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/* The 2-bit SC field in a SYNC or PL field in a WAIT instruction.
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For WAIT, some PL values are reserved:
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* Values 1, 2 and 3 are reserved. */
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static uint64_t
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insert_pl (uint64_t insn,
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int64_t value,
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ppc_cpu_t dialect ATTRIBUTE_UNUSED,
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const char **errmsg)
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{
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/* For WAIT, some PL values are illegal. */
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if (((insn >> 1) & 0x3ff) == 30
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&& value != 0)
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*errmsg = _("illegal PL operand value");
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return insn | ((value & 0x3) << 16);
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}
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static int64_t
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extract_pl (uint64_t insn,
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ppc_cpu_t dialect ATTRIBUTE_UNUSED,
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int *invalid)
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{
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/* Missing optional operands have a value of zero. */
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if (*invalid < 0)
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return 0;
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uint64_t value = (insn >> 16) & 0x3;
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/* For WAIT, some PL values are illegal. */
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if (((insn >> 1) & 0x3ff) == 30
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&& value != 0)
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*invalid = 1;
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return value;
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}
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/* The RA field in a D or X form instruction which is an updating
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load, which means that the RA field may not be zero and may not
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equal the RT field. */
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@ -2443,9 +2596,11 @@ const struct powerpc_operand powerpc_operands[] =
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#define L32OPT L1OPT + 1
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{ 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL32 },
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/* The L field in dcbf instruction. */
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/* The 2-bit L or WC field in an X (sync, dcbf or wait) form instruction. */
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#define L2OPT L32OPT + 1
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{ 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
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#define LS L2OPT
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#define WC L2OPT
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{ 0x3, 21, insert_ls, extract_ls, PPC_OPERAND_OPTIONAL },
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/* The LEV field in a POWER SVC / POWER9 SCV form instruction. */
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#define SVC_LEV L2OPT + 1
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@ -2465,13 +2620,13 @@ const struct powerpc_operand powerpc_operands[] =
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#define LIA LI + 1
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{ 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
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/* The LS or WC field in an X (sync or wait) form instruction. */
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#define LS LIA + 1
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#define WC LS
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{ 0x3, 21, insert_ls, extract_ls, PPC_OPERAND_OPTIONAL },
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/* The 3-bit L field in a sync or dcbf instruction. */
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#define LS3 LIA + 1
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#define L3OPT LS3
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{ 0x7, 21, insert_ls, extract_ls, PPC_OPERAND_OPTIONAL },
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|
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/* The ME field in an M form instruction. */
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#define ME LS + 1
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#define ME LS3 + 1
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#define ME_MASK (0x1f << 1)
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{ 0x1f, 1, NULL, NULL, 0 },
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|
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@ -3044,8 +3199,13 @@ const struct powerpc_operand powerpc_operands[] =
|
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#define IH ERAT_T + 1
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{ 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
|
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|
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/* The 2-bit SC or PL field in an X form instruction. */
|
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#define SC2 IH + 1
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#define PL SC2
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{ 0x3, 16, insert_pl, extract_pl, PPC_OPERAND_OPTIONAL },
|
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|
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/* The 8-bit IMM8 field in a XX1 form instruction. */
|
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#define IMM8 IH + 1
|
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#define IMM8 SC2 + 1
|
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{ 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT },
|
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|
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#define VX_OFF IMM8 + 1
|
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@ -3594,6 +3754,10 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
|
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field. */
|
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#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
|
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|
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/* An X form wait instruction with everything filled in except the WC
|
||||
and PL fields. */
|
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#define XWCPL_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | (3 << 18) | RB_MASK)
|
||||
|
||||
/* The mask for an XX1 form instruction. */
|
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#define XX1_MASK X (0x3f, 0x3ff)
|
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@ -3659,9 +3823,12 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
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/* An X_MASK with the RT field fixed. */
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#define XRT_MASK (X_MASK | RT_MASK)
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/* An XRT_MASK mask with the L bits clear. */
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/* An XRT_MASK mask with the 2 L bits clear. */
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#define XLRT_MASK (XRT_MASK & ~((uint64_t) 0x3 << 21))
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/* An XRT_MASK mask with the 3 L bits clear. */
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#define XL3RT_MASK (XRT_MASK & ~((uint64_t) 0x7 << 21))
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/* An X_MASK with the RA and RB fields fixed. */
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#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
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@ -3700,11 +3867,21 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
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(X ((op), (xop)) \
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| ((((uint64_t)(l)) & 1) << 21))
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||||
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/* An X form instruction with the L bits specified. */
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/* An X form instruction with the 2 L bits specified. */
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#define XOPL2(op, xop, l) \
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(X ((op), (xop)) \
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||||
| ((((uint64_t)(l)) & 3) << 21))
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||||
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/* An X form instruction with the 3 L bits specified. */
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#define XOPL3(op, xop, l) \
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||||
(X ((op), (xop)) \
|
||||
| ((((uint64_t)(l)) & 7) << 21))
|
||||
|
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/* An X form instruction with the WC and PL bits specified. */
|
||||
#define XWCPL(op, xop, wc, pl) \
|
||||
(XOPL3 ((op), (xop), (wc)) \
|
||||
| ((((uint64_t)(pl)) & 3) << 16))
|
||||
|
||||
/* An X form instruction with the L bit and RC bit specified. */
|
||||
#define XRCL(op, xop, l, rc) \
|
||||
(XRC ((op), (xop), (rc)) \
|
||||
@ -3753,6 +3930,16 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
|
||||
and E fields. */
|
||||
#define XSYNCLE_MASK (0xff90ffff)
|
||||
|
||||
/* An X form sync instruction. */
|
||||
#define XSYNCLS(op, xop, l, s) \
|
||||
(X ((op), (xop)) \
|
||||
| ((((uint64_t)(l)) & 7) << 21) \
|
||||
| ((((uint64_t)(s)) & 3) << 16))
|
||||
|
||||
/* An X form sync instruction with everything filled in except the
|
||||
L and SC fields. */
|
||||
#define XSYNCLS_MASK (0xff1cffff)
|
||||
|
||||
/* An X_MASK, but with the EH bit clear. */
|
||||
#define XEH_MASK (X_MASK & ~((uint64_t )1))
|
||||
|
||||
@ -6076,7 +6263,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
||||
{"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
|
||||
|
||||
{"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}},
|
||||
{"wait", X(31,30), XWC_MASK, POWER9, 0, {WC}},
|
||||
{"waitrsv", XWCPL(31,30,1,0),0xffffffff, POWER10, 0, {0}},
|
||||
{"pause_short", XWCPL(31,30,2,0),0xffffffff, POWER10, 0, {0}},
|
||||
{"wait", X(31,30), XWCPL_MASK, POWER10, 0, {WC, PL}},
|
||||
{"wait", X(31,30), XWC_MASK, POWER9, POWER10, {WC}},
|
||||
|
||||
{"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
|
||||
|
||||
@ -6174,7 +6364,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
||||
{"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}},
|
||||
|
||||
{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}},
|
||||
{"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}},
|
||||
{"dcbflp", XOPL2(31,86,3), XRT_MASK, POWER9, PPC476, {RA0, RB}},
|
||||
{"dcbfps", XOPL3(31,86,4), XRT_MASK, POWER10, PPC476, {RA0, RB}},
|
||||
{"dcbstps", XOPL3(31,86,6), XRT_MASK, POWER10, PPC476, {RA0, RB}},
|
||||
{"dcbf", X(31,86), XL3RT_MASK, POWER10, PPC476, {RA0, RB, L3OPT}},
|
||||
{"dcbf", X(31,86), XLRT_MASK, PPC, POWER10, {RA0, RB, L2OPT}},
|
||||
|
||||
{"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
|
||||
|
||||
@ -7243,8 +7437,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
||||
{"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}},
|
||||
{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
|
||||
{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, 0, {0}},
|
||||
{"phwsync", XSYNCLS(31,598,4,0), 0xffffffff, POWER10, 0, {0}},
|
||||
{"plwsync", XSYNCLS(31,598,5,0), 0xffffffff, POWER10, 0, {0}},
|
||||
{"stncisync", XSYNCLS(31,598,1,1), 0xffffffff, POWER10, 0, {0}},
|
||||
{"stcisync", XSYNCLS(31,598,0,2), 0xffffffff, POWER10, 0, {0}},
|
||||
{"stsync", XSYNCLS(31,598,0,3), 0xffffffff, POWER10, 0, {0}},
|
||||
{"sync", X(31,598), XSYNCLS_MASK, POWER10, BOOKE|PPC476, {LS3, SC2}},
|
||||
{"sync", X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}},
|
||||
{"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}},
|
||||
{"sync", X(31,598), XSYNC_MASK, PPCCOM, POWER10|BOOKE|PPC476, {LS}},
|
||||
{"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}},
|
||||
{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}},
|
||||
{"lwsync", X(31,598), 0xffffffff, E500, 0, {0}},
|
||||
|
||||
Loading…
Reference in New Issue
Block a user