* rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
operands, so that data addresses can be corrected when not ES-overridden. * rl78-decode.c: Regenerate. * rl78-dis.c (print_insn_rl78): Make order of modifiers irrelevent. When the 'e' specifier is used on an operand and no ES prefix is provided, adjust address to make it absolute.
This commit is contained in:
DJ Delorie
parent
588925d065
commit
3d557b4cce
@ -1,3 +1,13 @@
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2012-08-15 DJ Delorie <dj@redhat.com>
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* rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
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operands, so that data addresses can be corrected when not
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ES-overridden.
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* rl78-decode.c: Regenerate.
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* rl78-dis.c (print_insn_rl78): Make order of modifiers
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irrelevent. When the 'e' specifier is used on an operand and no
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ES prefix is provided, adjust address to make it absolute.
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2012-08-15 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR.
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@ -175,19 +175,19 @@ rl78_decode_opcode (unsigned long pc AU,
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/*----------------------------------------------------------------------*/
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/** 0000 1111 add %0, %e1%!1 */
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/** 0000 1111 add %0, %e!1 */
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ID(add); DR(A); SM(None, IMMU(2)); Fzac;
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/** 0000 1101 add %0, %e1%1 */
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/** 0000 1101 add %0, %e1 */
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ID(add); DR(A); SM(HL, 0); Fzac;
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/** 0110 0001 1000 000 add %0, %e1%1 */
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/** 0110 0001 1000 000 add %0, %e1 */
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ID(add); DR(A); SM2(HL, B, 0); Fzac;
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/** 0000 1110 add %0, %e1%1 */
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/** 0000 1110 add %0, %e1 */
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ID(add); DR(A); SM(HL, IMMU(1)); Fzac;
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/** 0110 0001 1000 0010 add %0, %e1%1 */
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/** 0110 0001 1000 0010 add %0, %e1 */
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ID(add); DR(A); SM2(HL, C, 0); Fzac;
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/** 0000 1100 add %0, #%1 */
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@ -207,19 +207,19 @@ rl78_decode_opcode (unsigned long pc AU,
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/*----------------------------------------------------------------------*/
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/** 0001 1111 addc %0, %e1%!1 */
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/** 0001 1111 addc %0, %e!1 */
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ID(addc); DR(A); SM(None, IMMU(2)); Fzac;
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/** 0001 1101 addc %0, %e1%1 */
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/** 0001 1101 addc %0, %e1 */
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ID(addc); DR(A); SM(HL, 0); Fzac;
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/** 0110 0001 1001 0000 addc %0, %e1%1 */
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/** 0110 0001 1001 0000 addc %0, %e1 */
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ID(addc); DR(A); SM2(HL, B, 0); Fzac;
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/** 0110 0001 1001 0010 addc %0, %e1%1 */
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/** 0110 0001 1001 0010 addc %0, %e1 */
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ID(addc); DR(A); SM2(HL, C, 0); Fzac;
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/** 0001 1110 addc %0, %e1%1 */
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/** 0001 1110 addc %0, %e1 */
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ID(addc); DR(A); SM(HL, IMMU(1)); Fzac;
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/** 0001 1100 addc %0, #%1 */
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@ -239,10 +239,10 @@ rl78_decode_opcode (unsigned long pc AU,
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/*----------------------------------------------------------------------*/
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/** 0000 0010 addw %0, %e1%!1 */
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/** 0000 0010 addw %0, %e!1 */
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ID(add); W(); DR(AX); SM(None, IMMU(2)); Fzac;
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/** 0110 0001 0000 1001 addw %0, %e1%1 */
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/** 0110 0001 0000 1001 addw %0, %e1 */
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ID(add); W(); DR(AX); SM(HL, IMMU(1)); Fzac;
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/** 0000 0100 addw %0, #%1 */
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@ -259,19 +259,19 @@ rl78_decode_opcode (unsigned long pc AU,
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/*----------------------------------------------------------------------*/
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/** 0101 1111 and %0, %e1%!1 */
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/** 0101 1111 and %0, %e!1 */
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ID(and); DR(A); SM(None, IMMU(2)); Fz;
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/** 0101 1101 and %0, %e1%1 */
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/** 0101 1101 and %0, %e1 */
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ID(and); DR(A); SM(HL, 0); Fz;
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/** 0110 0001 1101 0000 and %0, %e1%1 */
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/** 0110 0001 1101 0000 and %0, %e1 */
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ID(and); DR(A); SM2(HL, B, 0); Fz;
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/** 0101 1110 and %0, %e1%1 */
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/** 0101 1110 and %0, %e1 */
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ID(and); DR(A); SM(HL, IMMU(1)); Fz;
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/** 0110 0001 1101 0010 and %0, %e1%1 */
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/** 0110 0001 1101 0010 and %0, %e1 */
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ID(and); DR(A); SM2(HL, C, 0); Fz;
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/** 0101 1100 and %0, #%1 */
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@ -291,7 +291,7 @@ rl78_decode_opcode (unsigned long pc AU,
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/*----------------------------------------------------------------------*/
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/** 0111 0001 1bit 0101 and1 cy, %e1%1 */
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/** 0111 0001 1bit 0101 and1 cy, %e1 */
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ID(and); DCY(); SM(HL, 0); SB(bit);
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/** 0111 0001 1bit 1101 and1 cy, %1 */
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@ -328,7 +328,7 @@ rl78_decode_opcode (unsigned long pc AU,
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/*----------------------------------------------------------------------*/
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/** 0011 0001 1bit 0101 bf %e1%1, $%a0 */
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/** 0011 0001 1bit 0101 bf %e1, $%a0 */
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ID(branch_cond); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(F);
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/** 0011 0001 0bit 0101 bf %1, $%a0 */
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@ -367,7 +367,7 @@ rl78_decode_opcode (unsigned long pc AU,
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/*----------------------------------------------------------------------*/
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/** 0011 0001 1bit 0011 bt %e1%1, $%a0 */
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/** 0011 0001 1bit 0011 bt %e1, $%a0 */
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ID(branch_cond); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(T);
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/** 0011 0001 0bit 0011 bt %1, $%a0 */
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@ -381,7 +381,7 @@ rl78_decode_opcode (unsigned long pc AU,
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/*----------------------------------------------------------------------*/
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/** 0011 0001 1bit 0001 btclr %e1%1, $%a0 */
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/** 0011 0001 1bit 0001 btclr %e1, $%a0 */
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ID(branch_cond_clear); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(T);
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/** 0011 0001 0bit 0001 btclr %1, $%a0 */
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@ -412,10 +412,10 @@ rl78_decode_opcode (unsigned long pc AU,
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/*----------------------------------------------------------------------*/
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/** 0111 0001 0bit 1000 clr1 %e0%!0 */
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/** 0111 0001 0bit 1000 clr1 %e!0 */
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ID(mov); DM(None, IMMU(2)); DB(bit); SC(0);
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/** 0111 0001 1bit 0011 clr1 %e0%0 */
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/** 0111 0001 1bit 0011 clr1 %e0 */
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ID(mov); DM(HL, 0); DB(bit); SC(0);
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/** 0111 0001 1bit 1011 clr1 %0 */
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@ -435,7 +435,7 @@ rl78_decode_opcode (unsigned long pc AU,
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/*----------------------------------------------------------------------*/
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/** 1111 0101 clrb %e0%!0 */
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/** 1111 0101 clrb %e!0 */
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ID(mov); DM(None, IMMU(2)); SC(0);
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/** 1111 00rg clrb %0 */
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@ -454,25 +454,25 @@ rl78_decode_opcode (unsigned long pc AU,
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/*----------------------------------------------------------------------*/
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/** 0100 0000 cmp %e0%!0, #%1 */
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/** 0100 0000 cmp %e!0, #%1 */
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ID(cmp); DM(None, IMMU(2)); SC(IMMU(1)); Fzac;
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/** 0100 1010 cmp %0, #%1 */
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ID(cmp); DM(None, SADDR); SC(IMMU(1)); Fzac;
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/** 0100 1111 cmp %0, %e1%!1 */
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/** 0100 1111 cmp %0, %e!1 */
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ID(cmp); DR(A); SM(None, IMMU(2)); Fzac;
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/** 0100 1101 cmp %0, %e1%1 */
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/** 0100 1101 cmp %0, %e1 */
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ID(cmp); DR(A); SM(HL, 0); Fzac;
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/** 0110 0001 1100 0000 cmp %0, %e1%1 */
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/** 0110 0001 1100 0000 cmp %0, %e1 */
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ID(cmp); DR(A); SM2(HL, B, 0); Fzac;
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/** 0110 0001 1100 0010 cmp %0, %e1%1 */
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/** 0110 0001 1100 0010 cmp %0, %e1 */
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ID(cmp); DR(A); SM2(HL, C, 0); Fzac;
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/** 0100 1110 cmp %0, %e1%1 */
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/** 0100 1110 cmp %0, %e1 */
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ID(cmp); DR(A); SM(HL, IMMU(1)); Fzac;
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/** 0100 1100 cmp %0, #%1 */
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@ -489,7 +489,7 @@ rl78_decode_opcode (unsigned long pc AU,
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/*----------------------------------------------------------------------*/
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/** 1101 0101 cmp0 %e0%!0 */
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/** 1101 0101 cmp0 %e!0 */
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ID(cmp); DM(None, IMMU(2)); SC(0); Fzac;
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/** 1101 00rg cmp0 %0 */
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@ -500,15 +500,15 @@ rl78_decode_opcode (unsigned long pc AU,
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/*----------------------------------------------------------------------*/
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/** 0110 0001 1101 1110 cmps %0, %e1%1 */
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/** 0110 0001 1101 1110 cmps %0, %e1 */
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ID(cmp); DR(X); SM(HL, IMMU(1)); Fzac;
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/*----------------------------------------------------------------------*/
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/** 0100 0010 cmpw %0, %e1%!1 */
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/** 0100 0010 cmpw %0, %e!1 */
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ID(cmp); W(); DR(AX); SM(None, IMMU(2)); Fzac;
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/** 0110 0001 0100 1001 cmpw %0, %e1%1 */
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/** 0110 0001 0100 1001 cmpw %0, %e1 */
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ID(cmp); W(); DR(AX); SM(HL, IMMU(1)); Fzac;
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/** 0100 0100 cmpw %0, #%1 */
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@ -522,10 +522,10 @@ rl78_decode_opcode (unsigned long pc AU,
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/*----------------------------------------------------------------------*/
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/** 1011 0000 dec %e0%!0 */
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/** 1011 0000 dec %e!0 */
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ID(sub); DM(None, IMMU(2)); SC(1); Fza;
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/** 0110 0001 0110 1001 dec %e0%0 */
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/** 0110 0001 0110 1001 dec %e0 */
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ID(sub); DM(HL, IMMU(1)); SC(1); Fza;
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/** 1001 0reg dec %0 */
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@ -536,10 +536,10 @@ rl78_decode_opcode (unsigned long pc AU,
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/*----------------------------------------------------------------------*/
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/** 1011 0010 decw %e0%!0 */
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/** 1011 0010 decw %e!0 */
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ID(sub); W(); DM(None, IMMU(2)); SC(1);
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/** 0110 0001 1000 1001 decw %e0%0 */
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/** 0110 0001 1000 1001 decw %e0 */
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ID(sub); W(); DM(HL, IMMU(1)); SC(1);
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/** 1011 0rg1 decw %0 */
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@ -555,10 +555,10 @@ rl78_decode_opcode (unsigned long pc AU,
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/*----------------------------------------------------------------------*/
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/** 1010 0000 inc %e0%!0 */
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/** 1010 0000 inc %e!0 */
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ID(add); DM(None, IMMU(2)); SC(1); Fza;
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/** 0110 0001 0101 1001 inc %e0%0 */
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/** 0110 0001 0101 1001 inc %e0 */
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ID(add); DM(HL, IMMU(1)); SC(1); Fza;
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/** 1000 0reg inc %0 */
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@ -569,10 +569,10 @@ rl78_decode_opcode (unsigned long pc AU,
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/*----------------------------------------------------------------------*/
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/** 1010 0010 incw %e0%!0 */
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/** 1010 0010 incw %e!0 */
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ID(add); W(); DM(None, IMMU(2)); SC(1);
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/** 0110 0001 0111 1001 incw %e0%0 */
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/** 0110 0001 0111 1001 incw %e0 */
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ID(add); W(); DM(HL, IMMU(1)); SC(1);
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/** 1010 0rg1 incw %0 */
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@ -583,34 +583,34 @@ rl78_decode_opcode (unsigned long pc AU,
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/*----------------------------------------------------------------------*/
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/** 1100 1111 mov %e0%!0, #%1 */
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/** 1100 1111 mov %e!0, #%1 */
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ID(mov); DM(None, IMMU(2)); SC(IMMU(1));
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/** 1001 1111 mov %e0%!0, %1 */
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/** 1001 1111 mov %e!0, %1 */
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ID(mov); DM(None, IMMU(2)); SR(A);
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/** 1001 1001 mov %e0%0,%1 */
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/** 1001 1001 mov %e0,%1 */
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ID(mov); DM(DE, 0); SR(A);
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/** 1100 1010 mov %e0%0, #%1 */
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/** 1100 1010 mov %e0, #%1 */
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ID(mov); DM(DE, IMMU(1)); SC(IMMU(1));
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/** 1001 1010 mov %e0%0, %1 */
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/** 1001 1010 mov %e0, %1 */
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ID(mov); DM(DE, IMMU(1)); SR(A);
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/** 1001 1011 mov %e0%0,%1 */
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/** 1001 1011 mov %e0,%1 */
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ID(mov); DM(HL, 0); SR(A);
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/** 0110 0001 1101 1001 mov %e0%0, %1 */
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/** 0110 0001 1101 1001 mov %e0, %1 */
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ID(mov); DM2(HL, B, 0); SR(A);
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/** 1100 1100 mov %e0%0, #%1 */
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/** 1100 1100 mov %e0, #%1 */
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ID(mov); DM(HL, IMMU(1)); SC(IMMU(1));
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/** 1001 1100 mov %e0%0, %1 */
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/** 1001 1100 mov %e0, %1 */
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ID(mov); DM(HL, IMMU(1)); SR(A);
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/** 0110 0001 1111 1001 mov %e0%0, %1 */
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/** 0110 0001 1111 1001 mov %e0, %1 */
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ID(mov); DM2(HL, C, 0); SR(A);
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/** 1100 1000 mov %0, #%1 */
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@ -619,28 +619,28 @@ rl78_decode_opcode (unsigned long pc AU,
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/** 1001 1000 mov %0, %1 */
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ID(mov); DM(SP, IMMU(1)); SR(A);
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/** 1000 1111 mov %0, %e1%!1 */
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/** 1000 1111 mov %0, %e!1 */
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ID(mov); DR(A); SM(None, IMMU(2));
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/** 1000 1001 mov %0, %e1%1 */
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/** 1000 1001 mov %0, %e1 */
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ID(mov); DR(A); SM(DE, 0);
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/** 1000 1010 mov %0, %e1%1 */
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/** 1000 1010 mov %0, %e1 */
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ID(mov); DR(A); SM(DE, IMMU(1));
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/** 1000 1011 mov %0, %e1%1 */
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/** 1000 1011 mov %0, %e1 */
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ID(mov); DR(A); SM(HL, 0);
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/** 1000 1100 mov %0, %e1%1 */
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/** 1000 1100 mov %0, %e1 */
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ID(mov); DR(A); SM(HL, IMMU(1));
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/** 0110 0001 1100 1001 mov %0, %e1%1 */
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/** 0110 0001 1100 1001 mov %0, %e1 */
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ID(mov); DR(A); SM2(HL, B, 0);
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/** 0110 0001 1110 1001 mov %0, %e1%1 */
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/** 0110 0001 1110 1001 mov %0, %e1 */
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ID(mov); DR(A); SM2(HL, C, 0);
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/** 1000 1000 mov %0, %e1%1 */
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/** 1000 1000 mov %0, %e1 */
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ID(mov); DR(A); SM(SP, IMMU(1));
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/** 0101 0reg mov %0, #%1 */
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@ -652,13 +652,13 @@ rl78_decode_opcode (unsigned long pc AU,
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/** 1000 1110 1111 1101 mov %0, %1 */
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ID(mov); DR(A); SR(ES);
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/** 0000 1001 mov %0, %e1%1 */
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/** 0000 1001 mov %0, %e1 */
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ID(mov); DR(A); SM(B, IMMU(2));
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/** 0100 1001 mov %0, %e1%1 */
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/** 0100 1001 mov %0, %e1 */
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ID(mov); DR(A); SM(BC, IMMU(2));
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/** 0010 1001 mov %0, %e1%1 */
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/** 0010 1001 mov %0, %e1 */
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ID(mov); DR(A); SM(C, IMMU(2));
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/** 1000 1110 mov %0, %s1 */
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@ -667,7 +667,7 @@ rl78_decode_opcode (unsigned long pc AU,
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/** 1000 1101 mov %0, %1 */
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ID(mov); DR(A); SM(None, SADDR);
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/** 1110 1001 mov %0, %e1%!1 */
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/** 1110 1001 mov %0, %e!1 */
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ID(mov); DR(B); SM(None, IMMU(2));
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/** 0111 0rba mov %0, %1 */
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@ -676,13 +676,13 @@ rl78_decode_opcode (unsigned long pc AU,
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/** 1110 1000 mov %0, %1 */
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ID(mov); DR(B); SM(None, SADDR);
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/** 1111 1001 mov %0, %e1%!1 */
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/** 1111 1001 mov %0, %e!1 */
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ID(mov); DR(C); SM(None, IMMU(2));
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/** 1111 1000 mov %0, %1 */
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ID(mov); DR(C); SM(None, SADDR);
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/** 1101 1001 mov %0, %e1%!1 */
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/** 1101 1001 mov %0, %e!1 */
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ID(mov); DR(X); SM(None, IMMU(2));
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/** 1101 1000 mov %0, %1 */
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@ -700,22 +700,22 @@ rl78_decode_opcode (unsigned long pc AU,
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/** 0110 0001 1011 1000 mov %0, %1 */
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ID(mov); DR(ES); SM(None, SADDR);
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|
||||
/** 0001 1001 mov %e0%0, #%1 */
|
||||
/** 0001 1001 mov %e0, #%1 */
|
||||
ID(mov); DM(B, IMMU(2)); SC(IMMU(1));
|
||||
|
||||
/** 0001 1000 mov %e0%0, %1 */
|
||||
/** 0001 1000 mov %e0, %1 */
|
||||
ID(mov); DM(B, IMMU(2)); SR(A);
|
||||
|
||||
/** 0011 1001 mov %e0%0, #%1 */
|
||||
/** 0011 1001 mov %e0, #%1 */
|
||||
ID(mov); DM(BC, IMMU(2)); SC(IMMU(1));
|
||||
|
||||
/** 0100 1000 mov %e0%0, %1 */
|
||||
/** 0100 1000 mov %e0, %1 */
|
||||
ID(mov); DM(BC, IMMU(2)); SR(A);
|
||||
|
||||
/** 0011 1000 mov %e0%0, #%1 */
|
||||
/** 0011 1000 mov %e0, #%1 */
|
||||
ID(mov); DM(C, IMMU(2)); SC(IMMU(1));
|
||||
|
||||
/** 0010 1000 mov %e0%0, %1 */
|
||||
/** 0010 1000 mov %e0, %1 */
|
||||
ID(mov); DM(C, IMMU(2)); SR(A);
|
||||
|
||||
/** 1100 1101 mov %0, #%1 */
|
||||
@ -756,16 +756,16 @@ rl78_decode_opcode (unsigned long pc AU,
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
/** 0111 0001 1bit 0001 mov1 %e0%0, cy */
|
||||
/** 0111 0001 1bit 0001 mov1 %e0, cy */
|
||||
ID(mov); DM(HL, 0); DB(bit); SCY();
|
||||
|
||||
/** 0111 0001 1bit 1001 mov1 %e0%0, cy */
|
||||
/** 0111 0001 1bit 1001 mov1 %e0, cy */
|
||||
ID(mov); DR(A); DB(bit); SCY();
|
||||
|
||||
/** 0111 0001 1bit 0100 mov1 cy, %e1%1 */
|
||||
/** 0111 0001 1bit 0100 mov1 cy, %e1 */
|
||||
ID(mov); DCY(); SM(HL, 0); SB(bit);
|
||||
|
||||
/** 0111 0001 1bit 1100 mov1 cy, %e1%1 */
|
||||
/** 0111 0001 1bit 1100 mov1 cy, %e1 */
|
||||
ID(mov); DCY(); SR(A); SB(bit);
|
||||
|
||||
/** 0111 0001 0bit 0100 mov1 cy, %1 */
|
||||
@ -782,43 +782,43 @@ rl78_decode_opcode (unsigned long pc AU,
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
/** 0110 0001 1100 1110 movs %e0%0, %1 */
|
||||
/** 0110 0001 1100 1110 movs %e0, %1 */
|
||||
ID(mov); DM(HL, IMMU(1)); SR(X); Fzc;
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
/** 1011 1111 movw %e0%!0, %1 */
|
||||
/** 1011 1111 movw %e!0, %1 */
|
||||
ID(mov); W(); DM(None, IMMU(2)); SR(AX);
|
||||
|
||||
/** 1011 1001 movw %e0%0, %1 */
|
||||
/** 1011 1001 movw %e0, %1 */
|
||||
ID(mov); W(); DM(DE, 0); SR(AX);
|
||||
|
||||
/** 1011 1010 movw %e0%0, %1 */
|
||||
/** 1011 1010 movw %e0, %1 */
|
||||
ID(mov); W(); DM(DE, IMMU(1)); SR(AX);
|
||||
|
||||
/** 1011 1011 movw %e0%0, %1 */
|
||||
/** 1011 1011 movw %e0, %1 */
|
||||
ID(mov); W(); DM(HL, 0); SR(AX);
|
||||
|
||||
/** 1011 1100 movw %e0%0, %1 */
|
||||
/** 1011 1100 movw %e0, %1 */
|
||||
ID(mov); W(); DM(HL, IMMU(1)); SR(AX);
|
||||
|
||||
/** 1011 1000 movw %0, %1 */
|
||||
ID(mov); W(); DM(SP, IMMU(1)); SR(AX);
|
||||
|
||||
/** 1010 1111 movw %0, %e1%!1 */
|
||||
/** 1010 1111 movw %0, %e!1 */
|
||||
ID(mov); W(); DR(AX); SM(None, IMMU(2));
|
||||
|
||||
|
||||
/** 1010 1001 movw %0, %e1%1 */
|
||||
/** 1010 1001 movw %0, %e1 */
|
||||
ID(mov); W(); DR(AX); SM(DE, 0);
|
||||
|
||||
/** 1010 1010 movw %0, %e1%1 */
|
||||
/** 1010 1010 movw %0, %e1 */
|
||||
ID(mov); W(); DR(AX); SM(DE, IMMU(1));
|
||||
|
||||
/** 1010 1011 movw %0, %e1%1 */
|
||||
/** 1010 1011 movw %0, %e1 */
|
||||
ID(mov); W(); DR(AX); SM(HL, 0);
|
||||
|
||||
/** 1010 1100 movw %0, %e1%1 */
|
||||
/** 1010 1100 movw %0, %e1 */
|
||||
ID(mov); W(); DR(AX); SM(HL, IMMU(1));
|
||||
|
||||
/** 1010 1000 movw %0, %1 */
|
||||
@ -833,22 +833,22 @@ rl78_decode_opcode (unsigned long pc AU,
|
||||
/** 0001 0ra0 movw %0, %1 */
|
||||
ID(mov); W(); DRW(ra); SR(AX);
|
||||
|
||||
/** 0101 1001 movw %0, %e1%1 */
|
||||
/** 0101 1001 movw %0, %e1 */
|
||||
ID(mov); W(); DR(AX); SM(B, IMMU(2));
|
||||
|
||||
/** 0110 1001 movw %0, %e1%1 */
|
||||
/** 0110 1001 movw %0, %e1 */
|
||||
ID(mov); W(); DR(AX); SM(C, IMMU(2));
|
||||
|
||||
/** 0111 1001 movw %0, %e1%1 */
|
||||
/** 0111 1001 movw %0, %e1 */
|
||||
ID(mov); W(); DR(AX); SM(BC, IMMU(2));
|
||||
|
||||
/** 0101 1000 movw %e0%0, %1 */
|
||||
/** 0101 1000 movw %e0, %1 */
|
||||
ID(mov); W(); DM(B, IMMU(2)); SR(AX);
|
||||
|
||||
/** 0110 1000 movw %e0%0, %1 */
|
||||
/** 0110 1000 movw %e0, %1 */
|
||||
ID(mov); W(); DM(C, IMMU(2)); SR(AX);
|
||||
|
||||
/** 0111 1000 movw %e0%0, %1 */
|
||||
/** 0111 1000 movw %e0, %1 */
|
||||
ID(mov); W(); DM(BC, IMMU(2)); SR(AX);
|
||||
|
||||
/** 1010 1101 movw %0, %1 */
|
||||
@ -857,7 +857,7 @@ rl78_decode_opcode (unsigned long pc AU,
|
||||
/** 1010 1110 movw %0, %s1 */
|
||||
ID(mov); W(); DR(AX); SM(None, SFR);
|
||||
|
||||
/** 11ra 1011 movw %0, %e1%!1 */
|
||||
/** 11ra 1011 movw %0, %e!1 */
|
||||
ID(mov); W(); DRW(ra); SM(None, IMMU(2));
|
||||
|
||||
/** 11ra 1010 movw %0, %1 */
|
||||
@ -892,7 +892,7 @@ rl78_decode_opcode (unsigned long pc AU,
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
/** 1110 0101 oneb %e0%!0 */
|
||||
/** 1110 0101 oneb %e!0 */
|
||||
ID(mov); DM(None, IMMU(2)); SC(1);
|
||||
|
||||
/** 1110 00rg oneb %0 */
|
||||
@ -911,19 +911,19 @@ rl78_decode_opcode (unsigned long pc AU,
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
/** 0110 1111 or %0, %e1%!1 */
|
||||
/** 0110 1111 or %0, %e!1 */
|
||||
ID(or); DR(A); SM(None, IMMU(2)); Fz;
|
||||
|
||||
/** 0110 1101 or %0, %e1%1 */
|
||||
/** 0110 1101 or %0, %e1 */
|
||||
ID(or); DR(A); SM(HL, 0); Fz;
|
||||
|
||||
/** 0110 0001 1110 0000 or %0, %e1%1 */
|
||||
/** 0110 0001 1110 0000 or %0, %e1 */
|
||||
ID(or); DR(A); SM2(HL, B, 0); Fz;
|
||||
|
||||
/** 0110 1110 or %0, %e1%1 */
|
||||
/** 0110 1110 or %0, %e1 */
|
||||
ID(or); DR(A); SM(HL, IMMU(1)); Fz;
|
||||
|
||||
/** 0110 0001 1110 0010 or %0, %e1%1 */
|
||||
/** 0110 0001 1110 0010 or %0, %e1 */
|
||||
ID(or); DR(A); SM2(HL, C, 0); Fz;
|
||||
|
||||
/** 0110 1100 or %0, #%1 */
|
||||
@ -943,7 +943,7 @@ rl78_decode_opcode (unsigned long pc AU,
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
/** 0111 0001 1bit 0110 or1 cy, %e1%1 */
|
||||
/** 0111 0001 1bit 0110 or1 cy, %e1 */
|
||||
ID(or); DCY(); SM(HL, 0); SB(bit);
|
||||
|
||||
/** 0111 0001 1bit 1110 or1 cy, %1 */
|
||||
@ -1017,10 +1017,10 @@ rl78_decode_opcode (unsigned long pc AU,
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
/** 0111 0001 0bit 0000 set1 %e0%!0 */
|
||||
/** 0111 0001 0bit 0000 set1 %e!0 */
|
||||
ID(mov); DM(None, IMMU(2)); DB(bit); SC(1);
|
||||
|
||||
/** 0111 0001 1bit 0010 set1 %e0%0 */
|
||||
/** 0111 0001 1bit 0010 set1 %e0 */
|
||||
ID(mov); DM(HL, 0); DB(bit); SC(1);
|
||||
|
||||
/** 0111 0001 1bit 1010 set1 %0 */
|
||||
@ -1085,24 +1085,24 @@ rl78_decode_opcode (unsigned long pc AU,
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
/** 0110 0001 1111 1101 stop */
|
||||
/** 0110 0001 1111 1101 stop */
|
||||
ID(stop);
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
/** 0010 1111 sub %0, %e1%!1 */
|
||||
/** 0010 1111 sub %0, %e!1 */
|
||||
ID(sub); DR(A); SM(None, IMMU(2)); Fzac;
|
||||
|
||||
/** 0010 1101 sub %0, %e1%1 */
|
||||
/** 0010 1101 sub %0, %e1 */
|
||||
ID(sub); DR(A); SM(HL, 0); Fzac;
|
||||
|
||||
/** 0110 0001 1010 000 sub %0, %e1%1 */
|
||||
/** 0110 0001 1010 000 sub %0, %e1 */
|
||||
ID(sub); DR(A); SM2(HL, B, 0); Fzac;
|
||||
|
||||
/** 0010 1110 sub %0, %e1%1 */
|
||||
/** 0010 1110 sub %0, %e1 */
|
||||
ID(sub); DR(A); SM(HL, IMMU(1)); Fzac;
|
||||
|
||||
/** 0110 0001 1010 0010 sub %0, %e1%1 */
|
||||
/** 0110 0001 1010 0010 sub %0, %e1 */
|
||||
ID(sub); DR(A); SM2(HL, C, 0); Fzac;
|
||||
|
||||
/** 0010 1100 sub %0, #%1 */
|
||||
@ -1122,19 +1122,19 @@ rl78_decode_opcode (unsigned long pc AU,
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
/** 0011 1111 subc %0, %e1%!1 */
|
||||
/** 0011 1111 subc %0, %e!1 */
|
||||
ID(subc); DR(A); SM(None, IMMU(2)); Fzac;
|
||||
|
||||
/** 0011 1101 subc %0, %e1%1 */
|
||||
/** 0011 1101 subc %0, %e1 */
|
||||
ID(subc); DR(A); SM(HL, 0); Fzac;
|
||||
|
||||
/** 0110 0001 1011 0000 subc %0, %e1%1 */
|
||||
/** 0110 0001 1011 0000 subc %0, %e1 */
|
||||
ID(subc); DR(A); SM2(HL, B, 0); Fzac;
|
||||
|
||||
/** 0110 0001 1011 0010 subc %0, %e1%1 */
|
||||
/** 0110 0001 1011 0010 subc %0, %e1 */
|
||||
ID(subc); DR(A); SM2(HL, C, 0); Fzac;
|
||||
|
||||
/** 0011 1110 subc %0, %e1%1 */
|
||||
/** 0011 1110 subc %0, %e1 */
|
||||
ID(subc); DR(A); SM(HL, IMMU(1)); Fzac;
|
||||
|
||||
/** 0011 1100 subc %0, #%1 */
|
||||
@ -1154,10 +1154,10 @@ rl78_decode_opcode (unsigned long pc AU,
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
/** 0010 0010 subw %0, %e1%!1 */
|
||||
/** 0010 0010 subw %0, %e!1 */
|
||||
ID(sub); W(); DR(AX); SM(None, IMMU(2)); Fzac;
|
||||
|
||||
/** 0110 0001 0010 1001 subw %0, %e1%1 */
|
||||
/** 0110 0001 0010 1001 subw %0, %e1 */
|
||||
ID(sub); W(); DR(AX); SM(HL, IMMU(1)); Fzac;
|
||||
|
||||
/** 0010 0100 subw %0, #%1 */
|
||||
@ -1174,25 +1174,25 @@ rl78_decode_opcode (unsigned long pc AU,
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
/** 0110 0001 1010 1010 xch %0, %e1%!1 */
|
||||
/** 0110 0001 1010 1010 xch %0, %e!1 */
|
||||
ID(xch); DR(A); SM(None, IMMU(2));
|
||||
|
||||
/** 0110 0001 1010 1110 xch %0, %e1%1 */
|
||||
/** 0110 0001 1010 1110 xch %0, %e1 */
|
||||
ID(xch); DR(A); SM(DE, 0);
|
||||
|
||||
/** 0110 0001 1010 1111 xch %0, %e1%1 */
|
||||
/** 0110 0001 1010 1111 xch %0, %e1 */
|
||||
ID(xch); DR(A); SM(DE, IMMU(1));
|
||||
|
||||
/** 0110 0001 1010 1100 xch %0, %e1%1 */
|
||||
/** 0110 0001 1010 1100 xch %0, %e1 */
|
||||
ID(xch); DR(A); SM(HL, 0);
|
||||
|
||||
/** 0110 0001 1011 1001 xch %0, %e1%1 */
|
||||
/** 0110 0001 1011 1001 xch %0, %e1 */
|
||||
ID(xch); DR(A); SM2(HL, B, 0);
|
||||
|
||||
/** 0110 0001 1010 1101 xch %0, %e1%1 */
|
||||
/** 0110 0001 1010 1101 xch %0, %e1 */
|
||||
ID(xch); DR(A); SM(HL, IMMU(1));
|
||||
|
||||
/** 0110 0001 1010 1001 xch %0, %e1%1 */
|
||||
/** 0110 0001 1010 1001 xch %0, %e1 */
|
||||
ID(xch); DR(A); SM2(HL, C, 0);
|
||||
|
||||
/** 0110 0001 1000 1reg xch %0, %1 */
|
||||
@ -1215,19 +1215,19 @@ rl78_decode_opcode (unsigned long pc AU,
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
/** 0111 1111 xor %0, %e1%!1 */
|
||||
/** 0111 1111 xor %0, %e!1 */
|
||||
ID(xor); DR(A); SM(None, IMMU(2)); Fz;
|
||||
|
||||
/** 0111 1101 xor %0, %e1%1 */
|
||||
/** 0111 1101 xor %0, %e1 */
|
||||
ID(xor); DR(A); SM(HL, 0); Fz;
|
||||
|
||||
/** 0110 0001 1111 0000 xor %0, %e1%1 */
|
||||
/** 0110 0001 1111 0000 xor %0, %e1 */
|
||||
ID(xor); DR(A); SM2(HL, B, 0); Fz;
|
||||
|
||||
/** 0111 1110 xor %0, %e1%1 */
|
||||
/** 0111 1110 xor %0, %e1 */
|
||||
ID(xor); DR(A); SM(HL, IMMU(1)); Fz;
|
||||
|
||||
/** 0110 0001 1111 0010 xor %0, %e1%1 */
|
||||
/** 0110 0001 1111 0010 xor %0, %e1 */
|
||||
ID(xor); DR(A); SM2(HL, C, 0); Fz;
|
||||
|
||||
/** 0111 1100 xor %0, #%1 */
|
||||
@ -1247,7 +1247,7 @@ rl78_decode_opcode (unsigned long pc AU,
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
/** 0111 0001 1bit 0111 xor1 cy, %e1%1 */
|
||||
/** 0111 0001 1bit 0111 xor1 cy, %e1 */
|
||||
ID(xor); DCY(); SM(HL, 0); SB(bit);
|
||||
|
||||
/** 0111 0001 1bit 1111 xor1 cy, %1 */
|
||||
|
||||
@ -155,38 +155,34 @@ print_insn_rl78 (bfd_vma addr, disassemble_info * dis)
|
||||
int do_cond = 0;
|
||||
int do_bang = 0;
|
||||
|
||||
s ++;
|
||||
|
||||
if (*s == 'x')
|
||||
while (1)
|
||||
{
|
||||
do_hex = 1;
|
||||
s++;
|
||||
}
|
||||
if (*s == '!')
|
||||
{
|
||||
do_bang = 1;
|
||||
s++;
|
||||
}
|
||||
if (*s == 'e')
|
||||
{
|
||||
do_es = 1;
|
||||
s++;
|
||||
}
|
||||
if (*s == 'a')
|
||||
{
|
||||
do_addr = 1;
|
||||
s++;
|
||||
}
|
||||
if (*s == 's')
|
||||
{
|
||||
do_sfr = 1;
|
||||
s++;
|
||||
}
|
||||
if (*s == 'c')
|
||||
{
|
||||
do_cond = 1;
|
||||
s++;
|
||||
s ++;
|
||||
switch (*s)
|
||||
{
|
||||
case 'x':
|
||||
do_hex = 1;
|
||||
break;
|
||||
case '!':
|
||||
do_bang = 1;
|
||||
break;
|
||||
case 'e':
|
||||
do_es = 1;
|
||||
break;
|
||||
case 'a':
|
||||
do_addr = 1;
|
||||
break;
|
||||
case 's':
|
||||
do_sfr = 1;
|
||||
break;
|
||||
case 'c':
|
||||
do_cond = 1;
|
||||
break;
|
||||
default:
|
||||
goto no_more_modifiers;
|
||||
}
|
||||
}
|
||||
no_more_modifiers:;
|
||||
|
||||
switch (*s)
|
||||
{
|
||||
@ -222,98 +218,103 @@ print_insn_rl78 (bfd_vma addr, disassemble_info * dis)
|
||||
case '0':
|
||||
case '1':
|
||||
oper = opcode.op + *s - '0';
|
||||
if (do_bang)
|
||||
PC ('!');
|
||||
if (do_es)
|
||||
{
|
||||
if (oper->use_es && indirect_type (oper->type))
|
||||
PR (PS, "es:");
|
||||
}
|
||||
|
||||
if (do_es)
|
||||
{
|
||||
if (oper->use_es && indirect_type (oper->type))
|
||||
PR (PS, "es:");
|
||||
}
|
||||
if (do_bang)
|
||||
PC ('!');
|
||||
|
||||
else if (do_cond)
|
||||
{
|
||||
PR (PS, "%s", condition_names[oper->condition]);
|
||||
}
|
||||
if (do_cond)
|
||||
{
|
||||
PR (PS, "%s", condition_names[oper->condition]);
|
||||
break;
|
||||
}
|
||||
|
||||
else
|
||||
switch (oper->type)
|
||||
switch (oper->type)
|
||||
{
|
||||
case RL78_Operand_Immediate:
|
||||
if (do_addr)
|
||||
dis->print_address_func (oper->addend, dis);
|
||||
else if (do_hex
|
||||
|| oper->addend > 999
|
||||
|| oper->addend < -999)
|
||||
PR (PS, "%#x", oper->addend);
|
||||
else
|
||||
PR (PS, "%d", oper->addend);
|
||||
break;
|
||||
|
||||
case RL78_Operand_Register:
|
||||
PR (PS, "%s", register_names[oper->reg]);
|
||||
break;
|
||||
|
||||
case RL78_Operand_Bit:
|
||||
PR (PS, "%s.%d", register_names[oper->reg], oper->bit_number);
|
||||
break;
|
||||
|
||||
case RL78_Operand_Indirect:
|
||||
case RL78_Operand_BitIndirect:
|
||||
switch (oper->reg)
|
||||
{
|
||||
case RL78_Operand_Immediate:
|
||||
if (do_addr)
|
||||
dis->print_address_func (oper->addend, dis);
|
||||
else if (do_hex
|
||||
|| oper->addend > 999
|
||||
|| oper->addend < -999)
|
||||
case RL78_Reg_None:
|
||||
if (oper->addend == 0xffffa && do_sfr && opcode.size == RL78_Byte)
|
||||
PR (PS, "psw");
|
||||
else if (oper->addend == 0xffff8 && do_sfr && opcode.size == RL78_Word)
|
||||
PR (PS, "sp");
|
||||
else if (oper->addend >= 0xffe20)
|
||||
PR (PS, "%#x", oper->addend);
|
||||
else
|
||||
PR (PS, "%d", oper->addend);
|
||||
break;
|
||||
|
||||
case RL78_Operand_Register:
|
||||
PR (PS, "%s", register_names[oper->reg]);
|
||||
break;
|
||||
|
||||
case RL78_Operand_Bit:
|
||||
PR (PS, "%s.%d", register_names[oper->reg], oper->bit_number);
|
||||
break;
|
||||
|
||||
case RL78_Operand_Indirect:
|
||||
case RL78_Operand_BitIndirect:
|
||||
switch (oper->reg)
|
||||
{
|
||||
case RL78_Reg_None:
|
||||
if (oper->addend == 0xffffa && do_sfr && opcode.size == RL78_Byte)
|
||||
PR (PS, "psw");
|
||||
else if (oper->addend == 0xffff8 && do_sfr && opcode.size == RL78_Word)
|
||||
PR (PS, "sp");
|
||||
else if (oper->addend >= 0xffe20)
|
||||
PR (PS, "%#x", oper->addend);
|
||||
else
|
||||
dis->print_address_func (oper->addend, dis);
|
||||
break;
|
||||
|
||||
case RL78_Reg_B:
|
||||
case RL78_Reg_C:
|
||||
case RL78_Reg_BC:
|
||||
PR (PS, "%d[%s]", oper->addend, register_names[oper->reg]);
|
||||
break;
|
||||
|
||||
default:
|
||||
PR (PS, "[%s", register_names[oper->reg]);
|
||||
if (oper->reg2 != RL78_Reg_None)
|
||||
PR (PS, "+%s", register_names[oper->reg2]);
|
||||
if (oper->addend)
|
||||
PR (PS, "+%d", oper->addend);
|
||||
PC (']');
|
||||
break;
|
||||
|
||||
int faddr = oper->addend;
|
||||
if (do_es && ! oper->use_es)
|
||||
faddr += 0xf0000;
|
||||
dis->print_address_func (faddr, dis);
|
||||
}
|
||||
if (oper->type == RL78_Operand_BitIndirect)
|
||||
PR (PS, ".%d", oper->bit_number);
|
||||
break;
|
||||
|
||||
#if DEBUG_SEMANTICS
|
||||
/* Shouldn't happen - push and pop don't print
|
||||
[SP] directly. But we *do* use them for
|
||||
semantic debugging. */
|
||||
case RL78_Operand_PostInc:
|
||||
PR (PS, "[%s++]", register_names[oper->reg]);
|
||||
case RL78_Reg_B:
|
||||
case RL78_Reg_C:
|
||||
case RL78_Reg_BC:
|
||||
PR (PS, "%d[%s]", oper->addend, register_names[oper->reg]);
|
||||
break;
|
||||
case RL78_Operand_PreDec:
|
||||
PR (PS, "[--%s]", register_names[oper->reg]);
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
/* If we ever print this, that means the
|
||||
programmer tried to print an operand with a
|
||||
type we don't expect. Print the line and
|
||||
operand number from rl78-decode.opc for
|
||||
them. */
|
||||
PR (PS, "???%d.%d", opcode.lineno, *s - '0');
|
||||
PR (PS, "[%s", register_names[oper->reg]);
|
||||
if (oper->reg2 != RL78_Reg_None)
|
||||
PR (PS, "+%s", register_names[oper->reg2]);
|
||||
if (oper->addend)
|
||||
PR (PS, "+%d", oper->addend);
|
||||
PC (']');
|
||||
break;
|
||||
|
||||
}
|
||||
if (oper->type == RL78_Operand_BitIndirect)
|
||||
PR (PS, ".%d", oper->bit_number);
|
||||
break;
|
||||
|
||||
#if DEBUG_SEMANTICS
|
||||
/* Shouldn't happen - push and pop don't print
|
||||
[SP] directly. But we *do* use them for
|
||||
semantic debugging. */
|
||||
case RL78_Operand_PostInc:
|
||||
PR (PS, "[%s++]", register_names[oper->reg]);
|
||||
break;
|
||||
case RL78_Operand_PreDec:
|
||||
PR (PS, "[--%s]", register_names[oper->reg]);
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
/* If we ever print this, that means the
|
||||
programmer tried to print an operand with a
|
||||
type we don't expect. Print the line and
|
||||
operand number from rl78-decode.opc for
|
||||
them. */
|
||||
PR (PS, "???%d.%d", opcode.lineno, *s - '0');
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user