PR gas/10623
* config/tc-mmix.c (md_assemble) <case mmix_operands_xyz_opt>: Allow register operands for SWYM as for TRIP and TRAP. Correct operand handling and error checking. Never emit BFD_RELOC_MMIX_REG_OR_BYTE for operands to these insns.
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@ -1,3 +1,11 @@
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2009-09-11 Hans-Peter Nilsson <hp@bitrange.com>
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PR gas/10623
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* config/tc-mmix.c (md_assemble) <case mmix_operands_xyz_opt>:
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Allow register operands for SWYM as for TRIP and TRAP. Correct
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operand handling and error checking. Never emit
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BFD_RELOC_MMIX_REG_OR_BYTE for operands to these insns.
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2009-09-10 Alan Modra <amodra@bigpond.net.au>
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* config/tc-d10v.c: Include dwarf2dbg.h.
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@ -1673,7 +1673,10 @@ md_assemble (char *str)
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break;
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case mmix_operands_xyz_opt:
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/* SWYM, TRIP, TRAP: zero, one, two or three operands. */
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/* SWYM, TRIP, TRAP: zero, one, two or three operands. It's
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unspecified whether operands are registers or constants, but
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when we find register syntax, we require operands to be literal and
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within 0..255. */
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if (n_operands == 0 && ! mmix_gnu_syntax)
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/* Zeros are in place - nothing needs to be done for zero
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operands. We don't allow this in GNU syntax mode, because it
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@ -1684,7 +1687,7 @@ md_assemble (char *str)
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{
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if (exp[0].X_op == O_constant)
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{
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if (exp[0].X_add_number > 255*255*255
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if (exp[0].X_add_number > 255*256*256
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|| exp[0].X_add_number < 0)
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{
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as_bad (_("invalid operands to opcode %s: `%s'"),
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@ -1726,7 +1729,7 @@ md_assemble (char *str)
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if (exp[1].X_op == O_constant)
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{
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if (exp[1].X_add_number > 255*255
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if (exp[1].X_add_number > 255*256
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|| exp[1].X_add_number < 0)
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{
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as_bad (_("invalid operands to opcode %s: `%s'"),
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@ -1798,12 +1801,15 @@ md_assemble (char *str)
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fix_new_exp (opc_fragP, opcodep - opc_fragP->fr_literal + 3,
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1, exp + 2, 0, BFD_RELOC_8);
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}
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else if (n_operands <= 3
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&& (strcmp (instruction->name, "trip") == 0
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|| strcmp (instruction->name, "trap") == 0))
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else
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{
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/* The meaning of operands to TRIP and TRAP are not defined, so
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we add combinations not handled above here as we find them. */
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/* We can't get here for other cases. */
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gas_assert (n_operands <= 3);
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/* The meaning of operands to TRIP and TRAP is not defined (and
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SWYM operands aren't enforced in mmixal, so let's avoid
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that). We add combinations not handled above here as we find
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them and as they're reported. */
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if (n_operands == 3)
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{
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/* Don't require non-register operands. Always generate
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@ -1811,49 +1817,48 @@ md_assemble (char *str)
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maintenance problems. TRIP is supposed to be a rare
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instruction, so the overhead should not matter. We
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aren't allowed to fix_new_exp for an expression which is
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an O_register at this point, however. */
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an O_register at this point, however.
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Don't use BFD_RELOC_MMIX_REG_OR_BYTE as that modifies
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the insn for a register in the Z field and we want
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consistency. */
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if (exp[0].X_op == O_register)
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opcodep[1] = exp[0].X_add_number;
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else
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fix_new_exp (opc_fragP, opcodep - opc_fragP->fr_literal + 1,
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1, exp, 0, BFD_RELOC_MMIX_REG_OR_BYTE);
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1, exp, 0, BFD_RELOC_8);
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if (exp[1].X_op == O_register)
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opcodep[2] = exp[1].X_add_number;
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else
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fix_new_exp (opc_fragP, opcodep - opc_fragP->fr_literal + 2,
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1, exp + 1, 0, BFD_RELOC_MMIX_REG_OR_BYTE);
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1, exp + 1, 0, BFD_RELOC_8);
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if (exp[2].X_op == O_register)
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opcodep[3] = exp[2].X_add_number;
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else
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fix_new_exp (opc_fragP, opcodep - opc_fragP->fr_literal + 3,
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1, exp + 2, 0, BFD_RELOC_MMIX_REG_OR_BYTE);
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1, exp + 2, 0, BFD_RELOC_8);
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}
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else if (n_operands == 2)
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{
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if (exp[0].X_op == O_register)
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opcodep[2] = exp[0].X_add_number;
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opcodep[1] = exp[0].X_add_number;
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else
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fix_new_exp (opc_fragP, opcodep - opc_fragP->fr_literal + 2,
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1, exp, 0, BFD_RELOC_MMIX_REG_OR_BYTE);
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fix_new_exp (opc_fragP, opcodep - opc_fragP->fr_literal + 1,
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1, exp, 0, BFD_RELOC_8);
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if (exp[1].X_op == O_register)
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opcodep[3] = exp[1].X_add_number;
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else
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fix_new_exp (opc_fragP, opcodep - opc_fragP->fr_literal + 3,
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1, exp + 1, 0, BFD_RELOC_MMIX_REG_OR_BYTE);
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fix_new_exp (opc_fragP, opcodep - opc_fragP->fr_literal + 2,
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2, exp + 1, 0, BFD_RELOC_16);
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}
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else
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{
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as_bad (_("unsupported operands to %s: `%s'"),
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instruction->name, operands);
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return;
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/* We can't get here for other cases. */
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gas_assert (n_operands == 1 && exp[0].X_op == O_register);
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opcodep[3] = exp[0].X_add_number;
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}
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}
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else
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{
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as_bad (_("invalid operands to opcode %s: `%s'"),
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instruction->name, operands);
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return;
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}
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break;
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case mmix_operands_resume:
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