Adjust VLE testsuite
To suit f7d69005
.
* testsuite/ld-powerpc/vle-multiseg-1.d: Adjust to suit segment change.
* testsuite/ld-powerpc/vle-multiseg-2.d: Likewise.
* testsuite/ld-powerpc/vle-multiseg-3.d: Likewise.
* testsuite/ld-powerpc/vle-multiseg-6.d: Likewise.
* testsuite/ld-powerpc/vle-reloc-2.d: Likewise.
This commit is contained in:
parent
f7d69005fb
commit
3e8c34ea9d
ld
@ -1,3 +1,11 @@
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2016-08-31 Alan Modra <amodra@gmail.com>
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* testsuite/ld-powerpc/vle-multiseg-1.d: Adjust to suit segment change.
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* testsuite/ld-powerpc/vle-multiseg-2.d: Likewise.
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* testsuite/ld-powerpc/vle-multiseg-3.d: Likewise.
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* testsuite/ld-powerpc/vle-multiseg-6.d: Likewise.
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* testsuite/ld-powerpc/vle-reloc-2.d: Likewise.
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2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
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* testsuite/ld-arc/tls_gs-01.d: Set to XFAIL on arc*-*-elf*.
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@ -1,14 +1,12 @@
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Elf file type is EXEC.*
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Entry point 0x0
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There are 2 program headers, starting at offset [0-9]+
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There are 1 program headers, starting at offset [0-9]+
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Program Headers:
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Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
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LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+
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LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
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LOAD ( +0x[0-9a-f]+){5} RWE 0x[0-f]+
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Section to Segment mapping:
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Segment Sections...
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00 .data
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01 .text_vle .text_iv .iv_handlers
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00 \.data \.text_vle \.text_iv \.iv_handlers
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@ -1,16 +1,12 @@
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Elf file type is EXEC.*
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Entry point 0x0
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There are 3 program headers, starting at offset [0-9]+
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There are 1 program headers, starting at offset [0-9]+
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Program Headers:
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Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
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LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
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LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+
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LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
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LOAD ( +0x[0-9a-f]+){5} RWE 0x[0-f]+
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Section to Segment mapping:
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Segment Sections...
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00 .text_vle
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01 .data
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02 .text_iv .iv_handlers
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00 \.text_vle \.data \.text_iv \.iv_handlers
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@ -1,16 +1,12 @@
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Elf file type is EXEC.*
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Entry point 0x0
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There are 3 program headers, starting at offset [0-9]+
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There are 1 program headers, starting at offset [0-9]+
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Program Headers:
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Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
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LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
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LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+
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LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
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LOAD ( +0x[0-9a-f]+){5} RWE 0x[0-f]+
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Section to Segment mapping:
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Segment Sections...
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00 .text_vle .text_iv
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01 .data
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02 .iv_handlers
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00 \.text_vle \.text_iv \.data \.iv_handlers
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@ -12,14 +12,14 @@ There are 4 program headers, starting at offset [0-9]+
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Program Headers:
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Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
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LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+
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LOAD ( +0x[0-9a-f]+){5} RW 0x[0-f]+
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LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
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LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
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LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
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Section to Segment mapping:
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Segment Sections...
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00 .data
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01 .text_vle
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02 .text_iv
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03 .text
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00 \.data
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01 \.text_vle
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02 \.text_iv
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03 \.text
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@ -2,86 +2,86 @@
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Disassembly of section .text:
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01800094 <sub1>:
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1800094: 00 04 se_blr
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01800096 <sub2>:
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1800096: 00 04 se_blr
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01800098 <vle_reloc_2>:
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1800098: 70 20 c1 c2 e_or2i r1,450
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180009c: 70 40 c1 81 e_or2i r2,385
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18000a0: 70 60 c1 81 e_or2i r3,385
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18000a4: 70 80 c1 ce e_or2i r4,462
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18000a8: 70 a0 c1 80 e_or2i r5,384
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18000ac: 70 40 c1 81 e_or2i r2,385
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18000b0: 70 20 c9 c2 e_and2i. r1,450
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18000b4: 70 40 c9 81 e_and2i. r2,385
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18000b8: 70 60 c9 81 e_and2i. r3,385
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18000bc: 70 80 c9 ce e_and2i. r4,462
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18000c0: 70 a0 c9 80 e_and2i. r5,384
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18000c4: 70 40 c9 81 e_and2i. r2,385
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18000c8: 70 20 d1 c2 e_or2is r1,450
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18000cc: 70 40 d1 81 e_or2is r2,385
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18000d0: 70 60 d1 81 e_or2is r3,385
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18000d4: 70 80 d1 ce e_or2is r4,462
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18000d8: 70 a0 d1 80 e_or2is r5,384
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18000dc: 70 40 d1 81 e_or2is r2,385
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18000e0: 70 20 e1 c2 e_lis r1,450
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18000e4: 70 40 e1 81 e_lis r2,385
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18000e8: 70 60 e1 81 e_lis r3,385
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18000ec: 70 80 e1 ce e_lis r4,462
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18000f0: 70 a0 e1 80 e_lis r5,384
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18000f4: 70 40 e1 81 e_lis r2,385
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18000f8: 70 20 e9 c2 e_and2is. r1,450
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18000fc: 70 40 e9 81 e_and2is. r2,385
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1800100: 70 60 e9 81 e_and2is. r3,385
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1800104: 70 80 e9 ce e_and2is. r4,462
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1800108: 70 a0 e9 80 e_and2is. r5,384
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180010c: 70 40 e9 81 e_and2is. r2,385
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1800110: 70 01 99 c2 e_cmp16i r1,450
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1800114: 70 02 99 81 e_cmp16i r2,385
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1800118: 70 03 99 81 e_cmp16i r3,385
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180011c: 70 04 99 ce e_cmp16i r4,462
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1800120: 70 05 99 80 e_cmp16i r5,384
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1800124: 70 02 99 81 e_cmp16i r2,385
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1800128: 70 01 a9 c2 e_cmpl16i r1,450
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180012c: 70 02 a9 81 e_cmpl16i r2,385
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1800130: 70 03 a9 81 e_cmpl16i r3,385
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1800134: 70 04 a9 ce e_cmpl16i r4,462
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1800138: 70 05 a9 80 e_cmpl16i r5,384
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180013c: 70 02 a9 81 e_cmpl16i r2,385
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1800140: 70 01 b1 c2 e_cmph16i r1,450
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1800144: 70 02 b1 81 e_cmph16i r2,385
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1800148: 70 03 b1 81 e_cmph16i r3,385
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180014c: 70 04 b1 ce e_cmph16i r4,462
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1800150: 70 05 b1 80 e_cmph16i r5,384
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1800154: 70 02 b1 81 e_cmph16i r2,385
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1800158: 70 01 b9 c2 e_cmphl16i r1,450
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180015c: 70 02 b9 81 e_cmphl16i r2,385
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1800160: 70 03 b9 81 e_cmphl16i r3,385
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1800164: 70 04 b9 ce e_cmphl16i r4,462
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1800168: 70 05 b9 80 e_cmphl16i r5,384
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180016c: 70 02 b9 81 e_cmphl16i r2,385
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1800170: 70 01 89 c2 e_add2i. r1,450
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1800174: 70 02 89 81 e_add2i. r2,385
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1800178: 70 03 89 81 e_add2i. r3,385
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180017c: 70 04 89 ce e_add2i. r4,462
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1800180: 70 05 89 80 e_add2i. r5,384
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1800184: 70 02 89 81 e_add2i. r2,385
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1800188: 70 01 91 c2 e_add2is r1,450
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180018c: 70 02 91 81 e_add2is r2,385
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1800190: 70 03 91 81 e_add2is r3,385
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1800194: 70 04 91 ce e_add2is r4,462
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1800198: 70 05 91 80 e_add2is r5,384
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180019c: 70 02 91 81 e_add2is r2,385
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18001a0: 70 01 a1 c2 e_mull2i r1,450
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18001a4: 70 02 a1 81 e_mull2i r2,385
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18001a8: 70 03 a1 81 e_mull2i r3,385
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18001ac: 70 04 a1 ce e_mull2i r4,462
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18001b0: 70 05 a1 80 e_mull2i r5,384
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18001b4: 70 02 a1 81 e_mull2i r2,385
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018001b8 <sub3>:
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18001b8: 00 04 se_blr
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018001ba <sub4>:
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18001ba: 00 04 se_blr
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018001bc <sub5>:
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18001bc: 00 04 se_blr
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.* <sub1>:
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.*: 00 04 se_blr
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.* <sub2>:
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.*: 00 04 se_blr
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.* <vle_reloc_2>:
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.*: 70 20 c1 a2 e_or2i r1,418
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.*: 70 40 c1 81 e_or2i r2,385
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.*: 70 60 c1 81 e_or2i r3,385
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.*: 70 80 c1 ae e_or2i r4,430
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.*: 70 a0 c1 80 e_or2i r5,384
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.*: 70 40 c1 81 e_or2i r2,385
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.*: 70 20 c9 a2 e_and2i\. r1,418
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.*: 70 40 c9 81 e_and2i\. r2,385
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.*: 70 60 c9 81 e_and2i\. r3,385
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.*: 70 80 c9 ae e_and2i\. r4,430
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.*: 70 a0 c9 80 e_and2i\. r5,384
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.*: 70 40 c9 81 e_and2i\. r2,385
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.*: 70 20 d1 a2 e_or2is r1,418
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.*: 70 40 d1 81 e_or2is r2,385
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.*: 70 60 d1 81 e_or2is r3,385
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.*: 70 80 d1 ae e_or2is r4,430
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.*: 70 a0 d1 80 e_or2is r5,384
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.*: 70 40 d1 81 e_or2is r2,385
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.*: 70 20 e1 a2 e_lis r1,418
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.*: 70 40 e1 81 e_lis r2,385
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.*: 70 60 e1 81 e_lis r3,385
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.*: 70 80 e1 ae e_lis r4,430
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.*: 70 a0 e1 80 e_lis r5,384
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.*: 70 40 e1 81 e_lis r2,385
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.*: 70 20 e9 a2 e_and2is\. r1,418
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.*: 70 40 e9 81 e_and2is\. r2,385
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.*: 70 60 e9 81 e_and2is\. r3,385
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.*: 70 80 e9 ae e_and2is\. r4,430
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.*: 70 a0 e9 80 e_and2is\. r5,384
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.*: 70 40 e9 81 e_and2is\. r2,385
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.*: 70 01 99 a2 e_cmp16i r1,418
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.*: 70 02 99 81 e_cmp16i r2,385
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.*: 70 03 99 81 e_cmp16i r3,385
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.*: 70 04 99 ae e_cmp16i r4,430
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.*: 70 05 99 80 e_cmp16i r5,384
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.*: 70 02 99 81 e_cmp16i r2,385
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.*: 70 01 a9 a2 e_cmpl16i r1,418
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.*: 70 02 a9 81 e_cmpl16i r2,385
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.*: 70 03 a9 81 e_cmpl16i r3,385
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.*: 70 04 a9 ae e_cmpl16i r4,430
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.*: 70 05 a9 80 e_cmpl16i r5,384
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.*: 70 02 a9 81 e_cmpl16i r2,385
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.*: 70 01 b1 a2 e_cmph16i r1,418
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.*: 70 02 b1 81 e_cmph16i r2,385
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.*: 70 03 b1 81 e_cmph16i r3,385
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.*: 70 04 b1 ae e_cmph16i r4,430
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.*: 70 05 b1 80 e_cmph16i r5,384
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.*: 70 02 b1 81 e_cmph16i r2,385
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.*: 70 01 b9 a2 e_cmphl16i r1,418
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.*: 70 02 b9 81 e_cmphl16i r2,385
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.*: 70 03 b9 81 e_cmphl16i r3,385
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.*: 70 04 b9 ae e_cmphl16i r4,430
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.*: 70 05 b9 80 e_cmphl16i r5,384
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.*: 70 02 b9 81 e_cmphl16i r2,385
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.*: 70 01 89 a2 e_add2i\. r1,418
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.*: 70 02 89 81 e_add2i\. r2,385
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.*: 70 03 89 81 e_add2i\. r3,385
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.*: 70 04 89 ae e_add2i\. r4,430
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.*: 70 05 89 80 e_add2i\. r5,384
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.*: 70 02 89 81 e_add2i\. r2,385
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.*: 70 01 91 a2 e_add2is r1,418
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.*: 70 02 91 81 e_add2is r2,385
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.*: 70 03 91 81 e_add2is r3,385
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.*: 70 04 91 ae e_add2is r4,430
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.*: 70 05 91 80 e_add2is r5,384
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.*: 70 02 91 81 e_add2is r2,385
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.*: 70 01 a1 a2 e_mull2i r1,418
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.*: 70 02 a1 81 e_mull2i r2,385
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.*: 70 03 a1 81 e_mull2i r3,385
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.*: 70 04 a1 ae e_mull2i r4,430
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.*: 70 05 a1 80 e_mull2i r5,384
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.*: 70 02 a1 81 e_mull2i r2,385
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.* <sub3>:
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.*: 00 04 se_blr
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.* <sub4>:
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.*: 00 04 se_blr
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.* <sub5>:
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.*: 00 04 se_blr
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