[AArch64] Add ARMv8.3 combined pointer authentication load instructions
Add support for ARMv8.3 LDRAA and LDRAB combined pointer authentication and load instructions. These instructions authenticate the base register and load 8 byte from it plus a scaled 10-bit offset with optional writeback to update the base register. A new instruction class (ldst_imm10) and operand type (AARCH64_OPND_ADDR_SIMM10) were introduced to handle the special addressing form. include/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM10. (enum aarch64_insn_class): Add ldst_imm10. opcodes/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * aarch64-tbl.h (QL_X1NIL): New. (arch64_opcode_table): Add ldraa, ldrab. (AARCH64_OPERANDS): Add "ADDR_SIMM10". * aarch64-asm.h (aarch64_ins_addr_simm10): Declare. * aarch64-asm.c (aarch64_ins_addr_simm10): Define. * aarch64-dis.h (aarch64_ext_addr_simm10): Declare. * aarch64-dis.c (aarch64_ext_addr_simm10): Define. * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10. * aarch64-opc.c (fields): Add data for FLD_S_simm10. (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10. (aarch64_print_operand): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_ADDR_SIMM10. (fix_insn): Likewise. (warn_unpredictable_ldst): Handle ldst_imm10. * testsuite/gas/aarch64/pac.s: Add ldraa and ldrab tests. * testsuite/gas/aarch64/pac.d: Likewise. * testsuite/gas/aarch64/illegal-ldraa.s: New. * testsuite/gas/aarch64/illegal-ldraa.l: New. * testsuite/gas/aarch64/illegal-ldraa.d: New.
This commit is contained in:
Szabolcs Nagy
parent
6ec49e7c0a
commit
3f06e55061
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@ -1,3 +1,14 @@
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2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_ADDR_SIMM10.
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(fix_insn): Likewise.
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(warn_unpredictable_ldst): Handle ldst_imm10.
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* testsuite/gas/aarch64/pac.s: Add ldraa and ldrab tests.
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* testsuite/gas/aarch64/pac.d: Likewise.
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* testsuite/gas/aarch64/illegal-ldraa.s: New.
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* testsuite/gas/aarch64/illegal-ldraa.l: New.
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* testsuite/gas/aarch64/illegal-ldraa.d: New.
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2016-11-15 Nick Clifton <nickc@redhat.com>
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PR gas/20803
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@ -6024,6 +6024,25 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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/* skip_p */ 0);
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break;
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case AARCH64_OPND_ADDR_SIMM10:
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po_misc_or_fail (parse_address (&str, info));
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if (info->addr.pcrel || info->addr.offset.is_reg
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|| !info->addr.preind || info->addr.postind)
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{
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set_syntax_error (_("invalid addressing mode"));
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goto failure;
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}
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if (inst.reloc.type != BFD_RELOC_UNUSED)
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{
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set_syntax_error (_("relocation not allowed"));
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goto failure;
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}
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assign_imm_if_const_or_fixup_later (&inst.reloc, info,
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/* addr_off_p */ 1,
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/* need_libopcodes_p */ 1,
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/* skip_p */ 0);
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break;
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case AARCH64_OPND_ADDR_UIMM12:
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po_misc_or_fail (parse_address (&str, info));
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if (info->addr.pcrel || info->addr.offset.is_reg
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@ -6481,6 +6500,7 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
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{
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case ldst_pos:
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case ldst_imm9:
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case ldst_imm10:
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case ldst_unscaled:
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case ldst_unpriv:
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/* Loading/storing the base register is unpredictable if writeback. */
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@ -7350,6 +7370,7 @@ fix_insn (fixS *fixP, uint32_t flags, offsetT value)
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case AARCH64_OPND_ADDR_SIMM7:
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case AARCH64_OPND_ADDR_SIMM9:
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case AARCH64_OPND_ADDR_SIMM9_2:
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case AARCH64_OPND_ADDR_SIMM10:
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case AARCH64_OPND_ADDR_UIMM12:
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/* Immediate offset in an address. */
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insn = get_aarch64_insn (buf);
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@ -0,0 +1,2 @@
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#as: -march=armv8.3-a -mno-verbose-error
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#error-output: illegal-ldraa.l
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@ -0,0 +1,35 @@
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[^:]+: Assembler messages:
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[^:]+:9: Error: immediate value must be a multiple of 8 at operand 2 -- `ldraa x0,\[x1,#1\]'
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[^:]+:10: Error: immediate value must be a multiple of 8 at operand 2 -- `ldraa x0,\[x1,#4\]'
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[^:]+:11: Error: immediate value must be a multiple of 8 at operand 2 -- `ldraa x0,\[x1,#-10\]'
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[^:]+:12: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#4096\]'
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[^:]+:13: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#5555\]'
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[^:]+:14: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#-4104\]'
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[^:]+:15: Error: 64-bit integer or SP register expected at operand 2 -- `ldraa x0,\[xz\]'
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[^:]+:16: Error: missing offset in the pre-indexed address at operand 2 -- `ldraa x0,\[x1\]!'
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[^:]+:17: Error: invalid expression in the address at operand 2 -- `ldraa x0,\[sp\],'
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[^:]+:18: Error: immediate value must be a multiple of 8 at operand 2 -- `ldraa x0,\[x1,#1\]!'
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[^:]+:19: Error: immediate value must be a multiple of 8 at operand 2 -- `ldraa x0,\[x1,#4\]!'
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[^:]+:20: Error: immediate value must be a multiple of 8 at operand 2 -- `ldraa x0,\[x1,#-10\]!'
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[^:]+:21: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#4096\]!'
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[^:]+:22: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#5555\]!'
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[^:]+:23: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#-4104\]!'
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[^:]+:24: Error: 64-bit integer or SP register expected at operand 2 -- `ldraa x0,\[xz\]'
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[^:]+:25: Error: invalid addressing mode at operand 2 -- `ldraa x0,\[x1\],#8'
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[^:]+:28: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#1\]'
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[^:]+:29: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#4\]'
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[^:]+:30: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#-10\]'
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[^:]+:31: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#4096\]'
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[^:]+:32: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#5555\]'
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[^:]+:33: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#-4104\]'
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[^:]+:34: Error: 64-bit integer or SP register expected at operand 2 -- `ldrab x0,\[xz\]'
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[^:]+:35: Error: missing offset in the pre-indexed address at operand 2 -- `ldrab x0,\[x1\]!'
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[^:]+:36: Error: invalid expression in the address at operand 2 -- `ldrab x0,\[sp\],'
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[^:]+:37: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#1\]!'
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[^:]+:38: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#4\]!'
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[^:]+:39: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#-10\]!'
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[^:]+:40: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#4096\]!'
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[^:]+:41: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#5555\]!'
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[^:]+:42: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#-4104\]!'
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[^:]+:43: Error: 64-bit integer or SP register expected at operand 2 -- `ldrab x0,\[xz\]'
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[^:]+:44: Error: invalid addressing mode at operand 2 -- `ldrab x0,\[x1\],#8'
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@ -0,0 +1,44 @@
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// Test illegal ARMv8.3 LDRAA and LDRAB instructions
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.text
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// Good.
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ldraa x0, [x1,#8]
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ldrab x0, [x1,#8]
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ldraa x0, [x1,#1]
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ldraa x0, [x1,#4]
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ldraa x0, [x1,#-10]
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ldraa x0, [x1,#4096]
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ldraa x0, [x1,#5555]
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ldraa x0, [x1,#-4104]
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ldraa x0, [xz]
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ldraa x0, [x1]!
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ldraa x0, [sp],
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ldraa x0, [x1,#1]!
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ldraa x0, [x1,#4]!
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ldraa x0, [x1,#-10]!
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ldraa x0, [x1,#4096]!
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ldraa x0, [x1,#5555]!
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ldraa x0, [x1,#-4104]!
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ldraa x0, [xz]
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ldraa x0, [x1], #8
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ldrab x0, [x1,#1]
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ldrab x0, [x1,#4]
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ldrab x0, [x1,#-10]
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ldrab x0, [x1,#4096]
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ldrab x0, [x1,#5555]
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ldrab x0, [x1,#-4104]
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ldrab x0, [xz]
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ldrab x0, [x1]!
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ldrab x0, [sp],
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ldrab x0, [x1,#1]!
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ldrab x0, [x1,#4]!
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ldrab x0, [x1,#-10]!
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ldrab x0, [x1,#4096]!
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ldrab x0, [x1,#5555]!
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ldrab x0, [x1,#-4104]!
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ldrab x0, [xz]
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ldrab x0, [x1], #8
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@ -50,3 +50,25 @@ Disassembly of section \.text:
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a4: d65f0fff retab
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a8: d69f0bff eretaa
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ac: d69f0fff eretab
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b0: f8200441 ldraa x1, \[x2\]
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b4: f8200441 ldraa x1, \[x2\]
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b8: f87ff483 ldraa x3, \[x4, #-8\]
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bc: f82014c5 ldraa x5, \[x6, #8\]
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c0: f83ff507 ldraa x7, \[x8, #4088\]
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c4: f8600528 ldraa x8, \[x9, #-4096\]
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c8: f82007e2 ldraa x2, \[sp\]
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cc: f87067e4 ldraa x4, \[sp, #-2000\]
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d0: f8a00441 ldrab x1, \[x2\]
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d4: f8a00441 ldrab x1, \[x2\]
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d8: f8fff483 ldrab x3, \[x4, #-8\]
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dc: f8a014c5 ldrab x5, \[x6, #8\]
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e0: f8bff507 ldrab x7, \[x8, #4088\]
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e4: f8e00528 ldrab x8, \[x9, #-4096\]
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e8: f8a007e2 ldrab x2, \[sp\]
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ec: f8f067e4 ldrab x4, \[sp, #-2000\]
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f0: f8201c62 ldraa x2, \[x3, #8\]!
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f4: f87ffca4 ldraa x4, \[x5, #-8\]!
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f8: f83fffe6 ldraa x6, \[sp, #4088\]!
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fc: f8a01c62 ldrab x2, \[x3, #8\]!
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100: f8fffca4 ldrab x4, \[x5, #-8\]!
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104: f8bfffe6 ldrab x6, \[sp, #4088\]!
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@ -54,3 +54,26 @@
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retab
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eretaa
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eretab
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ldraa x1, [x2]
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ldraa x1, [x2,#0]
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ldraa x3, [x4,#-8]
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ldraa x5, [x6,#8]
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ldraa x7, [x8,#4088]
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ldraa x8, [x9,#-4096]
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ldraa x2, [sp]
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ldraa x4, [sp,#-2000]
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ldrab x1, [x2]
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ldrab x1, [x2,#0]
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ldrab x3, [x4,#-8]
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ldrab x5, [x6,#8]
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ldrab x7, [x8,#4088]
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ldrab x8, [x9,#-4096]
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ldrab x2, [sp]
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ldrab x4, [sp,#-2000]
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ldraa x2, [x3, #8]!
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ldraa x4, [x5, #-8]!
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ldraa x6, [sp, #4088]!
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ldrab x2, [x3, #8]!
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ldrab x4, [x5, #-8]!
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ldrab x6, [sp, #4088]!
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@ -1,3 +1,8 @@
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2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM10.
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(enum aarch64_insn_class): Add ldst_imm10.
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2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rm_SP.
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@ -225,6 +225,7 @@ enum aarch64_opnd
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friendly feature of using LDR/STR as the
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the mnemonic name for LDUR/STUR instructions
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wherever there is no ambiguity. */
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AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
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AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
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AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
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AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
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@ -465,6 +466,7 @@ enum aarch64_insn_class
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ldst_immpost,
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ldst_immpre,
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ldst_imm9, /* immpost or immpre */
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ldst_imm10, /* LDRAA/LDRAB */
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ldst_pos,
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ldst_regoff,
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ldst_unpriv,
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@ -1,3 +1,20 @@
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2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* aarch64-tbl.h (QL_X1NIL): New.
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(arch64_opcode_table): Add ldraa, ldrab.
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(AARCH64_OPERANDS): Add "ADDR_SIMM10".
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* aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
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* aarch64-asm.c (aarch64_ins_addr_simm10): Define.
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* aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
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* aarch64-dis.c (aarch64_ext_addr_simm10): Define.
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* aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
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* aarch64-opc.c (fields): Add data for FLD_S_simm10.
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(operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
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(aarch64_print_operand): Likewise.
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* aarch64-asm-2.c: Regenerate.
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* aarch64-dis-2.c: Regenerate.
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* aarch64-opc-2.c: Regenerate.
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2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
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@ -197,380 +197,380 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
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case 743: /* extr */
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value = 743; /* --> extr. */
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break;
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case 951: /* bic */
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case 950: /* and */
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value = 950; /* --> and. */
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case 953: /* bic */
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case 952: /* and */
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value = 952; /* --> and. */
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break;
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case 953: /* mov */
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case 952: /* orr */
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value = 952; /* --> orr. */
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case 955: /* mov */
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case 954: /* orr */
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value = 954; /* --> orr. */
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break;
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case 956: /* tst */
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case 955: /* ands */
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value = 955; /* --> ands. */
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case 958: /* tst */
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case 957: /* ands */
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value = 957; /* --> ands. */
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break;
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case 961: /* uxtw */
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case 960: /* mov */
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case 959: /* orr */
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value = 959; /* --> orr. */
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case 963: /* uxtw */
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case 962: /* mov */
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case 961: /* orr */
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value = 961; /* --> orr. */
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break;
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case 963: /* mvn */
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case 962: /* orn */
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value = 962; /* --> orn. */
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case 965: /* mvn */
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case 964: /* orn */
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value = 964; /* --> orn. */
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break;
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case 967: /* tst */
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case 966: /* ands */
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value = 966; /* --> ands. */
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case 969: /* tst */
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case 968: /* ands */
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value = 968; /* --> ands. */
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break;
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case 1093: /* staddb */
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case 997: /* ldaddb */
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value = 997; /* --> ldaddb. */
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case 1095: /* staddb */
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case 999: /* ldaddb */
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value = 999; /* --> ldaddb. */
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break;
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case 1094: /* staddh */
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case 998: /* ldaddh */
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value = 998; /* --> ldaddh. */
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case 1096: /* staddh */
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case 1000: /* ldaddh */
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value = 1000; /* --> ldaddh. */
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break;
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case 1095: /* stadd */
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case 999: /* ldadd */
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value = 999; /* --> ldadd. */
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case 1097: /* stadd */
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case 1001: /* ldadd */
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value = 1001; /* --> ldadd. */
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break;
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case 1096: /* staddlb */
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case 1001: /* ldaddlb */
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value = 1001; /* --> ldaddlb. */
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case 1098: /* staddlb */
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case 1003: /* ldaddlb */
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value = 1003; /* --> ldaddlb. */
|
||||
break;
|
||||
case 1097: /* staddlh */
|
||||
case 1004: /* ldaddlh */
|
||||
value = 1004; /* --> ldaddlh. */
|
||||
case 1099: /* staddlh */
|
||||
case 1006: /* ldaddlh */
|
||||
value = 1006; /* --> ldaddlh. */
|
||||
break;
|
||||
case 1098: /* staddl */
|
||||
case 1007: /* ldaddl */
|
||||
value = 1007; /* --> ldaddl. */
|
||||
case 1100: /* staddl */
|
||||
case 1009: /* ldaddl */
|
||||
value = 1009; /* --> ldaddl. */
|
||||
break;
|
||||
case 1099: /* stclrb */
|
||||
case 1009: /* ldclrb */
|
||||
value = 1009; /* --> ldclrb. */
|
||||
case 1101: /* stclrb */
|
||||
case 1011: /* ldclrb */
|
||||
value = 1011; /* --> ldclrb. */
|
||||
break;
|
||||
case 1100: /* stclrh */
|
||||
case 1010: /* ldclrh */
|
||||
value = 1010; /* --> ldclrh. */
|
||||
case 1102: /* stclrh */
|
||||
case 1012: /* ldclrh */
|
||||
value = 1012; /* --> ldclrh. */
|
||||
break;
|
||||
case 1101: /* stclr */
|
||||
case 1011: /* ldclr */
|
||||
value = 1011; /* --> ldclr. */
|
||||
case 1103: /* stclr */
|
||||
case 1013: /* ldclr */
|
||||
value = 1013; /* --> ldclr. */
|
||||
break;
|
||||
case 1102: /* stclrlb */
|
||||
case 1013: /* ldclrlb */
|
||||
value = 1013; /* --> ldclrlb. */
|
||||
case 1104: /* stclrlb */
|
||||
case 1015: /* ldclrlb */
|
||||
value = 1015; /* --> ldclrlb. */
|
||||
break;
|
||||
case 1103: /* stclrlh */
|
||||
case 1016: /* ldclrlh */
|
||||
value = 1016; /* --> ldclrlh. */
|
||||
case 1105: /* stclrlh */
|
||||
case 1018: /* ldclrlh */
|
||||
value = 1018; /* --> ldclrlh. */
|
||||
break;
|
||||
case 1104: /* stclrl */
|
||||
case 1019: /* ldclrl */
|
||||
value = 1019; /* --> ldclrl. */
|
||||
case 1106: /* stclrl */
|
||||
case 1021: /* ldclrl */
|
||||
value = 1021; /* --> ldclrl. */
|
||||
break;
|
||||
case 1105: /* steorb */
|
||||
case 1021: /* ldeorb */
|
||||
value = 1021; /* --> ldeorb. */
|
||||
case 1107: /* steorb */
|
||||
case 1023: /* ldeorb */
|
||||
value = 1023; /* --> ldeorb. */
|
||||
break;
|
||||
case 1106: /* steorh */
|
||||
case 1022: /* ldeorh */
|
||||
value = 1022; /* --> ldeorh. */
|
||||
case 1108: /* steorh */
|
||||
case 1024: /* ldeorh */
|
||||
value = 1024; /* --> ldeorh. */
|
||||
break;
|
||||
case 1107: /* steor */
|
||||
case 1023: /* ldeor */
|
||||
value = 1023; /* --> ldeor. */
|
||||
case 1109: /* steor */
|
||||
case 1025: /* ldeor */
|
||||
value = 1025; /* --> ldeor. */
|
||||
break;
|
||||
case 1108: /* steorlb */
|
||||
case 1025: /* ldeorlb */
|
||||
value = 1025; /* --> ldeorlb. */
|
||||
case 1110: /* steorlb */
|
||||
case 1027: /* ldeorlb */
|
||||
value = 1027; /* --> ldeorlb. */
|
||||
break;
|
||||
case 1109: /* steorlh */
|
||||
case 1028: /* ldeorlh */
|
||||
value = 1028; /* --> ldeorlh. */
|
||||
case 1111: /* steorlh */
|
||||
case 1030: /* ldeorlh */
|
||||
value = 1030; /* --> ldeorlh. */
|
||||
break;
|
||||
case 1110: /* steorl */
|
||||
case 1031: /* ldeorl */
|
||||
value = 1031; /* --> ldeorl. */
|
||||
case 1112: /* steorl */
|
||||
case 1033: /* ldeorl */
|
||||
value = 1033; /* --> ldeorl. */
|
||||
break;
|
||||
case 1111: /* stsetb */
|
||||
case 1033: /* ldsetb */
|
||||
value = 1033; /* --> ldsetb. */
|
||||
case 1113: /* stsetb */
|
||||
case 1035: /* ldsetb */
|
||||
value = 1035; /* --> ldsetb. */
|
||||
break;
|
||||
case 1112: /* stseth */
|
||||
case 1034: /* ldseth */
|
||||
value = 1034; /* --> ldseth. */
|
||||
case 1114: /* stseth */
|
||||
case 1036: /* ldseth */
|
||||
value = 1036; /* --> ldseth. */
|
||||
break;
|
||||
case 1113: /* stset */
|
||||
case 1035: /* ldset */
|
||||
value = 1035; /* --> ldset. */
|
||||
case 1115: /* stset */
|
||||
case 1037: /* ldset */
|
||||
value = 1037; /* --> ldset. */
|
||||
break;
|
||||
case 1114: /* stsetlb */
|
||||
case 1037: /* ldsetlb */
|
||||
value = 1037; /* --> ldsetlb. */
|
||||
case 1116: /* stsetlb */
|
||||
case 1039: /* ldsetlb */
|
||||
value = 1039; /* --> ldsetlb. */
|
||||
break;
|
||||
case 1115: /* stsetlh */
|
||||
case 1040: /* ldsetlh */
|
||||
value = 1040; /* --> ldsetlh. */
|
||||
case 1117: /* stsetlh */
|
||||
case 1042: /* ldsetlh */
|
||||
value = 1042; /* --> ldsetlh. */
|
||||
break;
|
||||
case 1116: /* stsetl */
|
||||
case 1043: /* ldsetl */
|
||||
value = 1043; /* --> ldsetl. */
|
||||
case 1118: /* stsetl */
|
||||
case 1045: /* ldsetl */
|
||||
value = 1045; /* --> ldsetl. */
|
||||
break;
|
||||
case 1117: /* stsmaxb */
|
||||
case 1045: /* ldsmaxb */
|
||||
value = 1045; /* --> ldsmaxb. */
|
||||
case 1119: /* stsmaxb */
|
||||
case 1047: /* ldsmaxb */
|
||||
value = 1047; /* --> ldsmaxb. */
|
||||
break;
|
||||
case 1118: /* stsmaxh */
|
||||
case 1046: /* ldsmaxh */
|
||||
value = 1046; /* --> ldsmaxh. */
|
||||
case 1120: /* stsmaxh */
|
||||
case 1048: /* ldsmaxh */
|
||||
value = 1048; /* --> ldsmaxh. */
|
||||
break;
|
||||
case 1119: /* stsmax */
|
||||
case 1047: /* ldsmax */
|
||||
value = 1047; /* --> ldsmax. */
|
||||
case 1121: /* stsmax */
|
||||
case 1049: /* ldsmax */
|
||||
value = 1049; /* --> ldsmax. */
|
||||
break;
|
||||
case 1120: /* stsmaxlb */
|
||||
case 1049: /* ldsmaxlb */
|
||||
value = 1049; /* --> ldsmaxlb. */
|
||||
case 1122: /* stsmaxlb */
|
||||
case 1051: /* ldsmaxlb */
|
||||
value = 1051; /* --> ldsmaxlb. */
|
||||
break;
|
||||
case 1121: /* stsmaxlh */
|
||||
case 1052: /* ldsmaxlh */
|
||||
value = 1052; /* --> ldsmaxlh. */
|
||||
case 1123: /* stsmaxlh */
|
||||
case 1054: /* ldsmaxlh */
|
||||
value = 1054; /* --> ldsmaxlh. */
|
||||
break;
|
||||
case 1122: /* stsmaxl */
|
||||
case 1055: /* ldsmaxl */
|
||||
value = 1055; /* --> ldsmaxl. */
|
||||
case 1124: /* stsmaxl */
|
||||
case 1057: /* ldsmaxl */
|
||||
value = 1057; /* --> ldsmaxl. */
|
||||
break;
|
||||
case 1123: /* stsminb */
|
||||
case 1057: /* ldsminb */
|
||||
value = 1057; /* --> ldsminb. */
|
||||
case 1125: /* stsminb */
|
||||
case 1059: /* ldsminb */
|
||||
value = 1059; /* --> ldsminb. */
|
||||
break;
|
||||
case 1124: /* stsminh */
|
||||
case 1058: /* ldsminh */
|
||||
value = 1058; /* --> ldsminh. */
|
||||
case 1126: /* stsminh */
|
||||
case 1060: /* ldsminh */
|
||||
value = 1060; /* --> ldsminh. */
|
||||
break;
|
||||
case 1125: /* stsmin */
|
||||
case 1059: /* ldsmin */
|
||||
value = 1059; /* --> ldsmin. */
|
||||
case 1127: /* stsmin */
|
||||
case 1061: /* ldsmin */
|
||||
value = 1061; /* --> ldsmin. */
|
||||
break;
|
||||
case 1126: /* stsminlb */
|
||||
case 1061: /* ldsminlb */
|
||||
value = 1061; /* --> ldsminlb. */
|
||||
case 1128: /* stsminlb */
|
||||
case 1063: /* ldsminlb */
|
||||
value = 1063; /* --> ldsminlb. */
|
||||
break;
|
||||
case 1127: /* stsminlh */
|
||||
case 1064: /* ldsminlh */
|
||||
value = 1064; /* --> ldsminlh. */
|
||||
case 1129: /* stsminlh */
|
||||
case 1066: /* ldsminlh */
|
||||
value = 1066; /* --> ldsminlh. */
|
||||
break;
|
||||
case 1128: /* stsminl */
|
||||
case 1067: /* ldsminl */
|
||||
value = 1067; /* --> ldsminl. */
|
||||
case 1130: /* stsminl */
|
||||
case 1069: /* ldsminl */
|
||||
value = 1069; /* --> ldsminl. */
|
||||
break;
|
||||
case 1129: /* stumaxb */
|
||||
case 1069: /* ldumaxb */
|
||||
value = 1069; /* --> ldumaxb. */
|
||||
case 1131: /* stumaxb */
|
||||
case 1071: /* ldumaxb */
|
||||
value = 1071; /* --> ldumaxb. */
|
||||
break;
|
||||
case 1130: /* stumaxh */
|
||||
case 1070: /* ldumaxh */
|
||||
value = 1070; /* --> ldumaxh. */
|
||||
case 1132: /* stumaxh */
|
||||
case 1072: /* ldumaxh */
|
||||
value = 1072; /* --> ldumaxh. */
|
||||
break;
|
||||
case 1131: /* stumax */
|
||||
case 1071: /* ldumax */
|
||||
value = 1071; /* --> ldumax. */
|
||||
case 1133: /* stumax */
|
||||
case 1073: /* ldumax */
|
||||
value = 1073; /* --> ldumax. */
|
||||
break;
|
||||
case 1132: /* stumaxlb */
|
||||
case 1073: /* ldumaxlb */
|
||||
value = 1073; /* --> ldumaxlb. */
|
||||
case 1134: /* stumaxlb */
|
||||
case 1075: /* ldumaxlb */
|
||||
value = 1075; /* --> ldumaxlb. */
|
||||
break;
|
||||
case 1133: /* stumaxlh */
|
||||
case 1076: /* ldumaxlh */
|
||||
value = 1076; /* --> ldumaxlh. */
|
||||
case 1135: /* stumaxlh */
|
||||
case 1078: /* ldumaxlh */
|
||||
value = 1078; /* --> ldumaxlh. */
|
||||
break;
|
||||
case 1134: /* stumaxl */
|
||||
case 1079: /* ldumaxl */
|
||||
value = 1079; /* --> ldumaxl. */
|
||||
case 1136: /* stumaxl */
|
||||
case 1081: /* ldumaxl */
|
||||
value = 1081; /* --> ldumaxl. */
|
||||
break;
|
||||
case 1135: /* stuminb */
|
||||
case 1081: /* lduminb */
|
||||
value = 1081; /* --> lduminb. */
|
||||
case 1137: /* stuminb */
|
||||
case 1083: /* lduminb */
|
||||
value = 1083; /* --> lduminb. */
|
||||
break;
|
||||
case 1136: /* stuminh */
|
||||
case 1082: /* lduminh */
|
||||
value = 1082; /* --> lduminh. */
|
||||
case 1138: /* stuminh */
|
||||
case 1084: /* lduminh */
|
||||
value = 1084; /* --> lduminh. */
|
||||
break;
|
||||
case 1137: /* stumin */
|
||||
case 1083: /* ldumin */
|
||||
value = 1083; /* --> ldumin. */
|
||||
case 1139: /* stumin */
|
||||
case 1085: /* ldumin */
|
||||
value = 1085; /* --> ldumin. */
|
||||
break;
|
||||
case 1138: /* stuminlb */
|
||||
case 1085: /* lduminlb */
|
||||
value = 1085; /* --> lduminlb. */
|
||||
case 1140: /* stuminlb */
|
||||
case 1087: /* lduminlb */
|
||||
value = 1087; /* --> lduminlb. */
|
||||
break;
|
||||
case 1139: /* stuminlh */
|
||||
case 1088: /* lduminlh */
|
||||
value = 1088; /* --> lduminlh. */
|
||||
case 1141: /* stuminlh */
|
||||
case 1090: /* lduminlh */
|
||||
value = 1090; /* --> lduminlh. */
|
||||
break;
|
||||
case 1140: /* stuminl */
|
||||
case 1091: /* lduminl */
|
||||
value = 1091; /* --> lduminl. */
|
||||
break;
|
||||
case 1142: /* mov */
|
||||
case 1141: /* movn */
|
||||
value = 1141; /* --> movn. */
|
||||
case 1142: /* stuminl */
|
||||
case 1093: /* lduminl */
|
||||
value = 1093; /* --> lduminl. */
|
||||
break;
|
||||
case 1144: /* mov */
|
||||
case 1143: /* movz */
|
||||
value = 1143; /* --> movz. */
|
||||
case 1143: /* movn */
|
||||
value = 1143; /* --> movn. */
|
||||
break;
|
||||
case 1182: /* autibsp */
|
||||
case 1181: /* autibz */
|
||||
case 1180: /* autiasp */
|
||||
case 1179: /* autiaz */
|
||||
case 1178: /* pacibsp */
|
||||
case 1177: /* pacibz */
|
||||
case 1176: /* paciasp */
|
||||
case 1175: /* paciaz */
|
||||
case 1162: /* psb */
|
||||
case 1161: /* esb */
|
||||
case 1160: /* autib1716 */
|
||||
case 1159: /* autia1716 */
|
||||
case 1158: /* pacib1716 */
|
||||
case 1157: /* pacia1716 */
|
||||
case 1156: /* xpaclri */
|
||||
case 1155: /* sevl */
|
||||
case 1154: /* sev */
|
||||
case 1153: /* wfi */
|
||||
case 1152: /* wfe */
|
||||
case 1151: /* yield */
|
||||
case 1150: /* nop */
|
||||
case 1149: /* hint */
|
||||
value = 1149; /* --> hint. */
|
||||
case 1146: /* mov */
|
||||
case 1145: /* movz */
|
||||
value = 1145; /* --> movz. */
|
||||
break;
|
||||
case 1171: /* tlbi */
|
||||
case 1170: /* ic */
|
||||
case 1169: /* dc */
|
||||
case 1168: /* at */
|
||||
case 1167: /* sys */
|
||||
value = 1167; /* --> sys. */
|
||||
case 1184: /* autibsp */
|
||||
case 1183: /* autibz */
|
||||
case 1182: /* autiasp */
|
||||
case 1181: /* autiaz */
|
||||
case 1180: /* pacibsp */
|
||||
case 1179: /* pacibz */
|
||||
case 1178: /* paciasp */
|
||||
case 1177: /* paciaz */
|
||||
case 1164: /* psb */
|
||||
case 1163: /* esb */
|
||||
case 1162: /* autib1716 */
|
||||
case 1161: /* autia1716 */
|
||||
case 1160: /* pacib1716 */
|
||||
case 1159: /* pacia1716 */
|
||||
case 1158: /* xpaclri */
|
||||
case 1157: /* sevl */
|
||||
case 1156: /* sev */
|
||||
case 1155: /* wfi */
|
||||
case 1154: /* wfe */
|
||||
case 1153: /* yield */
|
||||
case 1152: /* nop */
|
||||
case 1151: /* hint */
|
||||
value = 1151; /* --> hint. */
|
||||
break;
|
||||
case 1925: /* bic */
|
||||
case 1230: /* and */
|
||||
value = 1230; /* --> and. */
|
||||
case 1173: /* tlbi */
|
||||
case 1172: /* ic */
|
||||
case 1171: /* dc */
|
||||
case 1170: /* at */
|
||||
case 1169: /* sys */
|
||||
value = 1169; /* --> sys. */
|
||||
break;
|
||||
case 1213: /* mov */
|
||||
case 1927: /* bic */
|
||||
case 1232: /* and */
|
||||
value = 1232; /* --> and. */
|
||||
break;
|
||||
case 1217: /* movs */
|
||||
case 1233: /* ands */
|
||||
value = 1233; /* --> ands. */
|
||||
case 1215: /* mov */
|
||||
case 1234: /* and */
|
||||
value = 1234; /* --> and. */
|
||||
break;
|
||||
case 1926: /* cmple */
|
||||
case 1268: /* cmpge */
|
||||
value = 1268; /* --> cmpge. */
|
||||
case 1219: /* movs */
|
||||
case 1235: /* ands */
|
||||
value = 1235; /* --> ands. */
|
||||
break;
|
||||
case 1929: /* cmplt */
|
||||
case 1271: /* cmpgt */
|
||||
value = 1271; /* --> cmpgt. */
|
||||
case 1928: /* cmple */
|
||||
case 1270: /* cmpge */
|
||||
value = 1270; /* --> cmpge. */
|
||||
break;
|
||||
case 1927: /* cmplo */
|
||||
case 1273: /* cmphi */
|
||||
value = 1273; /* --> cmphi. */
|
||||
case 1931: /* cmplt */
|
||||
case 1273: /* cmpgt */
|
||||
value = 1273; /* --> cmpgt. */
|
||||
break;
|
||||
case 1928: /* cmpls */
|
||||
case 1276: /* cmphs */
|
||||
value = 1276; /* --> cmphs. */
|
||||
case 1929: /* cmplo */
|
||||
case 1275: /* cmphi */
|
||||
value = 1275; /* --> cmphi. */
|
||||
break;
|
||||
case 1210: /* mov */
|
||||
case 1298: /* cpy */
|
||||
value = 1298; /* --> cpy. */
|
||||
case 1930: /* cmpls */
|
||||
case 1278: /* cmphs */
|
||||
value = 1278; /* --> cmphs. */
|
||||
break;
|
||||
case 1212: /* mov */
|
||||
case 1299: /* cpy */
|
||||
value = 1299; /* --> cpy. */
|
||||
break;
|
||||
case 1936: /* fmov */
|
||||
case 1215: /* mov */
|
||||
case 1300: /* cpy */
|
||||
value = 1300; /* --> cpy. */
|
||||
break;
|
||||
case 1205: /* mov */
|
||||
case 1312: /* dup */
|
||||
value = 1312; /* --> dup. */
|
||||
case 1214: /* mov */
|
||||
case 1301: /* cpy */
|
||||
value = 1301; /* --> cpy. */
|
||||
break;
|
||||
case 1938: /* fmov */
|
||||
case 1217: /* mov */
|
||||
case 1302: /* cpy */
|
||||
value = 1302; /* --> cpy. */
|
||||
break;
|
||||
case 1207: /* mov */
|
||||
case 1204: /* mov */
|
||||
case 1313: /* dup */
|
||||
value = 1313; /* --> dup. */
|
||||
break;
|
||||
case 1935: /* fmov */
|
||||
case 1209: /* mov */
|
||||
case 1314: /* dup */
|
||||
value = 1314; /* --> dup. */
|
||||
break;
|
||||
case 1208: /* mov */
|
||||
case 1315: /* dupm */
|
||||
value = 1315; /* --> dupm. */
|
||||
case 1209: /* mov */
|
||||
case 1206: /* mov */
|
||||
case 1315: /* dup */
|
||||
value = 1315; /* --> dup. */
|
||||
break;
|
||||
case 1930: /* eon */
|
||||
case 1317: /* eor */
|
||||
value = 1317; /* --> eor. */
|
||||
case 1937: /* fmov */
|
||||
case 1211: /* mov */
|
||||
case 1316: /* dup */
|
||||
value = 1316; /* --> dup. */
|
||||
break;
|
||||
case 1218: /* not */
|
||||
case 1210: /* mov */
|
||||
case 1317: /* dupm */
|
||||
value = 1317; /* --> dupm. */
|
||||
break;
|
||||
case 1932: /* eon */
|
||||
case 1319: /* eor */
|
||||
value = 1319; /* --> eor. */
|
||||
break;
|
||||
case 1219: /* nots */
|
||||
case 1320: /* eors */
|
||||
value = 1320; /* --> eors. */
|
||||
case 1220: /* not */
|
||||
case 1321: /* eor */
|
||||
value = 1321; /* --> eor. */
|
||||
break;
|
||||
case 1931: /* facle */
|
||||
case 1325: /* facge */
|
||||
value = 1325; /* --> facge. */
|
||||
case 1221: /* nots */
|
||||
case 1322: /* eors */
|
||||
value = 1322; /* --> eors. */
|
||||
break;
|
||||
case 1932: /* faclt */
|
||||
case 1326: /* facgt */
|
||||
value = 1326; /* --> facgt. */
|
||||
case 1933: /* facle */
|
||||
case 1327: /* facge */
|
||||
value = 1327; /* --> facge. */
|
||||
break;
|
||||
case 1933: /* fcmle */
|
||||
case 1335: /* fcmge */
|
||||
value = 1335; /* --> fcmge. */
|
||||
case 1934: /* faclt */
|
||||
case 1328: /* facgt */
|
||||
value = 1328; /* --> facgt. */
|
||||
break;
|
||||
case 1934: /* fcmlt */
|
||||
case 1337: /* fcmgt */
|
||||
value = 1337; /* --> fcmgt. */
|
||||
case 1935: /* fcmle */
|
||||
case 1337: /* fcmge */
|
||||
value = 1337; /* --> fcmge. */
|
||||
break;
|
||||
case 1202: /* fmov */
|
||||
case 1343: /* fcpy */
|
||||
value = 1343; /* --> fcpy. */
|
||||
case 1936: /* fcmlt */
|
||||
case 1339: /* fcmgt */
|
||||
value = 1339; /* --> fcmgt. */
|
||||
break;
|
||||
case 1201: /* fmov */
|
||||
case 1360: /* fdup */
|
||||
value = 1360; /* --> fdup. */
|
||||
case 1204: /* fmov */
|
||||
case 1345: /* fcpy */
|
||||
value = 1345; /* --> fcpy. */
|
||||
break;
|
||||
case 1203: /* mov */
|
||||
case 1658: /* orr */
|
||||
value = 1658; /* --> orr. */
|
||||
case 1203: /* fmov */
|
||||
case 1362: /* fdup */
|
||||
value = 1362; /* --> fdup. */
|
||||
break;
|
||||
case 1937: /* orn */
|
||||
case 1659: /* orr */
|
||||
value = 1659; /* --> orr. */
|
||||
case 1205: /* mov */
|
||||
case 1660: /* orr */
|
||||
value = 1660; /* --> orr. */
|
||||
break;
|
||||
case 1206: /* mov */
|
||||
case 1939: /* orn */
|
||||
case 1661: /* orr */
|
||||
value = 1661; /* --> orr. */
|
||||
break;
|
||||
case 1216: /* movs */
|
||||
case 1662: /* orrs */
|
||||
value = 1662; /* --> orrs. */
|
||||
case 1208: /* mov */
|
||||
case 1663: /* orr */
|
||||
value = 1663; /* --> orr. */
|
||||
break;
|
||||
case 1211: /* mov */
|
||||
case 1718: /* sel */
|
||||
value = 1718; /* --> sel. */
|
||||
case 1218: /* movs */
|
||||
case 1664: /* orrs */
|
||||
value = 1664; /* --> orrs. */
|
||||
break;
|
||||
case 1214: /* mov */
|
||||
case 1719: /* sel */
|
||||
value = 1719; /* --> sel. */
|
||||
case 1213: /* mov */
|
||||
case 1720: /* sel */
|
||||
value = 1720; /* --> sel. */
|
||||
break;
|
||||
case 1216: /* mov */
|
||||
case 1721: /* sel */
|
||||
value = 1721; /* --> sel. */
|
||||
break;
|
||||
default: return NULL;
|
||||
}
|
||||
|
|
@ -613,7 +613,6 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||
case 28:
|
||||
case 36:
|
||||
case 37:
|
||||
case 140:
|
||||
case 141:
|
||||
case 142:
|
||||
case 143:
|
||||
|
|
@ -623,7 +622,7 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||
case 147:
|
||||
case 148:
|
||||
case 149:
|
||||
case 162:
|
||||
case 150:
|
||||
case 163:
|
||||
case 164:
|
||||
case 165:
|
||||
|
|
@ -633,7 +632,8 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||
case 169:
|
||||
case 170:
|
||||
case 171:
|
||||
case 174:
|
||||
case 172:
|
||||
case 175:
|
||||
return aarch64_ins_regno (self, info, code, inst);
|
||||
case 13:
|
||||
return aarch64_ins_reg_extended (self, info, code, inst);
|
||||
|
|
@ -671,9 +671,8 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||
case 70:
|
||||
case 71:
|
||||
case 72:
|
||||
case 137:
|
||||
case 139:
|
||||
case 154:
|
||||
case 138:
|
||||
case 140:
|
||||
case 155:
|
||||
case 156:
|
||||
case 157:
|
||||
|
|
@ -681,6 +680,7 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||
case 159:
|
||||
case 160:
|
||||
case 161:
|
||||
case 162:
|
||||
return aarch64_ins_imm (self, info, code, inst);
|
||||
case 39:
|
||||
case 40:
|
||||
|
|
@ -690,10 +690,10 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||
case 43:
|
||||
return aarch64_ins_advsimd_imm_modified (self, info, code, inst);
|
||||
case 47:
|
||||
case 130:
|
||||
case 131:
|
||||
return aarch64_ins_fpimm (self, info, code, inst);
|
||||
case 61:
|
||||
case 135:
|
||||
case 136:
|
||||
return aarch64_ins_limm (self, info, code, inst);
|
||||
case 62:
|
||||
return aarch64_ins_aimm (self, info, code, inst);
|
||||
|
|
@ -705,7 +705,7 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||
case 67:
|
||||
return aarch64_ins_cond (self, info, code, inst);
|
||||
case 73:
|
||||
case 79:
|
||||
case 80:
|
||||
return aarch64_ins_addr_simple (self, info, code, inst);
|
||||
case 74:
|
||||
return aarch64_ins_addr_regoff (self, info, code, inst);
|
||||
|
|
@ -714,40 +714,41 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||
case 77:
|
||||
return aarch64_ins_addr_simm (self, info, code, inst);
|
||||
case 78:
|
||||
return aarch64_ins_addr_simm10 (self, info, code, inst);
|
||||
case 79:
|
||||
return aarch64_ins_addr_uimm12 (self, info, code, inst);
|
||||
case 80:
|
||||
return aarch64_ins_simd_addr_post (self, info, code, inst);
|
||||
case 81:
|
||||
return aarch64_ins_sysreg (self, info, code, inst);
|
||||
return aarch64_ins_simd_addr_post (self, info, code, inst);
|
||||
case 82:
|
||||
return aarch64_ins_pstatefield (self, info, code, inst);
|
||||
return aarch64_ins_sysreg (self, info, code, inst);
|
||||
case 83:
|
||||
return aarch64_ins_pstatefield (self, info, code, inst);
|
||||
case 84:
|
||||
case 85:
|
||||
case 86:
|
||||
return aarch64_ins_sysins_op (self, info, code, inst);
|
||||
case 87:
|
||||
return aarch64_ins_sysins_op (self, info, code, inst);
|
||||
case 88:
|
||||
return aarch64_ins_barrier (self, info, code, inst);
|
||||
case 89:
|
||||
return aarch64_ins_prfop (self, info, code, inst);
|
||||
return aarch64_ins_barrier (self, info, code, inst);
|
||||
case 90:
|
||||
return aarch64_ins_hint (self, info, code, inst);
|
||||
return aarch64_ins_prfop (self, info, code, inst);
|
||||
case 91:
|
||||
return aarch64_ins_hint (self, info, code, inst);
|
||||
case 92:
|
||||
case 93:
|
||||
case 94:
|
||||
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst);
|
||||
case 95:
|
||||
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst);
|
||||
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst);
|
||||
case 96:
|
||||
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst);
|
||||
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst);
|
||||
case 97:
|
||||
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst);
|
||||
case 98:
|
||||
case 99:
|
||||
case 100:
|
||||
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst);
|
||||
case 101:
|
||||
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst);
|
||||
case 102:
|
||||
case 103:
|
||||
case 104:
|
||||
|
|
@ -759,8 +760,8 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||
case 110:
|
||||
case 111:
|
||||
case 112:
|
||||
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst);
|
||||
case 113:
|
||||
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst);
|
||||
case 114:
|
||||
case 115:
|
||||
case 116:
|
||||
|
|
@ -768,44 +769,45 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||
case 118:
|
||||
case 119:
|
||||
case 120:
|
||||
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst);
|
||||
case 121:
|
||||
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst);
|
||||
case 122:
|
||||
case 123:
|
||||
case 124:
|
||||
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst);
|
||||
case 125:
|
||||
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst);
|
||||
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst);
|
||||
case 126:
|
||||
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst);
|
||||
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst);
|
||||
case 127:
|
||||
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst);
|
||||
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst);
|
||||
case 128:
|
||||
return aarch64_ins_sve_aimm (self, info, code, inst);
|
||||
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst);
|
||||
case 129:
|
||||
return aarch64_ins_sve_aimm (self, info, code, inst);
|
||||
case 130:
|
||||
return aarch64_ins_sve_asimm (self, info, code, inst);
|
||||
case 131:
|
||||
return aarch64_ins_sve_float_half_one (self, info, code, inst);
|
||||
case 132:
|
||||
return aarch64_ins_sve_float_half_two (self, info, code, inst);
|
||||
return aarch64_ins_sve_float_half_one (self, info, code, inst);
|
||||
case 133:
|
||||
return aarch64_ins_sve_float_zero_one (self, info, code, inst);
|
||||
return aarch64_ins_sve_float_half_two (self, info, code, inst);
|
||||
case 134:
|
||||
return aarch64_ins_sve_float_zero_one (self, info, code, inst);
|
||||
case 135:
|
||||
return aarch64_ins_inv_limm (self, info, code, inst);
|
||||
case 136:
|
||||
case 137:
|
||||
return aarch64_ins_sve_limm_mov (self, info, code, inst);
|
||||
case 138:
|
||||
case 139:
|
||||
return aarch64_ins_sve_scale (self, info, code, inst);
|
||||
case 150:
|
||||
case 151:
|
||||
return aarch64_ins_sve_shlimm (self, info, code, inst);
|
||||
case 152:
|
||||
return aarch64_ins_sve_shlimm (self, info, code, inst);
|
||||
case 153:
|
||||
case 154:
|
||||
return aarch64_ins_sve_shrimm (self, info, code, inst);
|
||||
case 172:
|
||||
return aarch64_ins_sve_index (self, info, code, inst);
|
||||
case 173:
|
||||
case 175:
|
||||
return aarch64_ins_sve_index (self, info, code, inst);
|
||||
case 174:
|
||||
case 176:
|
||||
return aarch64_ins_sve_reglist (self, info, code, inst);
|
||||
default: assert (0); abort ();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -606,6 +606,30 @@ aarch64_ins_addr_simm (const aarch64_operand *self,
|
|||
return NULL;
|
||||
}
|
||||
|
||||
/* Encode the address operand for e.g. LDRAA <Xt>, [<Xn|SP>{, #<simm>}]. */
|
||||
const char *
|
||||
aarch64_ins_addr_simm10 (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info,
|
||||
aarch64_insn *code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
int imm;
|
||||
|
||||
/* Rn */
|
||||
insert_field (self->fields[0], code, info->addr.base_regno, 0);
|
||||
/* simm10 */
|
||||
imm = info->addr.offset.imm >> 3;
|
||||
insert_field (self->fields[1], code, imm >> 9, 0);
|
||||
insert_field (self->fields[2], code, imm, 0);
|
||||
/* writeback */
|
||||
if (info->addr.writeback)
|
||||
{
|
||||
assert (info->addr.preind == 1 && info->addr.postind == 0);
|
||||
insert_field (self->fields[3], code, 1, 0);
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<pimm>}]. */
|
||||
const char *
|
||||
aarch64_ins_addr_uimm12 (const aarch64_operand *self,
|
||||
|
|
|
|||
|
|
@ -59,6 +59,7 @@ AARCH64_DECL_OPD_INSERTER (ins_ft);
|
|||
AARCH64_DECL_OPD_INSERTER (ins_addr_simple);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_addr_regoff);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_addr_simm);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_addr_simm10);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_addr_uimm12);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_simd_addr_post);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_cond);
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -981,6 +981,27 @@ aarch64_ext_addr_uimm12 (const aarch64_operand *self, aarch64_opnd_info *info,
|
|||
return 1;
|
||||
}
|
||||
|
||||
/* Decode the address operand for e.g. LDRAA <Xt>, [<Xn|SP>{, #<simm>}]. */
|
||||
int
|
||||
aarch64_ext_addr_simm10 (const aarch64_operand *self, aarch64_opnd_info *info,
|
||||
aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED)
|
||||
{
|
||||
aarch64_insn imm;
|
||||
|
||||
info->qualifier = get_expected_qualifier (inst, info->idx);
|
||||
/* Rn */
|
||||
info->addr.base_regno = extract_field (self->fields[0], code, 0);
|
||||
/* simm10 */
|
||||
imm = extract_fields (code, 0, 2, self->fields[1], self->fields[2]);
|
||||
info->addr.offset.imm = sign_extend (imm, 9) << 3;
|
||||
if (extract_field (self->fields[3], code, 0) == 1) {
|
||||
info->addr.writeback = 1;
|
||||
info->addr.preind = 1;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Decode the address operand for e.g.
|
||||
LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>. */
|
||||
int
|
||||
|
|
|
|||
|
|
@ -81,6 +81,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_ft);
|
|||
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simple);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_regoff);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simm);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simm10);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_addr_uimm12);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_simd_addr_post);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_cond);
|
||||
|
|
|
|||
|
|
@ -102,6 +102,7 @@ const struct aarch64_operand aarch64_operands[] =
|
|||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm7,FLD_index2}, "an address with 7-bit signed immediate offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit signed immediate offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit negative or unaligned immediate offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index}, "an address with 10-bit scaled, signed immediate offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "ADDR_UIMM12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm12}, "an address with scaled, unsigned immediate offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with base register (no offset)"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_POST", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a post-indexed address with immediate or register increment"},
|
||||
|
|
@ -233,24 +234,24 @@ static const unsigned op_enum_table [] =
|
|||
896,
|
||||
902,
|
||||
903,
|
||||
946,
|
||||
947,
|
||||
948,
|
||||
949,
|
||||
950,
|
||||
951,
|
||||
12,
|
||||
627,
|
||||
628,
|
||||
1141,
|
||||
1143,
|
||||
1145,
|
||||
953,
|
||||
1147,
|
||||
955,
|
||||
1146,
|
||||
1144,
|
||||
1142,
|
||||
311,
|
||||
615,
|
||||
626,
|
||||
625,
|
||||
951,
|
||||
953,
|
||||
622,
|
||||
619,
|
||||
611,
|
||||
|
|
@ -260,7 +261,7 @@ static const unsigned op_enum_table [] =
|
|||
621,
|
||||
623,
|
||||
624,
|
||||
961,
|
||||
963,
|
||||
655,
|
||||
658,
|
||||
661,
|
||||
|
|
@ -277,17 +278,17 @@ static const unsigned op_enum_table [] =
|
|||
382,
|
||||
404,
|
||||
406,
|
||||
1206,
|
||||
1211,
|
||||
1204,
|
||||
1203,
|
||||
1207,
|
||||
1214,
|
||||
1216,
|
||||
1217,
|
||||
1208,
|
||||
1213,
|
||||
1219,
|
||||
1206,
|
||||
1205,
|
||||
1209,
|
||||
1216,
|
||||
1218,
|
||||
1219,
|
||||
1215,
|
||||
1221,
|
||||
1220,
|
||||
};
|
||||
|
||||
/* Given the opcode enumerator OP, return the pointer to the corresponding
|
||||
|
|
|
|||
|
|
@ -253,6 +253,7 @@ const aarch64_field fields[] =
|
|||
{ 16, 6 }, /* immr: in bitfield and logical immediate instructions. */
|
||||
{ 16, 3 }, /* immb: in advsimd shift by immediate instructions. */
|
||||
{ 19, 4 }, /* immh: in advsimd shift by immediate instructions. */
|
||||
{ 22, 1 }, /* S: in LDRAA and LDRAB instructions. */
|
||||
{ 22, 1 }, /* N: in logical (immediate) instructions. */
|
||||
{ 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */
|
||||
{ 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */
|
||||
|
|
@ -1528,6 +1529,14 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
|
|||
return 0;
|
||||
}
|
||||
break;
|
||||
case ldst_imm10:
|
||||
if (opnd->addr.writeback == 1 && opnd->addr.preind != 1)
|
||||
{
|
||||
set_syntax_error (mismatch_detail, idx,
|
||||
_("unexpected address writeback"));
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
case ldst_imm9:
|
||||
case ldstpair_indexed:
|
||||
case asisdlsep:
|
||||
|
|
@ -1584,6 +1593,20 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
|
|||
_("negative or unaligned offset expected"));
|
||||
return 0;
|
||||
|
||||
case AARCH64_OPND_ADDR_SIMM10:
|
||||
/* Scaled signed 10 bits immediate offset. */
|
||||
if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4088))
|
||||
{
|
||||
set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4088);
|
||||
return 0;
|
||||
}
|
||||
if (!value_aligned_p (opnd->addr.offset.imm, 8))
|
||||
{
|
||||
set_unaligned_error (mismatch_detail, idx, 8);
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SIMD_ADDR_POST:
|
||||
/* AdvSIMD load/store multiple structures, post-index. */
|
||||
assert (idx == 1);
|
||||
|
|
@ -3408,6 +3431,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
|||
case AARCH64_OPND_ADDR_SIMM7:
|
||||
case AARCH64_OPND_ADDR_SIMM9:
|
||||
case AARCH64_OPND_ADDR_SIMM9_2:
|
||||
case AARCH64_OPND_ADDR_SIMM10:
|
||||
case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
|
||||
case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
|
||||
case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
|
||||
|
|
|
|||
|
|
@ -80,6 +80,7 @@ enum aarch64_field_kind
|
|||
FLD_immr,
|
||||
FLD_immb,
|
||||
FLD_immh,
|
||||
FLD_S_imm10,
|
||||
FLD_N,
|
||||
FLD_index,
|
||||
FLD_index2,
|
||||
|
|
|
|||
|
|
@ -1094,6 +1094,12 @@
|
|||
QLF3(W, X, NIL), \
|
||||
}
|
||||
|
||||
/* e.g. LDRAA <Xt>, [<Xn|SP>{,#imm}]. */
|
||||
#define QL_X1NIL \
|
||||
{ \
|
||||
QLF2(X, NIL), \
|
||||
}
|
||||
|
||||
/* e.g. LDXP <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */
|
||||
#define QL_R2NIL \
|
||||
{ \
|
||||
|
|
@ -2916,6 +2922,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
|||
CORE_INSN ("ldur", 0xb8400000, 0xbfe00c00, ldst_unscaled, OP_LDUR, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q),
|
||||
CORE_INSN ("ldursw", 0xb8800000, 0xffe00c00, ldst_unscaled, OP_LDURSW, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
|
||||
CORE_INSN ("prfum", 0xf8800000, 0xffe00c00, ldst_unscaled, OP_PRFUM, OP2 (PRFOP, ADDR_SIMM9), QL_LDST_PRFM, 0),
|
||||
/* Load/store register (scaled signed immediate). */
|
||||
V8_3_INSN ("ldraa", 0xf8200400, 0xffa00400, ldst_imm10, OP2 (Rt, ADDR_SIMM10), QL_X1NIL, 0),
|
||||
V8_3_INSN ("ldrab", 0xf8a00400, 0xffa00400, ldst_imm10, OP2 (Rt, ADDR_SIMM10), QL_X1NIL, 0),
|
||||
/* Load/store exclusive. */
|
||||
CORE_INSN ("stxrb", 0x8007c00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0),
|
||||
CORE_INSN ("stlxrb", 0x800fc00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0),
|
||||
|
|
@ -4117,6 +4126,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
|
|||
"an address with 9-bit signed immediate offset") \
|
||||
Y(ADDRESS, addr_simm, "ADDR_SIMM9_2", 0, F(FLD_imm9,FLD_index), \
|
||||
"an address with 9-bit negative or unaligned immediate offset") \
|
||||
Y(ADDRESS, addr_simm10, "ADDR_SIMM10", 0, F(FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index),\
|
||||
"an address with 10-bit scaled, signed immediate offset") \
|
||||
Y(ADDRESS, addr_uimm12, "ADDR_UIMM12", 0, F(FLD_Rn,FLD_imm12), \
|
||||
"an address with scaled, unsigned immediate offset") \
|
||||
Y(ADDRESS, addr_simple, "SIMD_ADDR_SIMPLE", 0, F(), \
|
||||
|
|
|
|||
Loading…
Reference in New Issue