x86-64: fix handling of PUSH/POP of segment register
Commit 21df382b91 ("x86: fold SReg{2,3}") went too far: Folding 64-bit
PUSH/POP templates into non-64-bit ones isn't correct, due to the
different operand widths, and hence suffixes permitted. Restore the
separate templates.
Add tests of PUSH/POP with q suffix and %fs/%gs operands to the
testsuite. While doing so also add PUSHF/POPF ones _without_ suffix.
This commit is contained in:
Jan Beulich
parent
4c51dacacf
commit
3f9aad111c
@ -1,3 +1,12 @@
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2018-09-20 Jan Beulich <jbeulich@suse.com>
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PR gas/25012
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* config/tc-i386.c (process_operands): Adjust handling of
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PUSH/POP of segment registers.
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* testsuite/gas/i386/x86-64-opcode.s: Add PUSHq/POPq case with
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%fs/%gs operands. Add PUSHF/POPF case without suffix.
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* testsuite/gas/i386/x86-64-opcode.d: Adjust expectations.
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2019-09-19 Matthew Malcomson <matthew.malcomson@arm.com>
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* NEWS: Add SVE2 and TME entries.
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@ -7010,14 +7010,14 @@ duplicate:
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if (flag_code != CODE_64BIT
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? i.tm.base_opcode == POP_SEG_SHORT
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&& i.op[0].regs->reg_num == 1
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: (i.tm.base_opcode | 1) == POP_SEG_SHORT
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: (i.tm.base_opcode | 1) == POP_SEG386_SHORT
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&& i.op[0].regs->reg_num < 4)
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{
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as_bad (_("you can't `%s %s%s'"),
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i.tm.name, register_prefix, i.op[0].regs->reg_name);
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return 0;
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}
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if ( i.op[0].regs->reg_num > 3 )
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if ( i.op[0].regs->reg_num > 3 && i.tm.opcode_length == 1 )
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{
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i.tm.base_opcode ^= POP_SEG_SHORT ^ POP_SEG386_SHORT;
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i.tm.opcode_length = 2;
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@ -255,12 +255,18 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 41 8f 00 popq \(%r8\)
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[ ]*[a-f0-9]+: 8f 00 popq \(%rax\)
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[ ]*[a-f0-9]+: 0f a1 popq %fs
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[ ]*[a-f0-9]+: 0f a1 popq %fs
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[ ]*[a-f0-9]+: 0f a9 popq %gs
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[ ]*[a-f0-9]+: 0f a9 popq %gs
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[ ]*[a-f0-9]+: 9d popfq
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[ ]*[a-f0-9]+: 9d popfq
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[ ]*[a-f0-9]+: 41 ff 30 pushq \(%r8\)
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[ ]*[a-f0-9]+: ff 30 pushq \(%rax\)
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[ ]*[a-f0-9]+: 0f a0 pushq %fs
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[ ]*[a-f0-9]+: 0f a0 pushq %fs
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[ ]*[a-f0-9]+: 0f a8 pushq %gs
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[ ]*[a-f0-9]+: 0f a8 pushq %gs
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[ ]*[a-f0-9]+: 9c pushfq
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[ ]*[a-f0-9]+: 9c pushfq
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[ ]*[a-f0-9]+: 0f 77 emms
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[ ]*[a-f0-9]+: 0f 0e femms
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@ -323,15 +323,21 @@
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POPq (%r8) # -- -- -- 41 8F 00 ; REX to access upper reg.
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POPq (%rax) # -- -- -- -- 8F 00
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POP %fs # -- -- -- -- 0F A1
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POPq %fs # -- -- -- -- 0F A1
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POP %gs # -- -- -- -- 0F A9
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POPFQ # -- -- -- -- 9D
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POPq %gs # -- -- -- -- 0F A9
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POPF # -- -- -- -- 9D
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POPFq # -- -- -- -- 9D
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# PUSH
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PUSHq (%r8) # -- -- -- 41 FF 30 ; REX to access upper reg.
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PUSHq (%rax) # -- -- -- -- FF 30
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PUSH %fs # -- -- -- -- 0F A0
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PUSHq %fs # -- -- -- -- 0F A0
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PUSH %gs # -- -- -- -- 0F A8
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PUSHFQ # -- -- -- -- 9C
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PUSHq %gs # -- -- -- -- 0F A8
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PUSHF # -- -- -- -- 9C
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PUSHFq # -- -- -- -- 9C
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@ -1,3 +1,10 @@
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2018-09-20 Jan Beulich <jbeulich@suse.com>
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PR gas/25012
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* i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
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with SReg operand.
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* i386-tbl.h: Re-generate.
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2019-09-18 Alan Modra <amodra@gmail.com>
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* arc-ext.c: Update throughout for bfd section macro changes.
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@ -116,22 +116,24 @@ push, 1, 0x50, None, 1, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|N
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push, 1, 0xff, 0x6, 1, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex }
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push, 1, 0x6a, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8S }
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push, 1, 0x68, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16|Imm32 }
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push, 1, 0x6, None, 1, 0, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg }
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push, 1, 0x6, None, 1, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg }
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// In 64bit mode, the operand size is implicitly 64bit.
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push, 1, 0x50, None, 1, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64 }
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push, 1, 0xff, 0x6, 1, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex }
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push, 1, 0x6a, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8S }
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push, 1, 0x68, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Imm16|Imm32S }
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push, 1, 0xfa0, None, 2, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { SReg }
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pusha, 0, 0x60, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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// Pop instructions.
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pop, 1, 0x58, None, 1, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 }
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pop, 1, 0x8f, 0x0, 1, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex }
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pop, 1, 0x7, None, 1, 0, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg }
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pop, 1, 0x7, None, 1, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg }
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// In 64bit mode, the operand size is implicitly 64bit.
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pop, 1, 0x58, None, 1, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64 }
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pop, 1, 0x8f, 0x0, 1, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex }
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pop, 1, 0xfa1, None, 2, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { SReg }
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popa, 0, 0x61, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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@ -635,7 +635,7 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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0, 0, 0, 0, 0, 0, 0, 1, 0 } },
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{ 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1,
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1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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@ -694,6 +694,19 @@ const insn_template i386_optab[] =
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0 },
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
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{ "push", 1, 0xfa0, None, 2,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 1, 0, 0 } },
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{ 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 0,
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1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0 },
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{ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
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{ "pusha", 0, 0x60, None, 1,
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{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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@ -739,7 +752,7 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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0, 0, 0, 0, 0, 0, 0, 1, 0 } },
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{ 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1,
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1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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@ -772,6 +785,19 @@ const insn_template i386_optab[] =
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0 },
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{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0,
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0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0 } } } },
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{ "pop", 1, 0xfa1, None, 2,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 1, 0, 0 } },
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{ 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 0,
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1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0 },
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{ { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
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{ "popa", 0, 0x61, None, 1,
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{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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