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Obsolete the d30v.

This commit is contained in:
Andrew Cagney 2002-07-14 00:15:20 +00:00
parent f971e29ff1
commit 3fbeef0be8
23 changed files with 5941 additions and 5946 deletions
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8
gdb/ChangeLog
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@ -1,3 +1,11 @@
2002-07-13 Andrew Cagney <ac131313@redhat.com>
* MAINTAINERS: Note that d30v / d30v-elf has been made obsolete.
* configure.tgt: Mark d30v-*-* as obsolete.
* d30v-tdep.c: Mark file as obsolete.
* config/d30v/d30v.mt: Ditto.
* config/d30v/tm-d30v.h: Ditto.
2002-07-13 Aidan Skinner <aidan@velvet.net>
* ada-tasks.c (add_task_entry): replace calls to

4
gdb/MAINTAINERS
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@ -78,9 +78,7 @@ maintainer works with the native maintainer when resolving API issues.
d10v --target=d10v-elf ,-Werror
Maintenance only
d30v --target=d30v-elf ,-Werror
Maintenance only
OBSOLETE candidate, not multi-arch
d30v (--target=d30v-elf OBSOLETE)
djgpp --target=i586-pc-msdosdjgpp ,-Werror
(See native and host)

10
gdb/config/d30v/d30v.mt
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@ -1,5 +1,5 @@
# Target: Mitsubishi D30V processor
TDEPFILES= d30v-tdep.o
TM_FILE= tm-d30v.h
SIM_OBS= remote-sim.o
SIM= ../sim/d30v/libsim.a
# OBSOLETE # Target: Mitsubishi D30V processor
# OBSOLETE TDEPFILES= d30v-tdep.o
# OBSOLETE TM_FILE= tm-d30v.h
# OBSOLETE SIM_OBS= remote-sim.o
# OBSOLETE SIM= ../sim/d30v/libsim.a

646
gdb/config/d30v/tm-d30v.h
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@ -1,323 +1,323 @@
/* Target-specific definition for the Mitsubishi D30V
Copyright 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
#ifndef TM_D30V_H
#define TM_D30V_H
#include "regcache.h"
/* Offset from address of function to start of its code.
Zero on most machines. */
#define FUNCTION_START_OFFSET 0
/* these are the addresses the D30V-EVA board maps data */
/* and instruction memory to. */
#define DMEM_START 0x20000000
#define IMEM_START 0x00000000 /* was 0x10000000 */
#define STACK_START 0x20007ffe
/* Forward decls for prototypes */
struct frame_info;
struct frame_saved_regs;
struct type;
struct value;
/* Advance PC across any function entry prologue instructions
to reach some "real" code. */
extern CORE_ADDR d30v_skip_prologue (CORE_ADDR);
#define SKIP_PROLOGUE(ip) (d30v_skip_prologue (ip))
/* Stack grows downward. */
#define INNER_THAN(lhs,rhs) ((lhs) < (rhs))
/* for a breakpoint, use "dbt || nop" */
#define BREAKPOINT {0x00, 0xb0, 0x00, 0x00,\
0x00, 0xf0, 0x00, 0x00}
/* If your kernel resets the pc after the trap happens you may need to
define this before including this file. */
#define DECR_PC_AFTER_BREAK 0
#define REGISTER_NAMES \
{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
"r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
"r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
"r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
"r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
"spi", "spu", \
"psw", "bpsw", "pc", "bpc", "dpsw", "dpc", "cr6", "rpt_c", \
"rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "eit_vb",\
"int_s", "int_m", "a0", "a1" \
}
#define NUM_REGS 86
/* Register numbers of various important registers.
Note that some of these values are "real" register numbers,
and correspond to the general registers of the machine,
and some are "phony" register numbers which are too large
to be actual register numbers as far as the user is concerned
but do serve to get the desired values when passed to read_register. */
#define R0_REGNUM 0
#define FP_REGNUM 61
#define LR_REGNUM 62
#define SP_REGNUM 63
#define SPI_REGNUM 64 /* Interrupt stack pointer */
#define SPU_REGNUM 65 /* User stack pointer */
#define CREGS_START 66
#define PSW_REGNUM (CREGS_START + 0) /* psw, bpsw, or dpsw??? */
#define PSW_SM (((unsigned long)0x80000000) >> 0) /* Stack mode: 0/SPI */
/* 1/SPU */
#define PSW_EA (((unsigned long)0x80000000) >> 2) /* Execution status */
#define PSW_DB (((unsigned long)0x80000000) >> 3) /* Debug mode */
#define PSW_DS (((unsigned long)0x80000000) >> 4) /* Debug EIT status */
#define PSW_IE (((unsigned long)0x80000000) >> 5) /* Interrupt enable */
#define PSW_RP (((unsigned long)0x80000000) >> 6) /* Repeat enable */
#define PSW_MD (((unsigned long)0x80000000) >> 7) /* Modulo enable */
#define PSW_F0 (((unsigned long)0x80000000) >> 17) /* F0 flag */
#define PSW_F1 (((unsigned long)0x80000000) >> 19) /* F1 flag */
#define PSW_F2 (((unsigned long)0x80000000) >> 21) /* F2 flag */
#define PSW_F3 (((unsigned long)0x80000000) >> 23) /* F3 flag */
#define PSW_S (((unsigned long)0x80000000) >> 25) /* Saturation flag */
#define PSW_V (((unsigned long)0x80000000) >> 27) /* Overflow flag */
#define PSW_VA (((unsigned long)0x80000000) >> 29) /* Accum. overflow */
#define PSW_C (((unsigned long)0x80000000) >> 31) /* Carry/Borrow flag */
#define BPSW_REGNUM (CREGS_START + 1) /* Backup PSW (on interrupt) */
#define PC_REGNUM (CREGS_START + 2) /* pc, bpc, or dpc??? */
#define BPC_REGNUM (CREGS_START + 3) /* Backup PC (on interrupt) */
#define DPSW_REGNUM (CREGS_START + 4) /* Backup PSW (on debug trap) */
#define DPC_REGNUM (CREGS_START + 5) /* Backup PC (on debug trap) */
#define RPT_C_REGNUM (CREGS_START + 7) /* Loop count */
#define RPT_S_REGNUM (CREGS_START + 8) /* Loop start address */
#define RPT_E_REGNUM (CREGS_START + 9) /* Loop end address */
#define MOD_S_REGNUM (CREGS_START + 10)
#define MOD_E_REGNUM (CREGS_START + 11)
#define IBA_REGNUM (CREGS_START + 14) /* Instruction break address */
#define EIT_VB_REGNUM (CREGS_START + 15) /* Vector base address */
#define INT_S_REGNUM (CREGS_START + 16) /* Interrupt status */
#define INT_M_REGNUM (CREGS_START + 17) /* Interrupt mask */
#define A0_REGNUM 84
#define A1_REGNUM 85
/* Say how much memory is needed to store a copy of the register set */
#define REGISTER_BYTES ((NUM_REGS - 2) * 4 + 2 * 8)
/* Index within `registers' of the first byte of the space for
register N. */
#define REGISTER_BYTE(N) \
( ((N) >= A0_REGNUM) ? ( ((N) - A0_REGNUM) * 8 + A0_REGNUM * 4 ) : ((N) * 4) )
/* Number of bytes of storage in the actual machine representation
for register N. */
#define REGISTER_RAW_SIZE(N) ( ((N) >= A0_REGNUM) ? 8 : 4 )
/* Number of bytes of storage in the program's representation
for register N. */
#define REGISTER_VIRTUAL_SIZE(N) REGISTER_RAW_SIZE(N)
/* Largest value REGISTER_RAW_SIZE can have. */
#define MAX_REGISTER_RAW_SIZE 8
/* Largest value REGISTER_VIRTUAL_SIZE can have. */
#define MAX_REGISTER_VIRTUAL_SIZE 8
/* Return the GDB type object for the "standard" data type
of data in register N. */
#define REGISTER_VIRTUAL_TYPE(N) \
( ((N) < A0_REGNUM ) ? builtin_type_long : builtin_type_long_long)
/* Writing to r0 is a noop (not an error or exception or anything like
that, however). */
#define CANNOT_STORE_REGISTER(regno) ((regno) == R0_REGNUM)
void d30v_do_registers_info (int regnum, int fpregs);
#define DO_REGISTERS_INFO d30v_do_registers_info
/* Store the address of the place in which to copy the structure the
subroutine will return. This is called from call_function.
We store structs through a pointer passed in R2 */
#define STORE_STRUCT_RETURN(ADDR, SP) \
{ write_register (2, (ADDR)); }
/* Write into appropriate registers a function return value
of type TYPE, given in virtual format.
Things always get returned in R2/R3 */
#define STORE_RETURN_VALUE(TYPE,VALBUF) \
write_register_bytes (REGISTER_BYTE(2), VALBUF, TYPE_LENGTH (TYPE))
/* Extract from an array REGBUF containing the (raw) register state
the address in which a function should return its structure value,
as a CORE_ADDR (or an expression that can be used as one). */
#define DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) (((CORE_ADDR *)(REGBUF))[2])
/* Define other aspects of the stack frame.
we keep a copy of the worked out return pc lying around, since it
is a useful bit of info */
#define EXTRA_FRAME_INFO \
CORE_ADDR return_pc; \
CORE_ADDR dummy; \
int frameless; \
int size;
#define INIT_EXTRA_FRAME_INFO(fromleaf, fi) \
d30v_init_extra_frame_info(fromleaf, fi)
extern void d30v_init_extra_frame_info (int fromleaf, struct frame_info *fi);
/* A macro that tells us whether the function invocation represented
by FI does not have a frame on the stack associated with it. If it
does not, FRAMELESS is set to 1, else 0. */
#define FRAMELESS_FUNCTION_INVOCATION(FI) \
(frameless_look_for_prologue (FI))
CORE_ADDR d30v_frame_chain (struct frame_info *frame);
#define FRAME_CHAIN(FRAME) d30v_frame_chain(FRAME)
extern int d30v_frame_chain_valid (CORE_ADDR, struct frame_info *);
#define FRAME_CHAIN_VALID(chain, thisframe) d30v_frame_chain_valid (chain, thisframe)
#define FRAME_SAVED_PC(FRAME) ((FRAME)->return_pc)
#define FRAME_ARGS_ADDRESS(fi) (fi)->frame
#define FRAME_LOCALS_ADDRESS(fi) (fi)->frame
void d30v_init_frame_pc (int fromleaf, struct frame_info *prev);
#define INIT_FRAME_PC_FIRST(fromleaf, prev) d30v_init_frame_pc(fromleaf, prev)
#define INIT_FRAME_PC(fromleaf, prev) /* nada */
/* Immediately after a function call, return the saved pc. We can't */
/* use frame->return_pc beause that is determined by reading R62 off the */
/* stack and that may not be written yet. */
#define SAVED_PC_AFTER_CALL(frame) (read_register(LR_REGNUM))
/* Set VAL to the number of args passed to frame described by FI.
Can set VAL to -1, meaning no way to tell. */
/* We can't tell how many args there are */
#define FRAME_NUM_ARGS(fi) (-1)
/* Return number of bytes at start of arglist that are not really args. */
#define FRAME_ARGS_SKIP 0
/* Put here the code to store, into a struct frame_saved_regs,
the addresses of the saved registers of frame described by FRAME_INFO.
This includes special registers such as pc and fp saved in special
ways in the stack frame. sp is even more special:
the address we return for it IS the sp for the next frame. */
#define FRAME_FIND_SAVED_REGS(frame_info, frame_saved_regs) \
d30v_frame_find_saved_regs(frame_info, &(frame_saved_regs))
extern void d30v_frame_find_saved_regs (struct frame_info *,
struct frame_saved_regs *);
/* DUMMY FRAMES. Need these to support inferior function calls.
They work like this on D30V:
First we set a breakpoint at 0 or __start.
Then we push all the registers onto the stack.
Then put the function arguments in the proper registers and set r13
to our breakpoint address.
Finally call the function directly.
When it hits the breakpoint, clear the break point and pop the old
register contents off the stack. */
#define CALL_DUMMY { 0 }
#define PUSH_DUMMY_FRAME
#define CALL_DUMMY_START_OFFSET 0
#define CALL_DUMMY_LOCATION AT_ENTRY_POINT
#define CALL_DUMMY_BREAKPOINT_OFFSET (0)
extern CORE_ADDR d30v_call_dummy_address (void);
#define CALL_DUMMY_ADDRESS() d30v_call_dummy_address()
#define FIX_CALL_DUMMY(dummyname, pc, fun, nargs, args, type, gcc_p) \
sp = d30v_fix_call_dummy (dummyname, pc, fun, nargs, args, type, gcc_p)
#define PC_IN_CALL_DUMMY(pc, sp, frame_address) ( pc == IMEM_START + 4 )
extern CORE_ADDR d30v_fix_call_dummy (char *, CORE_ADDR, CORE_ADDR,
int, struct value **,
struct type *, int);
#define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
(d30v_push_arguments((nargs), (args), (sp), (struct_return), (struct_addr)))
extern CORE_ADDR d30v_push_arguments (int, struct value **, CORE_ADDR, int,
CORE_ADDR);
/* Extract from an array REGBUF containing the (raw) register state
a function return value of type TYPE, and copy that, in virtual format,
into VALBUF. */
#define DEPRECATED_EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
d30v_extract_return_value(TYPE, REGBUF, VALBUF)
extern void d30v_extract_return_value (struct type *, char *, char *);
/* Discard from the stack the innermost frame,
restoring all saved registers. */
#define POP_FRAME d30v_pop_frame();
extern void d30v_pop_frame (void);
#define REGISTER_SIZE 4
/* Need to handle SP special, as we need to select between spu and spi. */
#if 0 /* XXX until the simulator is fixed */
#define TARGET_READ_SP() ((read_register (PSW_REGNUM) & PSW_SM) \
? read_register (SPU_REGNUM) \
: read_register (SPI_REGNUM))
#define TARGET_WRITE_SP(val) ((read_register (PSW_REGNUM) & PSW_SM) \
? write_register (SPU_REGNUM, (val)) \
: write_register (SPI_REGNUM, (val)))
#endif
#define STACK_ALIGN(len) (((len) + 7 ) & ~7)
/* Turn this on to cause remote-sim.c to use sim_set/clear_breakpoint. */
#define SIM_HAS_BREAKPOINTS
#endif /* TM_D30V_H */
/* OBSOLETE /* Target-specific definition for the Mitsubishi D30V */
/* OBSOLETE Copyright 1997, 1998, 1999, 2000 Free Software Foundation, Inc. */
/* OBSOLETE */
/* OBSOLETE This file is part of GDB. */
/* OBSOLETE */
/* OBSOLETE This program is free software; you can redistribute it and/or modify */
/* OBSOLETE it under the terms of the GNU General Public License as published by */
/* OBSOLETE the Free Software Foundation; either version 2 of the License, or */
/* OBSOLETE (at your option) any later version. */
/* OBSOLETE */
/* OBSOLETE This program is distributed in the hope that it will be useful, */
/* OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of */
/* OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
/* OBSOLETE GNU General Public License for more details. */
/* OBSOLETE */
/* OBSOLETE You should have received a copy of the GNU General Public License */
/* OBSOLETE along with this program; if not, write to the Free Software */
/* OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330, */
/* OBSOLETE Boston, MA 02111-1307, USA. */ */
/* OBSOLETE */
/* OBSOLETE #ifndef TM_D30V_H */
/* OBSOLETE #define TM_D30V_H */
/* OBSOLETE */
/* OBSOLETE #include "regcache.h" */
/* OBSOLETE */
/* OBSOLETE /* Offset from address of function to start of its code. */
/* OBSOLETE Zero on most machines. */ */
/* OBSOLETE */
/* OBSOLETE #define FUNCTION_START_OFFSET 0 */
/* OBSOLETE */
/* OBSOLETE /* these are the addresses the D30V-EVA board maps data */ */
/* OBSOLETE /* and instruction memory to. */ */
/* OBSOLETE */
/* OBSOLETE #define DMEM_START 0x20000000 */
/* OBSOLETE #define IMEM_START 0x00000000 /* was 0x10000000 */ */
/* OBSOLETE #define STACK_START 0x20007ffe */
/* OBSOLETE */
/* OBSOLETE /* Forward decls for prototypes */ */
/* OBSOLETE struct frame_info; */
/* OBSOLETE struct frame_saved_regs; */
/* OBSOLETE struct type; */
/* OBSOLETE struct value; */
/* OBSOLETE */
/* OBSOLETE /* Advance PC across any function entry prologue instructions */
/* OBSOLETE to reach some "real" code. */ */
/* OBSOLETE */
/* OBSOLETE extern CORE_ADDR d30v_skip_prologue (CORE_ADDR); */
/* OBSOLETE #define SKIP_PROLOGUE(ip) (d30v_skip_prologue (ip)) */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE /* Stack grows downward. */ */
/* OBSOLETE #define INNER_THAN(lhs,rhs) ((lhs) < (rhs)) */
/* OBSOLETE */
/* OBSOLETE /* for a breakpoint, use "dbt || nop" */ */
/* OBSOLETE #define BREAKPOINT {0x00, 0xb0, 0x00, 0x00,\ */
/* OBSOLETE 0x00, 0xf0, 0x00, 0x00} */
/* OBSOLETE */
/* OBSOLETE /* If your kernel resets the pc after the trap happens you may need to */
/* OBSOLETE define this before including this file. */ */
/* OBSOLETE #define DECR_PC_AFTER_BREAK 0 */
/* OBSOLETE */
/* OBSOLETE #define REGISTER_NAMES \ */
/* OBSOLETE { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ */
/* OBSOLETE "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ */
/* OBSOLETE "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ */
/* OBSOLETE "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \ */
/* OBSOLETE "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \ */
/* OBSOLETE "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \ */
/* OBSOLETE "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \ */
/* OBSOLETE "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \ */
/* OBSOLETE "spi", "spu", \ */
/* OBSOLETE "psw", "bpsw", "pc", "bpc", "dpsw", "dpc", "cr6", "rpt_c", \ */
/* OBSOLETE "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "eit_vb",\ */
/* OBSOLETE "int_s", "int_m", "a0", "a1" \ */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE #define NUM_REGS 86 */
/* OBSOLETE */
/* OBSOLETE /* Register numbers of various important registers. */
/* OBSOLETE Note that some of these values are "real" register numbers, */
/* OBSOLETE and correspond to the general registers of the machine, */
/* OBSOLETE and some are "phony" register numbers which are too large */
/* OBSOLETE to be actual register numbers as far as the user is concerned */
/* OBSOLETE but do serve to get the desired values when passed to read_register. */ */
/* OBSOLETE */
/* OBSOLETE #define R0_REGNUM 0 */
/* OBSOLETE #define FP_REGNUM 61 */
/* OBSOLETE #define LR_REGNUM 62 */
/* OBSOLETE #define SP_REGNUM 63 */
/* OBSOLETE #define SPI_REGNUM 64 /* Interrupt stack pointer */ */
/* OBSOLETE #define SPU_REGNUM 65 /* User stack pointer */ */
/* OBSOLETE #define CREGS_START 66 */
/* OBSOLETE */
/* OBSOLETE #define PSW_REGNUM (CREGS_START + 0) /* psw, bpsw, or dpsw??? */ */
/* OBSOLETE #define PSW_SM (((unsigned long)0x80000000) >> 0) /* Stack mode: 0/SPI */ */
/* OBSOLETE /* 1/SPU */ */
/* OBSOLETE #define PSW_EA (((unsigned long)0x80000000) >> 2) /* Execution status */ */
/* OBSOLETE #define PSW_DB (((unsigned long)0x80000000) >> 3) /* Debug mode */ */
/* OBSOLETE #define PSW_DS (((unsigned long)0x80000000) >> 4) /* Debug EIT status */ */
/* OBSOLETE #define PSW_IE (((unsigned long)0x80000000) >> 5) /* Interrupt enable */ */
/* OBSOLETE #define PSW_RP (((unsigned long)0x80000000) >> 6) /* Repeat enable */ */
/* OBSOLETE #define PSW_MD (((unsigned long)0x80000000) >> 7) /* Modulo enable */ */
/* OBSOLETE #define PSW_F0 (((unsigned long)0x80000000) >> 17) /* F0 flag */ */
/* OBSOLETE #define PSW_F1 (((unsigned long)0x80000000) >> 19) /* F1 flag */ */
/* OBSOLETE #define PSW_F2 (((unsigned long)0x80000000) >> 21) /* F2 flag */ */
/* OBSOLETE #define PSW_F3 (((unsigned long)0x80000000) >> 23) /* F3 flag */ */
/* OBSOLETE #define PSW_S (((unsigned long)0x80000000) >> 25) /* Saturation flag */ */
/* OBSOLETE #define PSW_V (((unsigned long)0x80000000) >> 27) /* Overflow flag */ */
/* OBSOLETE #define PSW_VA (((unsigned long)0x80000000) >> 29) /* Accum. overflow */ */
/* OBSOLETE #define PSW_C (((unsigned long)0x80000000) >> 31) /* Carry/Borrow flag */ */
/* OBSOLETE */
/* OBSOLETE #define BPSW_REGNUM (CREGS_START + 1) /* Backup PSW (on interrupt) */ */
/* OBSOLETE #define PC_REGNUM (CREGS_START + 2) /* pc, bpc, or dpc??? */ */
/* OBSOLETE #define BPC_REGNUM (CREGS_START + 3) /* Backup PC (on interrupt) */ */
/* OBSOLETE #define DPSW_REGNUM (CREGS_START + 4) /* Backup PSW (on debug trap) */ */
/* OBSOLETE #define DPC_REGNUM (CREGS_START + 5) /* Backup PC (on debug trap) */ */
/* OBSOLETE #define RPT_C_REGNUM (CREGS_START + 7) /* Loop count */ */
/* OBSOLETE #define RPT_S_REGNUM (CREGS_START + 8) /* Loop start address */ */
/* OBSOLETE #define RPT_E_REGNUM (CREGS_START + 9) /* Loop end address */ */
/* OBSOLETE #define MOD_S_REGNUM (CREGS_START + 10) */
/* OBSOLETE #define MOD_E_REGNUM (CREGS_START + 11) */
/* OBSOLETE #define IBA_REGNUM (CREGS_START + 14) /* Instruction break address */ */
/* OBSOLETE #define EIT_VB_REGNUM (CREGS_START + 15) /* Vector base address */ */
/* OBSOLETE #define INT_S_REGNUM (CREGS_START + 16) /* Interrupt status */ */
/* OBSOLETE #define INT_M_REGNUM (CREGS_START + 17) /* Interrupt mask */ */
/* OBSOLETE #define A0_REGNUM 84 */
/* OBSOLETE #define A1_REGNUM 85 */
/* OBSOLETE */
/* OBSOLETE /* Say how much memory is needed to store a copy of the register set */ */
/* OBSOLETE #define REGISTER_BYTES ((NUM_REGS - 2) * 4 + 2 * 8) */
/* OBSOLETE */
/* OBSOLETE /* Index within `registers' of the first byte of the space for */
/* OBSOLETE register N. */ */
/* OBSOLETE */
/* OBSOLETE #define REGISTER_BYTE(N) \ */
/* OBSOLETE ( ((N) >= A0_REGNUM) ? ( ((N) - A0_REGNUM) * 8 + A0_REGNUM * 4 ) : ((N) * 4) ) */
/* OBSOLETE */
/* OBSOLETE /* Number of bytes of storage in the actual machine representation */
/* OBSOLETE for register N. */ */
/* OBSOLETE */
/* OBSOLETE #define REGISTER_RAW_SIZE(N) ( ((N) >= A0_REGNUM) ? 8 : 4 ) */
/* OBSOLETE */
/* OBSOLETE /* Number of bytes of storage in the program's representation */
/* OBSOLETE for register N. */ */
/* OBSOLETE #define REGISTER_VIRTUAL_SIZE(N) REGISTER_RAW_SIZE(N) */
/* OBSOLETE */
/* OBSOLETE /* Largest value REGISTER_RAW_SIZE can have. */ */
/* OBSOLETE */
/* OBSOLETE #define MAX_REGISTER_RAW_SIZE 8 */
/* OBSOLETE */
/* OBSOLETE /* Largest value REGISTER_VIRTUAL_SIZE can have. */ */
/* OBSOLETE */
/* OBSOLETE #define MAX_REGISTER_VIRTUAL_SIZE 8 */
/* OBSOLETE */
/* OBSOLETE /* Return the GDB type object for the "standard" data type */
/* OBSOLETE of data in register N. */ */
/* OBSOLETE */
/* OBSOLETE #define REGISTER_VIRTUAL_TYPE(N) \ */
/* OBSOLETE ( ((N) < A0_REGNUM ) ? builtin_type_long : builtin_type_long_long) */
/* OBSOLETE */
/* OBSOLETE /* Writing to r0 is a noop (not an error or exception or anything like */
/* OBSOLETE that, however). */ */
/* OBSOLETE */
/* OBSOLETE #define CANNOT_STORE_REGISTER(regno) ((regno) == R0_REGNUM) */
/* OBSOLETE */
/* OBSOLETE void d30v_do_registers_info (int regnum, int fpregs); */
/* OBSOLETE */
/* OBSOLETE #define DO_REGISTERS_INFO d30v_do_registers_info */
/* OBSOLETE */
/* OBSOLETE /* Store the address of the place in which to copy the structure the */
/* OBSOLETE subroutine will return. This is called from call_function. */
/* OBSOLETE */
/* OBSOLETE We store structs through a pointer passed in R2 */ */
/* OBSOLETE */
/* OBSOLETE #define STORE_STRUCT_RETURN(ADDR, SP) \ */
/* OBSOLETE { write_register (2, (ADDR)); } */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE /* Write into appropriate registers a function return value */
/* OBSOLETE of type TYPE, given in virtual format. */
/* OBSOLETE */
/* OBSOLETE Things always get returned in R2/R3 */ */
/* OBSOLETE */
/* OBSOLETE #define STORE_RETURN_VALUE(TYPE,VALBUF) \ */
/* OBSOLETE write_register_bytes (REGISTER_BYTE(2), VALBUF, TYPE_LENGTH (TYPE)) */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE /* Extract from an array REGBUF containing the (raw) register state */
/* OBSOLETE the address in which a function should return its structure value, */
/* OBSOLETE as a CORE_ADDR (or an expression that can be used as one). */ */
/* OBSOLETE #define DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) (((CORE_ADDR *)(REGBUF))[2]) */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE /* Define other aspects of the stack frame. */
/* OBSOLETE we keep a copy of the worked out return pc lying around, since it */
/* OBSOLETE is a useful bit of info */ */
/* OBSOLETE */
/* OBSOLETE #define EXTRA_FRAME_INFO \ */
/* OBSOLETE CORE_ADDR return_pc; \ */
/* OBSOLETE CORE_ADDR dummy; \ */
/* OBSOLETE int frameless; \ */
/* OBSOLETE int size; */
/* OBSOLETE */
/* OBSOLETE #define INIT_EXTRA_FRAME_INFO(fromleaf, fi) \ */
/* OBSOLETE d30v_init_extra_frame_info(fromleaf, fi) */
/* OBSOLETE */
/* OBSOLETE extern void d30v_init_extra_frame_info (int fromleaf, struct frame_info *fi); */
/* OBSOLETE */
/* OBSOLETE /* A macro that tells us whether the function invocation represented */
/* OBSOLETE by FI does not have a frame on the stack associated with it. If it */
/* OBSOLETE does not, FRAMELESS is set to 1, else 0. */ */
/* OBSOLETE */
/* OBSOLETE #define FRAMELESS_FUNCTION_INVOCATION(FI) \ */
/* OBSOLETE (frameless_look_for_prologue (FI)) */
/* OBSOLETE */
/* OBSOLETE CORE_ADDR d30v_frame_chain (struct frame_info *frame); */
/* OBSOLETE #define FRAME_CHAIN(FRAME) d30v_frame_chain(FRAME) */
/* OBSOLETE extern int d30v_frame_chain_valid (CORE_ADDR, struct frame_info *); */
/* OBSOLETE #define FRAME_CHAIN_VALID(chain, thisframe) d30v_frame_chain_valid (chain, thisframe) */
/* OBSOLETE #define FRAME_SAVED_PC(FRAME) ((FRAME)->return_pc) */
/* OBSOLETE #define FRAME_ARGS_ADDRESS(fi) (fi)->frame */
/* OBSOLETE #define FRAME_LOCALS_ADDRESS(fi) (fi)->frame */
/* OBSOLETE */
/* OBSOLETE void d30v_init_frame_pc (int fromleaf, struct frame_info *prev); */
/* OBSOLETE #define INIT_FRAME_PC_FIRST(fromleaf, prev) d30v_init_frame_pc(fromleaf, prev) */
/* OBSOLETE #define INIT_FRAME_PC(fromleaf, prev) /* nada */ */
/* OBSOLETE */
/* OBSOLETE /* Immediately after a function call, return the saved pc. We can't */ */
/* OBSOLETE /* use frame->return_pc beause that is determined by reading R62 off the */ */
/* OBSOLETE /* stack and that may not be written yet. */ */
/* OBSOLETE */
/* OBSOLETE #define SAVED_PC_AFTER_CALL(frame) (read_register(LR_REGNUM)) */
/* OBSOLETE */
/* OBSOLETE /* Set VAL to the number of args passed to frame described by FI. */
/* OBSOLETE Can set VAL to -1, meaning no way to tell. */ */
/* OBSOLETE /* We can't tell how many args there are */ */
/* OBSOLETE */
/* OBSOLETE #define FRAME_NUM_ARGS(fi) (-1) */
/* OBSOLETE */
/* OBSOLETE /* Return number of bytes at start of arglist that are not really args. */ */
/* OBSOLETE */
/* OBSOLETE #define FRAME_ARGS_SKIP 0 */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE /* Put here the code to store, into a struct frame_saved_regs, */
/* OBSOLETE the addresses of the saved registers of frame described by FRAME_INFO. */
/* OBSOLETE This includes special registers such as pc and fp saved in special */
/* OBSOLETE ways in the stack frame. sp is even more special: */
/* OBSOLETE the address we return for it IS the sp for the next frame. */ */
/* OBSOLETE */
/* OBSOLETE #define FRAME_FIND_SAVED_REGS(frame_info, frame_saved_regs) \ */
/* OBSOLETE d30v_frame_find_saved_regs(frame_info, &(frame_saved_regs)) */
/* OBSOLETE */
/* OBSOLETE extern void d30v_frame_find_saved_regs (struct frame_info *, */
/* OBSOLETE struct frame_saved_regs *); */
/* OBSOLETE */
/* OBSOLETE /* DUMMY FRAMES. Need these to support inferior function calls. */
/* OBSOLETE They work like this on D30V: */
/* OBSOLETE First we set a breakpoint at 0 or __start. */
/* OBSOLETE Then we push all the registers onto the stack. */
/* OBSOLETE Then put the function arguments in the proper registers and set r13 */
/* OBSOLETE to our breakpoint address. */
/* OBSOLETE Finally call the function directly. */
/* OBSOLETE When it hits the breakpoint, clear the break point and pop the old */
/* OBSOLETE register contents off the stack. */ */
/* OBSOLETE */
/* OBSOLETE #define CALL_DUMMY { 0 } */
/* OBSOLETE #define PUSH_DUMMY_FRAME */
/* OBSOLETE #define CALL_DUMMY_START_OFFSET 0 */
/* OBSOLETE #define CALL_DUMMY_LOCATION AT_ENTRY_POINT */
/* OBSOLETE #define CALL_DUMMY_BREAKPOINT_OFFSET (0) */
/* OBSOLETE */
/* OBSOLETE extern CORE_ADDR d30v_call_dummy_address (void); */
/* OBSOLETE #define CALL_DUMMY_ADDRESS() d30v_call_dummy_address() */
/* OBSOLETE */
/* OBSOLETE #define FIX_CALL_DUMMY(dummyname, pc, fun, nargs, args, type, gcc_p) \ */
/* OBSOLETE sp = d30v_fix_call_dummy (dummyname, pc, fun, nargs, args, type, gcc_p) */
/* OBSOLETE */
/* OBSOLETE #define PC_IN_CALL_DUMMY(pc, sp, frame_address) ( pc == IMEM_START + 4 ) */
/* OBSOLETE */
/* OBSOLETE extern CORE_ADDR d30v_fix_call_dummy (char *, CORE_ADDR, CORE_ADDR, */
/* OBSOLETE int, struct value **, */
/* OBSOLETE struct type *, int); */
/* OBSOLETE #define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \ */
/* OBSOLETE (d30v_push_arguments((nargs), (args), (sp), (struct_return), (struct_addr))) */
/* OBSOLETE extern CORE_ADDR d30v_push_arguments (int, struct value **, CORE_ADDR, int, */
/* OBSOLETE CORE_ADDR); */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE /* Extract from an array REGBUF containing the (raw) register state */
/* OBSOLETE a function return value of type TYPE, and copy that, in virtual format, */
/* OBSOLETE into VALBUF. */ */
/* OBSOLETE */
/* OBSOLETE #define DEPRECATED_EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \ */
/* OBSOLETE d30v_extract_return_value(TYPE, REGBUF, VALBUF) */
/* OBSOLETE extern void d30v_extract_return_value (struct type *, char *, char *); */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE /* Discard from the stack the innermost frame, */
/* OBSOLETE restoring all saved registers. */ */
/* OBSOLETE #define POP_FRAME d30v_pop_frame(); */
/* OBSOLETE extern void d30v_pop_frame (void); */
/* OBSOLETE */
/* OBSOLETE #define REGISTER_SIZE 4 */
/* OBSOLETE */
/* OBSOLETE /* Need to handle SP special, as we need to select between spu and spi. */ */
/* OBSOLETE #if 0 /* XXX until the simulator is fixed */ */
/* OBSOLETE #define TARGET_READ_SP() ((read_register (PSW_REGNUM) & PSW_SM) \ */
/* OBSOLETE ? read_register (SPU_REGNUM) \ */
/* OBSOLETE : read_register (SPI_REGNUM)) */
/* OBSOLETE */
/* OBSOLETE #define TARGET_WRITE_SP(val) ((read_register (PSW_REGNUM) & PSW_SM) \ */
/* OBSOLETE ? write_register (SPU_REGNUM, (val)) \ */
/* OBSOLETE : write_register (SPI_REGNUM, (val))) */
/* OBSOLETE #endif */
/* OBSOLETE */
/* OBSOLETE #define STACK_ALIGN(len) (((len) + 7 ) & ~7) */
/* OBSOLETE */
/* OBSOLETE /* Turn this on to cause remote-sim.c to use sim_set/clear_breakpoint. */ */
/* OBSOLETE */
/* OBSOLETE #define SIM_HAS_BREAKPOINTS */
/* OBSOLETE */
/* OBSOLETE #endif /* TM_D30V_H */ */

2
gdb/configure.tgt
View File

@ -66,7 +66,7 @@ avr-*-*) gdb_target=avr
cris*) gdb_target=cris ;;
d10v-*-*) gdb_target=d10v ;;
d30v-*-*) gdb_target=d30v ;;
# OBSOLETE d30v-*-*) gdb_target=d30v ;;
h8300-*-*) gdb_target=h8300 ;;
h8500-*-*) gdb_target=h8500 ;;

2730
gdb/d30v-tdep.c
View File

File diff suppressed because it is too large Load Diff

5
sim/ChangeLog
View File

@ -1,3 +1,8 @@
2002-07-13 Andrew Cagney <ac131313@redhat.com>
* configure.in (extra_subdirs): Mark d30v-*-* as obsolete.
* configure: Re-generate.
2002-06-16 Andrew Cagney <ac131313@redhat.com>
* Makefile.in (autoconf-changelog autoheader-changelog): Let name,

5
sim/common/ChangeLog
View File

@ -1,3 +1,8 @@
2002-07-13 Andrew Cagney <ac131313@redhat.com>
* gennltvals.sh (dir): Mark d30v as obsolete.
* nltvals.def: Remove d30v.
2002-06-17 Andrew Cagney <cagney@redhat.com>
* hw-events.c (hw_event_queue_schedule): Initialize `dummy'.

6
sim/common/gennltvals.sh
View File

@ -33,9 +33,9 @@ dir=newlib/libc/sys/d10v/sys target=d10v
$shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \
"syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}"
dir=libgloss target=d30v
$shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \
"syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}"
# OBSOLETE dir=libgloss target=d30v
# OBSOLETE $shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \
# OBSOLETE "syscall.h" 'SYS_[_A-Za-z0-9]*' "${cpp}"
dir=libgloss target=fr30
$shell ${srccom}/gentvals.sh $target sys ${srcroot}/$dir \

24
sim/common/nltvals.def
View File

@ -214,30 +214,6 @@
/* end d10v sys target macros */
#endif
#endif
#ifdef NL_TARGET_d30v
#ifdef sys_defs
/* from syscall.h */
/* begin d30v sys target macros */
{ "SYS_argv", 13 },
{ "SYS_argvlen", 12 },
{ "SYS_chdir", 14 },
{ "SYS_chmod", 16 },
{ "SYS_close", 3 },
{ "SYS_exit", 1 },
{ "SYS_fstat", 10 },
{ "SYS_getpid", 8 },
{ "SYS_kill", 9 },
{ "SYS_lseek", 6 },
{ "SYS_open", 2 },
{ "SYS_read", 4 },
{ "SYS_stat", 15 },
{ "SYS_time", 18 },
{ "SYS_unlink", 7 },
{ "SYS_utime", 17 },
{ "SYS_write", 5 },
/* end d30v sys target macros */
#endif
#endif
#ifdef NL_TARGET_fr30
#ifdef sys_defs
/* from syscall.h */

10
sim/configure vendored
View File

@ -1420,11 +1420,11 @@ case "${target}" in
extra_subdirs="${extra_subdirs} testsuite"
;;
d10v-*-*) sim_target=d10v ;;
d30v-*-*)
sim_target=d30v
only_if_gcc=yes
extra_subdirs="${extra_subdirs} igen"
;;
# OBSOLETE d30v-*-*)
# OBSOLETE sim_target=d30v
# OBSOLETE only_if_gcc=yes
# OBSOLETE extra_subdirs="${extra_subdirs} igen"
# OBSOLETE ;;
fr30-*-*) sim_target=fr30 ;;
h8300*-*-*) sim_target=h8300 ;;
h8500-*-*) sim_target=h8500 ;;

10
sim/configure.in
View File

@ -59,11 +59,11 @@ case "${target}" in
extra_subdirs="${extra_subdirs} testsuite"
;;
d10v-*-*) sim_target=d10v ;;
d30v-*-*)
sim_target=d30v
only_if_gcc=yes
extra_subdirs="${extra_subdirs} igen"
;;
# OBSOLETE d30v-*-*)
# OBSOLETE sim_target=d30v
# OBSOLETE only_if_gcc=yes
# OBSOLETE extra_subdirs="${extra_subdirs} igen"
# OBSOLETE ;;
fr30-*-*) sim_target=fr30 ;;
h8300*-*-*) sim_target=h8300 ;;
h8500-*-*) sim_target=h8500 ;;

6
sim/d30v/ChangeLog
View File

@ -1,3 +1,9 @@
2002-07-13 Andrew Cagney <ac131313@redhat.com>
* cpu.h: Mark file obsolete.
* sim-main.h, sim-calls.c, engine.c, cpu.c, alu.h: Ditto.
* dc-short, ic-d30v, d30v-insns, Makefile.in: Ditto.
2002-06-16 Andrew Cagney <ac131313@redhat.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.

434
sim/d30v/Makefile.in
View File

@ -1,217 +1,217 @@
# Mitsubishi Electric Corp. D30V Simulator.
# Copyright (C) 1997, Free Software Foundation, Inc.
# Contributed by Cygnus Support.
#
# This file is part of GDB, the GNU debugger.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License along
# with this program; if not, write to the Free Software Foundation, Inc.,
# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
M4= @M4@
## COMMON_PRE_CONFIG_FRAG
# These variables are given default values in COMMON_PRE_CONFIG_FRAG.
# We override the ones we need to here.
# Not all of these need to be mentioned, only the necessary ones.
# List of object files, less common parts.
SIM_OBJS = \
$(SIM_NEW_COMMON_OBJS) \
engine.o cpu.o \
s_support.o l_support.o \
s_idecode.o l_idecode.o \
s_semantics.o l_semantics.o \
sim-calls.o itable.o \
sim-hload.o \
sim-hrw.o \
sim-engine.o \
sim-stop.o \
sim-reason.o \
sim-resume.o
# List of extra dependencies.
# Generally this consists of simulator specific files included by sim-main.h.
SIM_EXTRA_DEPS = itable.h s_idecode.h l_idecode.h cpu.h alu.h
# List of generators
SIM_GEN=tmp-igen
# List of extra flags to always pass to $(CC).
SIM_EXTRA_CFLAGS = @sim_trapdump@
# List of main object files for `run'.
SIM_RUN_OBJS = nrun.o
# Dependency of `clean' to clean any extra files.
SIM_EXTRA_CLEAN = clean-igen
# This selects the d30v newlib/libgloss syscall definitions.
NL_TARGET=-DNL_TARGET_d30v
## COMMON_POST_CONFIG_FRAG
MAIN_INCLUDE_DEPS = tconfig.h
INCLUDE_DEPS = $(MAIN_INCLUDE_DEPS) $(SIM_EXTRA_DEPS)
# Rules need to build $(SIM_OBJS), plus whatever else the target wants.
# ... target specific rules ...
# Filter to eliminate known warnings
FILTER = 2>&1 | egrep -v "Discarding instruction|instruction field of type \`compute\' changed to \`cache\'|Instruction format is not 64 bits wide"
BUILT_SRC_FROM_IGEN = \
s_icache.h \
s_icache.c \
s_idecode.h \
s_idecode.c \
s_semantics.h \
s_semantics.c \
s_model.h \
s_model.c \
s_support.h \
s_support.c \
l_icache.h \
l_icache.c \
l_idecode.h \
l_idecode.c \
l_semantics.h \
l_semantics.c \
l_model.h \
l_model.c \
l_support.h \
l_support.c \
itable.h itable.c
$(BUILT_SRC_FROM_IGEN): tmp-igen
#
.PHONY: clean-igen
clean-igen:
rm -f $(BUILT_SRC_FROM_IGEN)
rm -f tmp-igen tmp-insns
../igen/igen:
cd ../igen && $(MAKE)
tmp-igen: $(srcdir)/dc-short $(srcdir)/d30v-insns $(srcdir)/ic-d30v ../igen/igen
cd ../igen && $(MAKE)
echo "# 1 \"$(srcdir)/d30v-insns\"" > tmp-insns
$(M4) < $(srcdir)/d30v-insns >> tmp-insns
@echo "Generating short version ..."
../igen/igen \
-G gen-zero-r0 \
-G direct-access \
-G default-nia-minus-one \
-G conditional-issue \
-G verify-slot \
-G field-widths \
-F short,emul \
-B 32 \
-P "s_" \
-o $(srcdir)/dc-short \
-k $(srcdir)/ic-d30v \
-n $(srcdir)/d30v-insns -i tmp-insns \
-n s_icache.h -hc tmp-icache.h \
-n s_icache.c -c tmp-icache.c \
-n s_semantics.h -hs tmp-semantics.h \
-n s_semantics.c -s tmp-semantics.c \
-n s_idecode.h -hd tmp-idecode.h \
-n s_idecode.c -d tmp-idecode.c \
-n s_model.h -hm tmp-model.h \
-n s_model.c -m tmp-model.c \
-n s_support.h -hf tmp-support.h \
-n s_support.c -f tmp-support.c $(FILTER)
$(srcdir)/../../move-if-change tmp-icache.h s_icache.h
$(srcdir)/../../move-if-change tmp-icache.c s_icache.c
$(srcdir)/../../move-if-change tmp-idecode.h s_idecode.h
$(srcdir)/../../move-if-change tmp-idecode.c s_idecode.c
$(srcdir)/../../move-if-change tmp-semantics.h s_semantics.h
$(srcdir)/../../move-if-change tmp-semantics.c s_semantics.c
$(srcdir)/../../move-if-change tmp-model.h s_model.h
$(srcdir)/../../move-if-change tmp-model.c s_model.c
$(srcdir)/../../move-if-change tmp-support.h s_support.h
$(srcdir)/../../move-if-change tmp-support.c s_support.c
@echo "Generating long version ..."
../igen/igen \
-G gen-zero-r0 \
-G direct-access \
-G default-nia-minus-one \
-G conditional-issue \
-G field-widths \
-F long,emul \
-B 64 \
-P "l_" \
-o $(srcdir)/dc-short \
-k $(srcdir)/ic-d30v \
-i tmp-insns \
-n l_icache.h -hc tmp-icache.h \
-n l_icache.c -c tmp-icache.c \
-n l_semantics.h -hs tmp-semantics.h \
-n l_semantics.c -s tmp-semantics.c \
-n l_idecode.h -hd tmp-idecode.h \
-n l_idecode.c -d tmp-idecode.c \
-n l_model.h -hm tmp-model.h \
-n l_model.c -m tmp-model.c \
-n l_support.h -hf tmp-support.h \
-n l_support.c -f tmp-support.c $(FILTER)
$(srcdir)/../../move-if-change tmp-icache.h l_icache.h
$(srcdir)/../../move-if-change tmp-icache.c l_icache.c
$(srcdir)/../../move-if-change tmp-idecode.h l_idecode.h
$(srcdir)/../../move-if-change tmp-idecode.c l_idecode.c
$(srcdir)/../../move-if-change tmp-semantics.h l_semantics.h
$(srcdir)/../../move-if-change tmp-semantics.c l_semantics.c
$(srcdir)/../../move-if-change tmp-model.h l_model.h
$(srcdir)/../../move-if-change tmp-model.c l_model.c
$(srcdir)/../../move-if-change tmp-support.h l_support.h
$(srcdir)/../../move-if-change tmp-support.c l_support.c
@echo "Generating instruction database ..."
../igen/igen \
-G field-widths \
-F short,long,emul \
-B 64 \
-o $(srcdir)/dc-short \
-k $(srcdir)/ic-d30v \
-i tmp-insns \
-n itable.h -ht tmp-itable.h \
-n itable.c -t tmp-itable.c $(FILTER)
$(srcdir)/../../move-if-change tmp-itable.h itable.h
$(srcdir)/../../move-if-change tmp-itable.c itable.c
touch tmp-igen
ENGINE_H = \
sim-main.h \
$(srcdir)/../common/sim-basics.h \
config.h \
$(srcdir)/../common/sim-config.h \
$(srcdir)/../common/sim-inline.h \
$(srcdir)/../common/sim-types.h \
$(srcdir)/../common/sim-bits.h \
$(srcdir)/../common/sim-endian.h \
itable.h \
l_idecode.h s_idecode.h \
cpu.h \
alu.h \
$(srcdir)/../common/sim-alu.h \
$(srcdir)/../common/sim-core.h \
$(srcdir)/../common/sim-events.h \
engine.o: engine.c $(ENGINE_H)
sim-calls.o: sim-calls.c $(ENGINE_H) $(srcdir)/../common/sim-utils.h $(srcdir)/../common/sim-options.h
cpu.o: cpu.c $(ENGINE_H)
s_support.o: s_support.c $(ENGINE_H)
l_support.o: l_support.c $(ENGINE_H)
s_semantics.o: s_semantics.c $(ENGINE_H)
l_semantics.o: l_semantics.c $(ENGINE_H)
# OBSOLETE # Mitsubishi Electric Corp. D30V Simulator.
# OBSOLETE # Copyright (C) 1997, Free Software Foundation, Inc.
# OBSOLETE # Contributed by Cygnus Support.
# OBSOLETE #
# OBSOLETE # This file is part of GDB, the GNU debugger.
# OBSOLETE #
# OBSOLETE # This program is free software; you can redistribute it and/or modify
# OBSOLETE # it under the terms of the GNU General Public License as published by
# OBSOLETE # the Free Software Foundation; either version 2, or (at your option)
# OBSOLETE # any later version.
# OBSOLETE #
# OBSOLETE # This program is distributed in the hope that it will be useful,
# OBSOLETE # but WITHOUT ANY WARRANTY; without even the implied warranty of
# OBSOLETE # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# OBSOLETE # GNU General Public License for more details.
# OBSOLETE #
# OBSOLETE # You should have received a copy of the GNU General Public License along
# OBSOLETE # with this program; if not, write to the Free Software Foundation, Inc.,
# OBSOLETE # 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
# OBSOLETE
# OBSOLETE M4= @M4@
# OBSOLETE
# OBSOLETE
# OBSOLETE ## COMMON_PRE_CONFIG_FRAG
# OBSOLETE
# OBSOLETE # These variables are given default values in COMMON_PRE_CONFIG_FRAG.
# OBSOLETE # We override the ones we need to here.
# OBSOLETE # Not all of these need to be mentioned, only the necessary ones.
# OBSOLETE
# OBSOLETE # List of object files, less common parts.
# OBSOLETE SIM_OBJS = \
# OBSOLETE $(SIM_NEW_COMMON_OBJS) \
# OBSOLETE engine.o cpu.o \
# OBSOLETE s_support.o l_support.o \
# OBSOLETE s_idecode.o l_idecode.o \
# OBSOLETE s_semantics.o l_semantics.o \
# OBSOLETE sim-calls.o itable.o \
# OBSOLETE sim-hload.o \
# OBSOLETE sim-hrw.o \
# OBSOLETE sim-engine.o \
# OBSOLETE sim-stop.o \
# OBSOLETE sim-reason.o \
# OBSOLETE sim-resume.o
# OBSOLETE
# OBSOLETE # List of extra dependencies.
# OBSOLETE # Generally this consists of simulator specific files included by sim-main.h.
# OBSOLETE SIM_EXTRA_DEPS = itable.h s_idecode.h l_idecode.h cpu.h alu.h
# OBSOLETE
# OBSOLETE # List of generators
# OBSOLETE SIM_GEN=tmp-igen
# OBSOLETE
# OBSOLETE # List of extra flags to always pass to $(CC).
# OBSOLETE SIM_EXTRA_CFLAGS = @sim_trapdump@
# OBSOLETE
# OBSOLETE # List of main object files for `run'.
# OBSOLETE SIM_RUN_OBJS = nrun.o
# OBSOLETE
# OBSOLETE # Dependency of `clean' to clean any extra files.
# OBSOLETE SIM_EXTRA_CLEAN = clean-igen
# OBSOLETE
# OBSOLETE # This selects the d30v newlib/libgloss syscall definitions.
# OBSOLETE NL_TARGET=-DNL_TARGET_d30v
# OBSOLETE
# OBSOLETE ## COMMON_POST_CONFIG_FRAG
# OBSOLETE
# OBSOLETE MAIN_INCLUDE_DEPS = tconfig.h
# OBSOLETE INCLUDE_DEPS = $(MAIN_INCLUDE_DEPS) $(SIM_EXTRA_DEPS)
# OBSOLETE
# OBSOLETE # Rules need to build $(SIM_OBJS), plus whatever else the target wants.
# OBSOLETE
# OBSOLETE # ... target specific rules ...
# OBSOLETE
# OBSOLETE # Filter to eliminate known warnings
# OBSOLETE FILTER = 2>&1 | egrep -v "Discarding instruction|instruction field of type \`compute\' changed to \`cache\'|Instruction format is not 64 bits wide"
# OBSOLETE
# OBSOLETE BUILT_SRC_FROM_IGEN = \
# OBSOLETE s_icache.h \
# OBSOLETE s_icache.c \
# OBSOLETE s_idecode.h \
# OBSOLETE s_idecode.c \
# OBSOLETE s_semantics.h \
# OBSOLETE s_semantics.c \
# OBSOLETE s_model.h \
# OBSOLETE s_model.c \
# OBSOLETE s_support.h \
# OBSOLETE s_support.c \
# OBSOLETE l_icache.h \
# OBSOLETE l_icache.c \
# OBSOLETE l_idecode.h \
# OBSOLETE l_idecode.c \
# OBSOLETE l_semantics.h \
# OBSOLETE l_semantics.c \
# OBSOLETE l_model.h \
# OBSOLETE l_model.c \
# OBSOLETE l_support.h \
# OBSOLETE l_support.c \
# OBSOLETE itable.h itable.c
# OBSOLETE $(BUILT_SRC_FROM_IGEN): tmp-igen
# OBSOLETE #
# OBSOLETE
# OBSOLETE .PHONY: clean-igen
# OBSOLETE clean-igen:
# OBSOLETE rm -f $(BUILT_SRC_FROM_IGEN)
# OBSOLETE rm -f tmp-igen tmp-insns
# OBSOLETE
# OBSOLETE ../igen/igen:
# OBSOLETE cd ../igen && $(MAKE)
# OBSOLETE
# OBSOLETE tmp-igen: $(srcdir)/dc-short $(srcdir)/d30v-insns $(srcdir)/ic-d30v ../igen/igen
# OBSOLETE cd ../igen && $(MAKE)
# OBSOLETE echo "# 1 \"$(srcdir)/d30v-insns\"" > tmp-insns
# OBSOLETE $(M4) < $(srcdir)/d30v-insns >> tmp-insns
# OBSOLETE @echo "Generating short version ..."
# OBSOLETE ../igen/igen \
# OBSOLETE -G gen-zero-r0 \
# OBSOLETE -G direct-access \
# OBSOLETE -G default-nia-minus-one \
# OBSOLETE -G conditional-issue \
# OBSOLETE -G verify-slot \
# OBSOLETE -G field-widths \
# OBSOLETE -F short,emul \
# OBSOLETE -B 32 \
# OBSOLETE -P "s_" \
# OBSOLETE -o $(srcdir)/dc-short \
# OBSOLETE -k $(srcdir)/ic-d30v \
# OBSOLETE -n $(srcdir)/d30v-insns -i tmp-insns \
# OBSOLETE -n s_icache.h -hc tmp-icache.h \
# OBSOLETE -n s_icache.c -c tmp-icache.c \
# OBSOLETE -n s_semantics.h -hs tmp-semantics.h \
# OBSOLETE -n s_semantics.c -s tmp-semantics.c \
# OBSOLETE -n s_idecode.h -hd tmp-idecode.h \
# OBSOLETE -n s_idecode.c -d tmp-idecode.c \
# OBSOLETE -n s_model.h -hm tmp-model.h \
# OBSOLETE -n s_model.c -m tmp-model.c \
# OBSOLETE -n s_support.h -hf tmp-support.h \
# OBSOLETE -n s_support.c -f tmp-support.c $(FILTER)
# OBSOLETE $(srcdir)/../../move-if-change tmp-icache.h s_icache.h
# OBSOLETE $(srcdir)/../../move-if-change tmp-icache.c s_icache.c
# OBSOLETE $(srcdir)/../../move-if-change tmp-idecode.h s_idecode.h
# OBSOLETE $(srcdir)/../../move-if-change tmp-idecode.c s_idecode.c
# OBSOLETE $(srcdir)/../../move-if-change tmp-semantics.h s_semantics.h
# OBSOLETE $(srcdir)/../../move-if-change tmp-semantics.c s_semantics.c
# OBSOLETE $(srcdir)/../../move-if-change tmp-model.h s_model.h
# OBSOLETE $(srcdir)/../../move-if-change tmp-model.c s_model.c
# OBSOLETE $(srcdir)/../../move-if-change tmp-support.h s_support.h
# OBSOLETE $(srcdir)/../../move-if-change tmp-support.c s_support.c
# OBSOLETE @echo "Generating long version ..."
# OBSOLETE ../igen/igen \
# OBSOLETE -G gen-zero-r0 \
# OBSOLETE -G direct-access \
# OBSOLETE -G default-nia-minus-one \
# OBSOLETE -G conditional-issue \
# OBSOLETE -G field-widths \
# OBSOLETE -F long,emul \
# OBSOLETE -B 64 \
# OBSOLETE -P "l_" \
# OBSOLETE -o $(srcdir)/dc-short \
# OBSOLETE -k $(srcdir)/ic-d30v \
# OBSOLETE -i tmp-insns \
# OBSOLETE -n l_icache.h -hc tmp-icache.h \
# OBSOLETE -n l_icache.c -c tmp-icache.c \
# OBSOLETE -n l_semantics.h -hs tmp-semantics.h \
# OBSOLETE -n l_semantics.c -s tmp-semantics.c \
# OBSOLETE -n l_idecode.h -hd tmp-idecode.h \
# OBSOLETE -n l_idecode.c -d tmp-idecode.c \
# OBSOLETE -n l_model.h -hm tmp-model.h \
# OBSOLETE -n l_model.c -m tmp-model.c \
# OBSOLETE -n l_support.h -hf tmp-support.h \
# OBSOLETE -n l_support.c -f tmp-support.c $(FILTER)
# OBSOLETE $(srcdir)/../../move-if-change tmp-icache.h l_icache.h
# OBSOLETE $(srcdir)/../../move-if-change tmp-icache.c l_icache.c
# OBSOLETE $(srcdir)/../../move-if-change tmp-idecode.h l_idecode.h
# OBSOLETE $(srcdir)/../../move-if-change tmp-idecode.c l_idecode.c
# OBSOLETE $(srcdir)/../../move-if-change tmp-semantics.h l_semantics.h
# OBSOLETE $(srcdir)/../../move-if-change tmp-semantics.c l_semantics.c
# OBSOLETE $(srcdir)/../../move-if-change tmp-model.h l_model.h
# OBSOLETE $(srcdir)/../../move-if-change tmp-model.c l_model.c
# OBSOLETE $(srcdir)/../../move-if-change tmp-support.h l_support.h
# OBSOLETE $(srcdir)/../../move-if-change tmp-support.c l_support.c
# OBSOLETE @echo "Generating instruction database ..."
# OBSOLETE ../igen/igen \
# OBSOLETE -G field-widths \
# OBSOLETE -F short,long,emul \
# OBSOLETE -B 64 \
# OBSOLETE -o $(srcdir)/dc-short \
# OBSOLETE -k $(srcdir)/ic-d30v \
# OBSOLETE -i tmp-insns \
# OBSOLETE -n itable.h -ht tmp-itable.h \
# OBSOLETE -n itable.c -t tmp-itable.c $(FILTER)
# OBSOLETE $(srcdir)/../../move-if-change tmp-itable.h itable.h
# OBSOLETE $(srcdir)/../../move-if-change tmp-itable.c itable.c
# OBSOLETE touch tmp-igen
# OBSOLETE
# OBSOLETE ENGINE_H = \
# OBSOLETE sim-main.h \
# OBSOLETE $(srcdir)/../common/sim-basics.h \
# OBSOLETE config.h \
# OBSOLETE $(srcdir)/../common/sim-config.h \
# OBSOLETE $(srcdir)/../common/sim-inline.h \
# OBSOLETE $(srcdir)/../common/sim-types.h \
# OBSOLETE $(srcdir)/../common/sim-bits.h \
# OBSOLETE $(srcdir)/../common/sim-endian.h \
# OBSOLETE itable.h \
# OBSOLETE l_idecode.h s_idecode.h \
# OBSOLETE cpu.h \
# OBSOLETE alu.h \
# OBSOLETE $(srcdir)/../common/sim-alu.h \
# OBSOLETE $(srcdir)/../common/sim-core.h \
# OBSOLETE $(srcdir)/../common/sim-events.h \
# OBSOLETE
# OBSOLETE engine.o: engine.c $(ENGINE_H)
# OBSOLETE sim-calls.o: sim-calls.c $(ENGINE_H) $(srcdir)/../common/sim-utils.h $(srcdir)/../common/sim-options.h
# OBSOLETE cpu.o: cpu.c $(ENGINE_H)
# OBSOLETE s_support.o: s_support.c $(ENGINE_H)
# OBSOLETE l_support.o: l_support.c $(ENGINE_H)
# OBSOLETE s_semantics.o: s_semantics.c $(ENGINE_H)
# OBSOLETE l_semantics.o: l_semantics.c $(ENGINE_H)

212
sim/d30v/alu.h
View File

@ -1,106 +1,106 @@
/* Mitsubishi Electric Corp. D30V Simulator.
Copyright (C) 1997, Free Software Foundation, Inc.
Contributed by Cygnus Support.
This file is part of GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#ifndef _D30V_ALU_H_
#define _D30V_ALU_H_
#define ALU_CARRY (PSW_VAL(PSW_C) != 0)
#include "sim-alu.h"
#define ALU16_END(TARG, HIGH) \
{ \
unsigned32 mask, value; \
if (ALU16_HAD_OVERFLOW) { \
mask = BIT32 (PSW_V) | BIT32 (PSW_VA) | BIT32 (PSW_C); \
value = BIT32 (PSW_V) | BIT32 (PSW_VA); \
} \
else { \
mask = BIT32 (PSW_V) | BIT32 (PSW_C); \
value = 0; \
} \
if (ALU16_HAD_CARRY_BORROW) \
value |= BIT32 (PSW_C); \
if (HIGH) \
WRITE32_QUEUE_MASK (TARG, ALU16_OVERFLOW_RESULT<<16, 0xffff0000); \
else \
WRITE32_QUEUE_MASK (TARG, ALU16_OVERFLOW_RESULT, 0x0000ffff); \
WRITE32_QUEUE_MASK (&PSW, value, mask); \
}
#define ALU32_END(TARG) \
{ \
unsigned32 mask, value; \
if (ALU32_HAD_OVERFLOW) { \
mask = BIT32 (PSW_V) | BIT32 (PSW_VA) | BIT32 (PSW_C); \
value = BIT32 (PSW_V) | BIT32 (PSW_VA); \
} \
else { \
mask = BIT32 (PSW_V) | BIT32 (PSW_C); \
value = 0; \
} \
if (ALU32_HAD_CARRY_BORROW) \
value |= BIT32 (PSW_C); \
WRITE32_QUEUE (TARG, ALU32_OVERFLOW_RESULT); \
WRITE32_QUEUE_MASK (&PSW, value, mask); \
}
#define ALU_END(TARG) ALU32_END(TARG)
/* PSW & Flag manipulation */
#define PSW_SET(BIT,VAL) BLIT32(PSW, (BIT), (VAL))
#define PSW_VAL(BIT) EXTRACTED32(PSW, (BIT), (BIT))
#define PSW_F(FLAG) (17 + ((FLAG) % 8) * 2)
#define PSW_FLAG_SET(FLAG,VAL) PSW_SET(PSW_F(FLAG), VAL)
#define PSW_FLAG_VAL(FLAG) PSW_VAL(PSW_F(FLAG))
#define PSW_SET_QUEUE(BIT,VAL) \
do { \
unsigned32 mask = BIT32 (BIT); \
unsigned32 bitval = (VAL) ? mask : 0; \
WRITE32_QUEUE_MASK (&PSW, bitval, mask); \
} while (0)
#define PSW_FLAG_SET_QUEUE(FLAG,VAL) \
do { \
unsigned32 mask = BIT32 (PSW_F (FLAG)); \
unsigned32 bitval = (VAL) ? mask : 0; \
WRITE32_QUEUE_MASK (&PSW, bitval, mask); \
} while (0)
/* Bring data in from the cold */
#define IMEM(EA) \
(sim_core_read_8(STATE_CPU (sd, 0), cia, exec_map, (EA)))
#define MEM(SIGN, EA, NR_BYTES) \
((SIGN##_##NR_BYTES) sim_core_read_unaligned_##NR_BYTES(STATE_CPU (sd, 0), cia, read_map, (EA)))
#define STORE(EA, NR_BYTES, VAL) \
do { \
sim_core_write_unaligned_##NR_BYTES(STATE_CPU (sd, 0), cia, write_map, (EA), (VAL)); \
} while (0)
#endif
/* OBSOLETE /* Mitsubishi Electric Corp. D30V Simulator. */
/* OBSOLETE Copyright (C) 1997, Free Software Foundation, Inc. */
/* OBSOLETE Contributed by Cygnus Support. */
/* OBSOLETE */
/* OBSOLETE This file is part of GDB, the GNU debugger. */
/* OBSOLETE */
/* OBSOLETE This program is free software; you can redistribute it and/or modify */
/* OBSOLETE it under the terms of the GNU General Public License as published by */
/* OBSOLETE the Free Software Foundation; either version 2, or (at your option) */
/* OBSOLETE any later version. */
/* OBSOLETE */
/* OBSOLETE This program is distributed in the hope that it will be useful, */
/* OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of */
/* OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
/* OBSOLETE GNU General Public License for more details. */
/* OBSOLETE */
/* OBSOLETE You should have received a copy of the GNU General Public License along */
/* OBSOLETE with this program; if not, write to the Free Software Foundation, Inc., */
/* OBSOLETE 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE #ifndef _D30V_ALU_H_ */
/* OBSOLETE #define _D30V_ALU_H_ */
/* OBSOLETE */
/* OBSOLETE #define ALU_CARRY (PSW_VAL(PSW_C) != 0) */
/* OBSOLETE */
/* OBSOLETE #include "sim-alu.h" */
/* OBSOLETE */
/* OBSOLETE #define ALU16_END(TARG, HIGH) \ */
/* OBSOLETE { \ */
/* OBSOLETE unsigned32 mask, value; \ */
/* OBSOLETE if (ALU16_HAD_OVERFLOW) { \ */
/* OBSOLETE mask = BIT32 (PSW_V) | BIT32 (PSW_VA) | BIT32 (PSW_C); \ */
/* OBSOLETE value = BIT32 (PSW_V) | BIT32 (PSW_VA); \ */
/* OBSOLETE } \ */
/* OBSOLETE else { \ */
/* OBSOLETE mask = BIT32 (PSW_V) | BIT32 (PSW_C); \ */
/* OBSOLETE value = 0; \ */
/* OBSOLETE } \ */
/* OBSOLETE if (ALU16_HAD_CARRY_BORROW) \ */
/* OBSOLETE value |= BIT32 (PSW_C); \ */
/* OBSOLETE if (HIGH) \ */
/* OBSOLETE WRITE32_QUEUE_MASK (TARG, ALU16_OVERFLOW_RESULT<<16, 0xffff0000); \ */
/* OBSOLETE else \ */
/* OBSOLETE WRITE32_QUEUE_MASK (TARG, ALU16_OVERFLOW_RESULT, 0x0000ffff); \ */
/* OBSOLETE WRITE32_QUEUE_MASK (&PSW, value, mask); \ */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE #define ALU32_END(TARG) \ */
/* OBSOLETE { \ */
/* OBSOLETE unsigned32 mask, value; \ */
/* OBSOLETE if (ALU32_HAD_OVERFLOW) { \ */
/* OBSOLETE mask = BIT32 (PSW_V) | BIT32 (PSW_VA) | BIT32 (PSW_C); \ */
/* OBSOLETE value = BIT32 (PSW_V) | BIT32 (PSW_VA); \ */
/* OBSOLETE } \ */
/* OBSOLETE else { \ */
/* OBSOLETE mask = BIT32 (PSW_V) | BIT32 (PSW_C); \ */
/* OBSOLETE value = 0; \ */
/* OBSOLETE } \ */
/* OBSOLETE if (ALU32_HAD_CARRY_BORROW) \ */
/* OBSOLETE value |= BIT32 (PSW_C); \ */
/* OBSOLETE WRITE32_QUEUE (TARG, ALU32_OVERFLOW_RESULT); \ */
/* OBSOLETE WRITE32_QUEUE_MASK (&PSW, value, mask); \ */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE #define ALU_END(TARG) ALU32_END(TARG) */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE /* PSW & Flag manipulation */ */
/* OBSOLETE */
/* OBSOLETE #define PSW_SET(BIT,VAL) BLIT32(PSW, (BIT), (VAL)) */
/* OBSOLETE #define PSW_VAL(BIT) EXTRACTED32(PSW, (BIT), (BIT)) */
/* OBSOLETE */
/* OBSOLETE #define PSW_F(FLAG) (17 + ((FLAG) % 8) * 2) */
/* OBSOLETE #define PSW_FLAG_SET(FLAG,VAL) PSW_SET(PSW_F(FLAG), VAL) */
/* OBSOLETE #define PSW_FLAG_VAL(FLAG) PSW_VAL(PSW_F(FLAG)) */
/* OBSOLETE */
/* OBSOLETE #define PSW_SET_QUEUE(BIT,VAL) \ */
/* OBSOLETE do { \ */
/* OBSOLETE unsigned32 mask = BIT32 (BIT); \ */
/* OBSOLETE unsigned32 bitval = (VAL) ? mask : 0; \ */
/* OBSOLETE WRITE32_QUEUE_MASK (&PSW, bitval, mask); \ */
/* OBSOLETE } while (0) */
/* OBSOLETE */
/* OBSOLETE #define PSW_FLAG_SET_QUEUE(FLAG,VAL) \ */
/* OBSOLETE do { \ */
/* OBSOLETE unsigned32 mask = BIT32 (PSW_F (FLAG)); \ */
/* OBSOLETE unsigned32 bitval = (VAL) ? mask : 0; \ */
/* OBSOLETE WRITE32_QUEUE_MASK (&PSW, bitval, mask); \ */
/* OBSOLETE } while (0) */
/* OBSOLETE */
/* OBSOLETE /* Bring data in from the cold */ */
/* OBSOLETE */
/* OBSOLETE #define IMEM(EA) \ */
/* OBSOLETE (sim_core_read_8(STATE_CPU (sd, 0), cia, exec_map, (EA))) */
/* OBSOLETE */
/* OBSOLETE #define MEM(SIGN, EA, NR_BYTES) \ */
/* OBSOLETE ((SIGN##_##NR_BYTES) sim_core_read_unaligned_##NR_BYTES(STATE_CPU (sd, 0), cia, read_map, (EA))) */
/* OBSOLETE */
/* OBSOLETE #define STORE(EA, NR_BYTES, VAL) \ */
/* OBSOLETE do { \ */
/* OBSOLETE sim_core_write_unaligned_##NR_BYTES(STATE_CPU (sd, 0), cia, write_map, (EA), (VAL)); \ */
/* OBSOLETE } while (0) */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE #endif */

344
sim/d30v/cpu.c
View File

@ -1,172 +1,172 @@
/* Mitsubishi Electric Corp. D30V Simulator.
Copyright (C) 1997, Free Software Foundation, Inc.
Contributed by Cygnus Support.
This file is part of GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#ifndef _CPU_C_
#define _CPU_C_
#include "sim-main.h"
int
is_wrong_slot (SIM_DESC sd,
address_word cia,
itable_index index)
{
switch (STATE_CPU (sd, 0)->unit)
{
case memory_unit:
return !itable[index].option[itable_option_mu];
case integer_unit:
return !itable[index].option[itable_option_iu];
case any_unit:
return 0;
default:
sim_engine_abort (sd, STATE_CPU (sd, 0), cia,
"internal error - is_wrong_slot - bad switch");
return -1;
}
}
int
is_condition_ok (SIM_DESC sd,
address_word cia,
int cond)
{
switch (cond)
{
case 0x0:
return 1;
case 0x1:
return PSW_VAL(PSW_F0);
case 0x2:
return !PSW_VAL(PSW_F0);
case 0x3:
return PSW_VAL(PSW_F1);
case 0x4:
return !PSW_VAL(PSW_F1);
case 0x5:
return PSW_VAL(PSW_F0) && PSW_VAL(PSW_F1);
case 0x6:
return PSW_VAL(PSW_F0) && !PSW_VAL(PSW_F1);
case 0x7:
sim_engine_abort (sd, STATE_CPU (sd, 0), cia,
"is_condition_ok - bad instruction condition bits");
return 0;
default:
sim_engine_abort (sd, STATE_CPU (sd, 0), cia,
"internal error - is_condition_ok - bad switch");
return -1;
}
}
/* If --trace-call, trace calls, remembering the current state of
registers. */
typedef struct _call_stack {
struct _call_stack *prev;
registers regs;
} call_stack;
static call_stack *call_stack_head = (call_stack *)0;
static int call_depth = 0;
void call_occurred (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
address_word nia)
{
call_stack *ptr = ZALLOC (call_stack);
ptr->regs = cpu->regs;
ptr->prev = call_stack_head;
call_stack_head = ptr;
trace_one_insn (sd, cpu, nia, 1, "", 0, "call",
"Depth %3d, Return 0x%.8lx, Args 0x%.8lx 0x%.8lx",
++call_depth, (unsigned long)cia+8, (unsigned long)GPR[2],
(unsigned long)GPR[3]);
}
/* If --trace-call, trace returns, checking if any saved register was changed. */
void return_occurred (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
address_word nia)
{
char buffer[1024];
char *buf_ptr = buffer;
call_stack *ptr = call_stack_head;
int regno;
char *prefix = ", Registers that differ: ";
*buf_ptr = '\0';
for (regno = 34; regno <= 63; regno++) {
if (cpu->regs.general_purpose[regno] != ptr->regs.general_purpose[regno]) {
sprintf (buf_ptr, "%sr%d", prefix, regno);
buf_ptr += strlen (buf_ptr);
prefix = " ";
}
}
if (cpu->regs.accumulator[1] != ptr->regs.accumulator[1]) {
sprintf (buf_ptr, "%sa1", prefix);
buf_ptr += strlen (buf_ptr);
prefix = " ";
}
trace_one_insn (sd, cpu, cia, 1, "", 0, "return",
"Depth %3d, Return 0x%.8lx, Ret. 0x%.8lx 0x%.8lx%s",
call_depth--, (unsigned long)nia, (unsigned long)GPR[2],
(unsigned long)GPR[3], buffer);
call_stack_head = ptr->prev;
zfree (ptr);
}
/* Read/write functions for system call interface. */
int
d30v_read_mem (host_callback *cb,
struct cb_syscall *sc,
unsigned long taddr,
char *buf,
int bytes)
{
SIM_DESC sd = (SIM_DESC) sc->p1;
sim_cpu *cpu = STATE_CPU (sd, 0);
return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
}
int
d30v_write_mem (host_callback *cb,
struct cb_syscall *sc,
unsigned long taddr,
const char *buf,
int bytes)
{
SIM_DESC sd = (SIM_DESC) sc->p1;
sim_cpu *cpu = STATE_CPU (sd, 0);
return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
}
#endif /* _CPU_C_ */
/* OBSOLETE /* Mitsubishi Electric Corp. D30V Simulator. */
/* OBSOLETE Copyright (C) 1997, Free Software Foundation, Inc. */
/* OBSOLETE Contributed by Cygnus Support. */
/* OBSOLETE */
/* OBSOLETE This file is part of GDB, the GNU debugger. */
/* OBSOLETE */
/* OBSOLETE This program is free software; you can redistribute it and/or modify */
/* OBSOLETE it under the terms of the GNU General Public License as published by */
/* OBSOLETE the Free Software Foundation; either version 2, or (at your option) */
/* OBSOLETE any later version. */
/* OBSOLETE */
/* OBSOLETE This program is distributed in the hope that it will be useful, */
/* OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of */
/* OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
/* OBSOLETE GNU General Public License for more details. */
/* OBSOLETE */
/* OBSOLETE You should have received a copy of the GNU General Public License along */
/* OBSOLETE with this program; if not, write to the Free Software Foundation, Inc., */
/* OBSOLETE 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE #ifndef _CPU_C_ */
/* OBSOLETE #define _CPU_C_ */
/* OBSOLETE */
/* OBSOLETE #include "sim-main.h" */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE int */
/* OBSOLETE is_wrong_slot (SIM_DESC sd, */
/* OBSOLETE address_word cia, */
/* OBSOLETE itable_index index) */
/* OBSOLETE { */
/* OBSOLETE switch (STATE_CPU (sd, 0)->unit) */
/* OBSOLETE { */
/* OBSOLETE case memory_unit: */
/* OBSOLETE return !itable[index].option[itable_option_mu]; */
/* OBSOLETE case integer_unit: */
/* OBSOLETE return !itable[index].option[itable_option_iu]; */
/* OBSOLETE case any_unit: */
/* OBSOLETE return 0; */
/* OBSOLETE default: */
/* OBSOLETE sim_engine_abort (sd, STATE_CPU (sd, 0), cia, */
/* OBSOLETE "internal error - is_wrong_slot - bad switch"); */
/* OBSOLETE return -1; */
/* OBSOLETE } */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE int */
/* OBSOLETE is_condition_ok (SIM_DESC sd, */
/* OBSOLETE address_word cia, */
/* OBSOLETE int cond) */
/* OBSOLETE { */
/* OBSOLETE switch (cond) */
/* OBSOLETE { */
/* OBSOLETE case 0x0: */
/* OBSOLETE return 1; */
/* OBSOLETE case 0x1: */
/* OBSOLETE return PSW_VAL(PSW_F0); */
/* OBSOLETE case 0x2: */
/* OBSOLETE return !PSW_VAL(PSW_F0); */
/* OBSOLETE case 0x3: */
/* OBSOLETE return PSW_VAL(PSW_F1); */
/* OBSOLETE case 0x4: */
/* OBSOLETE return !PSW_VAL(PSW_F1); */
/* OBSOLETE case 0x5: */
/* OBSOLETE return PSW_VAL(PSW_F0) && PSW_VAL(PSW_F1); */
/* OBSOLETE case 0x6: */
/* OBSOLETE return PSW_VAL(PSW_F0) && !PSW_VAL(PSW_F1); */
/* OBSOLETE case 0x7: */
/* OBSOLETE sim_engine_abort (sd, STATE_CPU (sd, 0), cia, */
/* OBSOLETE "is_condition_ok - bad instruction condition bits"); */
/* OBSOLETE return 0; */
/* OBSOLETE default: */
/* OBSOLETE sim_engine_abort (sd, STATE_CPU (sd, 0), cia, */
/* OBSOLETE "internal error - is_condition_ok - bad switch"); */
/* OBSOLETE return -1; */
/* OBSOLETE } */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE /* If --trace-call, trace calls, remembering the current state of */
/* OBSOLETE registers. */ */
/* OBSOLETE */
/* OBSOLETE typedef struct _call_stack { */
/* OBSOLETE struct _call_stack *prev; */
/* OBSOLETE registers regs; */
/* OBSOLETE } call_stack; */
/* OBSOLETE */
/* OBSOLETE static call_stack *call_stack_head = (call_stack *)0; */
/* OBSOLETE static int call_depth = 0; */
/* OBSOLETE */
/* OBSOLETE void call_occurred (SIM_DESC sd, */
/* OBSOLETE sim_cpu *cpu, */
/* OBSOLETE address_word cia, */
/* OBSOLETE address_word nia) */
/* OBSOLETE { */
/* OBSOLETE call_stack *ptr = ZALLOC (call_stack); */
/* OBSOLETE ptr->regs = cpu->regs; */
/* OBSOLETE ptr->prev = call_stack_head; */
/* OBSOLETE call_stack_head = ptr; */
/* OBSOLETE */
/* OBSOLETE trace_one_insn (sd, cpu, nia, 1, "", 0, "call", */
/* OBSOLETE "Depth %3d, Return 0x%.8lx, Args 0x%.8lx 0x%.8lx", */
/* OBSOLETE ++call_depth, (unsigned long)cia+8, (unsigned long)GPR[2], */
/* OBSOLETE (unsigned long)GPR[3]); */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE /* If --trace-call, trace returns, checking if any saved register was changed. */ */
/* OBSOLETE */
/* OBSOLETE void return_occurred (SIM_DESC sd, */
/* OBSOLETE sim_cpu *cpu, */
/* OBSOLETE address_word cia, */
/* OBSOLETE address_word nia) */
/* OBSOLETE { */
/* OBSOLETE char buffer[1024]; */
/* OBSOLETE char *buf_ptr = buffer; */
/* OBSOLETE call_stack *ptr = call_stack_head; */
/* OBSOLETE int regno; */
/* OBSOLETE char *prefix = ", Registers that differ: "; */
/* OBSOLETE */
/* OBSOLETE *buf_ptr = '\0'; */
/* OBSOLETE for (regno = 34; regno <= 63; regno++) { */
/* OBSOLETE if (cpu->regs.general_purpose[regno] != ptr->regs.general_purpose[regno]) { */
/* OBSOLETE sprintf (buf_ptr, "%sr%d", prefix, regno); */
/* OBSOLETE buf_ptr += strlen (buf_ptr); */
/* OBSOLETE prefix = " "; */
/* OBSOLETE } */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE if (cpu->regs.accumulator[1] != ptr->regs.accumulator[1]) { */
/* OBSOLETE sprintf (buf_ptr, "%sa1", prefix); */
/* OBSOLETE buf_ptr += strlen (buf_ptr); */
/* OBSOLETE prefix = " "; */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE trace_one_insn (sd, cpu, cia, 1, "", 0, "return", */
/* OBSOLETE "Depth %3d, Return 0x%.8lx, Ret. 0x%.8lx 0x%.8lx%s", */
/* OBSOLETE call_depth--, (unsigned long)nia, (unsigned long)GPR[2], */
/* OBSOLETE (unsigned long)GPR[3], buffer); */
/* OBSOLETE */
/* OBSOLETE call_stack_head = ptr->prev; */
/* OBSOLETE zfree (ptr); */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE /* Read/write functions for system call interface. */ */
/* OBSOLETE int */
/* OBSOLETE d30v_read_mem (host_callback *cb, */
/* OBSOLETE struct cb_syscall *sc, */
/* OBSOLETE unsigned long taddr, */
/* OBSOLETE char *buf, */
/* OBSOLETE int bytes) */
/* OBSOLETE { */
/* OBSOLETE SIM_DESC sd = (SIM_DESC) sc->p1; */
/* OBSOLETE sim_cpu *cpu = STATE_CPU (sd, 0); */
/* OBSOLETE */
/* OBSOLETE return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes); */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE int */
/* OBSOLETE d30v_write_mem (host_callback *cb, */
/* OBSOLETE struct cb_syscall *sc, */
/* OBSOLETE unsigned long taddr, */
/* OBSOLETE const char *buf, */
/* OBSOLETE int bytes) */
/* OBSOLETE { */
/* OBSOLETE SIM_DESC sd = (SIM_DESC) sc->p1; */
/* OBSOLETE sim_cpu *cpu = STATE_CPU (sd, 0); */
/* OBSOLETE */
/* OBSOLETE return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes); */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE #endif /* _CPU_C_ */ */

498
sim/d30v/cpu.h
View File

@ -1,249 +1,249 @@
/* Mitsubishi Electric Corp. D30V Simulator.
Copyright (C) 1997, Free Software Foundation, Inc.
Contributed by Cygnus Support.
This file is part of GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#ifndef _CPU_H_
#define _CPU_H_
enum {
NR_GENERAL_PURPOSE_REGISTERS = 64,
NR_CONTROL_REGISTERS = 64,
NR_ACCUMULATORS = 2,
STACK_POINTER_GPR = 63,
NR_STACK_POINTERS = 2,
};
enum {
processor_status_word_cr = 0,
backup_processor_status_word_cr = 1,
program_counter_cr = 2,
backup_program_counter_cr = 3,
debug_backup_processor_status_word_cr = 4,
debug_backup_program_counter_cr = 5,
reserved_6_cr = 6,
repeat_count_cr = 7,
repeat_start_address_cr = 8,
repeat_end_address_cr = 9,
modulo_start_address_cr = 10,
modulo_end_address_cr = 11,
instruction_break_address_cr = 14,
eit_vector_base_cr = 15,
};
enum {
PSW_SM = 0,
PSW_EA = 2,
PSW_DB = 3,
PSW_DS = 4,
PSW_IE = 5,
PSW_RP = 6,
PSW_MD = 7,
PSW_F0 = 17,
PSW_F1 = 19,
PSW_F2 = 21,
PSW_F3 = 23,
PSW_S = 25,
PSW_V = 27,
PSW_VA = 29,
PSW_C = 31,
};
/* aliases for PSW flag numbers (F0..F7) */
enum
{
PSW_S_FLAG = 4,
};
typedef struct _registers {
unsigned32 general_purpose[NR_GENERAL_PURPOSE_REGISTERS];
/* keep track of the stack pointer */
unsigned32 sp[NR_STACK_POINTERS]; /* swap with SP */
unsigned32 current_sp;
unsigned32 control[NR_CONTROL_REGISTERS];
unsigned64 accumulator[NR_ACCUMULATORS];
} registers;
typedef enum _cpu_units {
memory_unit,
integer_unit,
any_unit,
} cpu_units;
/* In order to support parallel instructions, which one instruction can be
writing to a register that is used as input to another, queue up the
writes to the end of the instruction boundaries. */
#define MAX_WRITE32 16
#define MAX_WRITE64 2
struct _write32 {
int num; /* # of 32-bit writes queued up */
unsigned32 value[MAX_WRITE32]; /* value to write */
unsigned32 mask[MAX_WRITE32]; /* mask to use */
unsigned32 *ptr[MAX_WRITE32]; /* address to write to */
};
struct _write64 {
int num; /* # of 64-bit writes queued up */
unsigned64 value[MAX_WRITE64]; /* value to write */
unsigned64 *ptr[MAX_WRITE64]; /* address to write to */
};
struct _sim_cpu {
cpu_units unit;
registers regs;
sim_cpu_base base;
int trace_call_p; /* Whether to do call tracing. */
int trace_trap_p; /* If unknown traps dump out the regs */
int trace_action; /* trace bits at end of instructions */
int left_kills_right_p; /* left insn kills insn in right slot of -> */
int mvtsys_left_p; /* left insn was mvtsys */
int did_trap; /* we did a trap & need to finish it */
struct _write32 write32; /* queued up 32-bit writes */
struct _write64 write64; /* queued up 64-bit writes */
};
#define PC (STATE_CPU (sd, 0)->regs.control[program_counter_cr])
#define PSW (STATE_CPU (sd, 0)->regs.control[processor_status_word_cr])
#define PSWL (*AL2_4(&PSW))
#define PSWH (*AH2_4(&PSW))
#define DPSW (STATE_CPU (sd, 0)->regs.control[debug_backup_processor_status_word_cr])
#define DPC (STATE_CPU (sd, 0)->regs.control[debug_backup_program_counter_cr])
#define bPC (STATE_CPU (sd, 0)->regs.control[backup_program_counter_cr])
#define bPSW (STATE_CPU (sd, 0)->regs.control[backup_processor_status_word_cr])
#define RPT_C (STATE_CPU (sd, 0)->regs.control[repeat_count_cr])
#define RPT_S (STATE_CPU (sd, 0)->regs.control[repeat_start_address_cr])
#define RPT_E (STATE_CPU (sd, 0)->regs.control[repeat_end_address_cr])
#define MOD_S (STATE_CPU (sd, 0)->regs.control[modulo_start_address_cr])
#define MOD_E (STATE_CPU (sd, 0)->regs.control[modulo_end_address_cr])
#define IBA (STATE_CPU (sd, 0)->regs.control[instruction_break_address_cr])
#define EIT_VB (STATE_CPU (sd, 0)->regs.control[eit_vector_base_cr])
#define GPR (STATE_CPU (sd, 0)->regs.general_purpose)
#define GPR_CLEAR(N) (GPR[(N)] = 0)
#define ACC (STATE_CPU (sd, 0)->regs.accumulator)
#define CREG (STATE_CPU (sd, 0)->regs.control)
#define SP (GPR[STACK_POINTER_GPR])
#define TRACE_CALL_P (STATE_CPU (sd, 0)->trace_call_p)
#define TRACE_TRAP_P (STATE_CPU (sd, 0)->trace_trap_p)
#define TRACE_ACTION (STATE_CPU (sd, 0)->trace_action)
#define TRACE_ACTION_CALL 0x00000001 /* call occurred */
#define TRACE_ACTION_RETURN 0x00000002 /* return occurred */
#define WRITE32 (STATE_CPU (sd, 0)->write32)
#define WRITE32_NUM (WRITE32.num)
#define WRITE32_PTR(N) (WRITE32.ptr[N])
#define WRITE32_MASK(N) (WRITE32.mask[N])
#define WRITE32_VALUE(N) (WRITE32.value[N])
#define WRITE32_QUEUE(PTR, VALUE) WRITE32_QUEUE_MASK (PTR, VALUE, 0xffffffff)
#define WRITE32_QUEUE_MASK(PTR, VALUE, MASK) \
do { \
int _num = WRITE32_NUM; \
if (_num >= MAX_WRITE32) \
sim_engine_abort (sd, STATE_CPU (sd, 0), cia, \
"Too many queued 32-bit writes"); \
WRITE32_PTR(_num) = PTR; \
WRITE32_VALUE(_num) = VALUE; \
WRITE32_MASK(_num) = MASK; \
WRITE32_NUM = _num+1; \
} while (0)
#define DID_TRAP (STATE_CPU (sd, 0)->did_trap)
#define WRITE64 (STATE_CPU (sd, 0)->write64)
#define WRITE64_NUM (WRITE64.num)
#define WRITE64_PTR(N) (WRITE64.ptr[N])
#define WRITE64_VALUE(N) (WRITE64.value[N])
#define WRITE64_QUEUE(PTR, VALUE) \
do { \
int _num = WRITE64_NUM; \
if (_num >= MAX_WRITE64) \
sim_engine_abort (sd, STATE_CPU (sd, 0), cia, \
"Too many queued 64-bit writes"); \
WRITE64_PTR(_num) = PTR; \
WRITE64_VALUE(_num) = VALUE; \
WRITE64_NUM = _num+1; \
} while (0)
#define DPSW_VALID 0xbf005555
#define PSW_VALID 0xb7005555
#define EIT_VALID 0xfffff000 /* From page 7-4 of D30V/MPEG arch. manual */
#define EIT_VB_DEFAULT 0xfffff000 /* Value of the EIT_VB register after reset */
/* Verify that the instruction is in the correct slot */
#define IS_WRONG_SLOT is_wrong_slot(sd, cia, MY_INDEX)
extern int is_wrong_slot
(SIM_DESC sd,
address_word cia,
itable_index index);
#define IS_CONDITION_OK is_condition_ok(sd, cia, CCC)
extern int is_condition_ok
(SIM_DESC sd,
address_word cia,
int cond);
#define SIM_HAVE_BREAKPOINTS /* Turn on internal breakpoint module */
/* Internal breakpoint instruction is syscall 5 */
#define SIM_BREAKPOINT {0x0e, 0x00, 0x00, 0x05}
#define SIM_BREAKPOINT_SIZE (4)
/* Call occurred */
extern void call_occurred
(SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
address_word nia);
/* Return occurred */
extern void return_occurred
(SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
address_word nia);
/* Whether to do call tracing. */
extern int d30v_call_trace_p;
/* Read/write functions for system call interface. */
extern int d30v_read_mem
(host_callback *cb,
struct cb_syscall *sc,
unsigned long taddr,
char *buf,
int bytes);
extern int d30v_write_mem
(host_callback *cb,
struct cb_syscall *sc,
unsigned long taddr,
const char *buf,
int bytes);
/* Process all of the queued up writes in order now */
void unqueue_writes
(SIM_DESC sd,
sim_cpu *cpu,
address_word cia);
#endif /* _CPU_H_ */
/* OBSOLETE /* Mitsubishi Electric Corp. D30V Simulator. */
/* OBSOLETE Copyright (C) 1997, Free Software Foundation, Inc. */
/* OBSOLETE Contributed by Cygnus Support. */
/* OBSOLETE */
/* OBSOLETE This file is part of GDB, the GNU debugger. */
/* OBSOLETE */
/* OBSOLETE This program is free software; you can redistribute it and/or modify */
/* OBSOLETE it under the terms of the GNU General Public License as published by */
/* OBSOLETE the Free Software Foundation; either version 2, or (at your option) */
/* OBSOLETE any later version. */
/* OBSOLETE */
/* OBSOLETE This program is distributed in the hope that it will be useful, */
/* OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of */
/* OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
/* OBSOLETE GNU General Public License for more details. */
/* OBSOLETE */
/* OBSOLETE You should have received a copy of the GNU General Public License along */
/* OBSOLETE with this program; if not, write to the Free Software Foundation, Inc., */
/* OBSOLETE 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE #ifndef _CPU_H_ */
/* OBSOLETE #define _CPU_H_ */
/* OBSOLETE */
/* OBSOLETE enum { */
/* OBSOLETE NR_GENERAL_PURPOSE_REGISTERS = 64, */
/* OBSOLETE NR_CONTROL_REGISTERS = 64, */
/* OBSOLETE NR_ACCUMULATORS = 2, */
/* OBSOLETE STACK_POINTER_GPR = 63, */
/* OBSOLETE NR_STACK_POINTERS = 2, */
/* OBSOLETE }; */
/* OBSOLETE */
/* OBSOLETE enum { */
/* OBSOLETE processor_status_word_cr = 0, */
/* OBSOLETE backup_processor_status_word_cr = 1, */
/* OBSOLETE program_counter_cr = 2, */
/* OBSOLETE backup_program_counter_cr = 3, */
/* OBSOLETE debug_backup_processor_status_word_cr = 4, */
/* OBSOLETE debug_backup_program_counter_cr = 5, */
/* OBSOLETE reserved_6_cr = 6, */
/* OBSOLETE repeat_count_cr = 7, */
/* OBSOLETE repeat_start_address_cr = 8, */
/* OBSOLETE repeat_end_address_cr = 9, */
/* OBSOLETE modulo_start_address_cr = 10, */
/* OBSOLETE modulo_end_address_cr = 11, */
/* OBSOLETE instruction_break_address_cr = 14, */
/* OBSOLETE eit_vector_base_cr = 15, */
/* OBSOLETE }; */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE enum { */
/* OBSOLETE PSW_SM = 0, */
/* OBSOLETE PSW_EA = 2, */
/* OBSOLETE PSW_DB = 3, */
/* OBSOLETE PSW_DS = 4, */
/* OBSOLETE PSW_IE = 5, */
/* OBSOLETE PSW_RP = 6, */
/* OBSOLETE PSW_MD = 7, */
/* OBSOLETE PSW_F0 = 17, */
/* OBSOLETE PSW_F1 = 19, */
/* OBSOLETE PSW_F2 = 21, */
/* OBSOLETE PSW_F3 = 23, */
/* OBSOLETE PSW_S = 25, */
/* OBSOLETE PSW_V = 27, */
/* OBSOLETE PSW_VA = 29, */
/* OBSOLETE PSW_C = 31, */
/* OBSOLETE }; */
/* OBSOLETE */
/* OBSOLETE /* aliases for PSW flag numbers (F0..F7) */ */
/* OBSOLETE enum */
/* OBSOLETE { */
/* OBSOLETE PSW_S_FLAG = 4, */
/* OBSOLETE }; */
/* OBSOLETE */
/* OBSOLETE typedef struct _registers { */
/* OBSOLETE unsigned32 general_purpose[NR_GENERAL_PURPOSE_REGISTERS]; */
/* OBSOLETE /* keep track of the stack pointer */ */
/* OBSOLETE unsigned32 sp[NR_STACK_POINTERS]; /* swap with SP */ */
/* OBSOLETE unsigned32 current_sp; */
/* OBSOLETE unsigned32 control[NR_CONTROL_REGISTERS]; */
/* OBSOLETE unsigned64 accumulator[NR_ACCUMULATORS]; */
/* OBSOLETE } registers; */
/* OBSOLETE */
/* OBSOLETE typedef enum _cpu_units { */
/* OBSOLETE memory_unit, */
/* OBSOLETE integer_unit, */
/* OBSOLETE any_unit, */
/* OBSOLETE } cpu_units; */
/* OBSOLETE */
/* OBSOLETE /* In order to support parallel instructions, which one instruction can be */
/* OBSOLETE writing to a register that is used as input to another, queue up the */
/* OBSOLETE writes to the end of the instruction boundaries. */ */
/* OBSOLETE */
/* OBSOLETE #define MAX_WRITE32 16 */
/* OBSOLETE #define MAX_WRITE64 2 */
/* OBSOLETE */
/* OBSOLETE struct _write32 { */
/* OBSOLETE int num; /* # of 32-bit writes queued up */ */
/* OBSOLETE unsigned32 value[MAX_WRITE32]; /* value to write */ */
/* OBSOLETE unsigned32 mask[MAX_WRITE32]; /* mask to use */ */
/* OBSOLETE unsigned32 *ptr[MAX_WRITE32]; /* address to write to */ */
/* OBSOLETE }; */
/* OBSOLETE */
/* OBSOLETE struct _write64 { */
/* OBSOLETE int num; /* # of 64-bit writes queued up */ */
/* OBSOLETE unsigned64 value[MAX_WRITE64]; /* value to write */ */
/* OBSOLETE unsigned64 *ptr[MAX_WRITE64]; /* address to write to */ */
/* OBSOLETE }; */
/* OBSOLETE */
/* OBSOLETE struct _sim_cpu { */
/* OBSOLETE cpu_units unit; */
/* OBSOLETE registers regs; */
/* OBSOLETE sim_cpu_base base; */
/* OBSOLETE int trace_call_p; /* Whether to do call tracing. */ */
/* OBSOLETE int trace_trap_p; /* If unknown traps dump out the regs */ */
/* OBSOLETE int trace_action; /* trace bits at end of instructions */ */
/* OBSOLETE int left_kills_right_p; /* left insn kills insn in right slot of -> */ */
/* OBSOLETE int mvtsys_left_p; /* left insn was mvtsys */ */
/* OBSOLETE int did_trap; /* we did a trap & need to finish it */ */
/* OBSOLETE struct _write32 write32; /* queued up 32-bit writes */ */
/* OBSOLETE struct _write64 write64; /* queued up 64-bit writes */ */
/* OBSOLETE }; */
/* OBSOLETE */
/* OBSOLETE #define PC (STATE_CPU (sd, 0)->regs.control[program_counter_cr]) */
/* OBSOLETE #define PSW (STATE_CPU (sd, 0)->regs.control[processor_status_word_cr]) */
/* OBSOLETE #define PSWL (*AL2_4(&PSW)) */
/* OBSOLETE #define PSWH (*AH2_4(&PSW)) */
/* OBSOLETE #define DPSW (STATE_CPU (sd, 0)->regs.control[debug_backup_processor_status_word_cr]) */
/* OBSOLETE #define DPC (STATE_CPU (sd, 0)->regs.control[debug_backup_program_counter_cr]) */
/* OBSOLETE #define bPC (STATE_CPU (sd, 0)->regs.control[backup_program_counter_cr]) */
/* OBSOLETE #define bPSW (STATE_CPU (sd, 0)->regs.control[backup_processor_status_word_cr]) */
/* OBSOLETE #define RPT_C (STATE_CPU (sd, 0)->regs.control[repeat_count_cr]) */
/* OBSOLETE #define RPT_S (STATE_CPU (sd, 0)->regs.control[repeat_start_address_cr]) */
/* OBSOLETE #define RPT_E (STATE_CPU (sd, 0)->regs.control[repeat_end_address_cr]) */
/* OBSOLETE #define MOD_S (STATE_CPU (sd, 0)->regs.control[modulo_start_address_cr]) */
/* OBSOLETE #define MOD_E (STATE_CPU (sd, 0)->regs.control[modulo_end_address_cr]) */
/* OBSOLETE #define IBA (STATE_CPU (sd, 0)->regs.control[instruction_break_address_cr]) */
/* OBSOLETE #define EIT_VB (STATE_CPU (sd, 0)->regs.control[eit_vector_base_cr]) */
/* OBSOLETE #define GPR (STATE_CPU (sd, 0)->regs.general_purpose) */
/* OBSOLETE #define GPR_CLEAR(N) (GPR[(N)] = 0) */
/* OBSOLETE #define ACC (STATE_CPU (sd, 0)->regs.accumulator) */
/* OBSOLETE #define CREG (STATE_CPU (sd, 0)->regs.control) */
/* OBSOLETE #define SP (GPR[STACK_POINTER_GPR]) */
/* OBSOLETE #define TRACE_CALL_P (STATE_CPU (sd, 0)->trace_call_p) */
/* OBSOLETE #define TRACE_TRAP_P (STATE_CPU (sd, 0)->trace_trap_p) */
/* OBSOLETE #define TRACE_ACTION (STATE_CPU (sd, 0)->trace_action) */
/* OBSOLETE #define TRACE_ACTION_CALL 0x00000001 /* call occurred */ */
/* OBSOLETE #define TRACE_ACTION_RETURN 0x00000002 /* return occurred */ */
/* OBSOLETE */
/* OBSOLETE #define WRITE32 (STATE_CPU (sd, 0)->write32) */
/* OBSOLETE #define WRITE32_NUM (WRITE32.num) */
/* OBSOLETE #define WRITE32_PTR(N) (WRITE32.ptr[N]) */
/* OBSOLETE #define WRITE32_MASK(N) (WRITE32.mask[N]) */
/* OBSOLETE #define WRITE32_VALUE(N) (WRITE32.value[N]) */
/* OBSOLETE #define WRITE32_QUEUE(PTR, VALUE) WRITE32_QUEUE_MASK (PTR, VALUE, 0xffffffff) */
/* OBSOLETE */
/* OBSOLETE #define WRITE32_QUEUE_MASK(PTR, VALUE, MASK) \ */
/* OBSOLETE do { \ */
/* OBSOLETE int _num = WRITE32_NUM; \ */
/* OBSOLETE if (_num >= MAX_WRITE32) \ */
/* OBSOLETE sim_engine_abort (sd, STATE_CPU (sd, 0), cia, \ */
/* OBSOLETE "Too many queued 32-bit writes"); \ */
/* OBSOLETE WRITE32_PTR(_num) = PTR; \ */
/* OBSOLETE WRITE32_VALUE(_num) = VALUE; \ */
/* OBSOLETE WRITE32_MASK(_num) = MASK; \ */
/* OBSOLETE WRITE32_NUM = _num+1; \ */
/* OBSOLETE } while (0) */
/* OBSOLETE */
/* OBSOLETE #define DID_TRAP (STATE_CPU (sd, 0)->did_trap) */
/* OBSOLETE */
/* OBSOLETE #define WRITE64 (STATE_CPU (sd, 0)->write64) */
/* OBSOLETE #define WRITE64_NUM (WRITE64.num) */
/* OBSOLETE #define WRITE64_PTR(N) (WRITE64.ptr[N]) */
/* OBSOLETE #define WRITE64_VALUE(N) (WRITE64.value[N]) */
/* OBSOLETE #define WRITE64_QUEUE(PTR, VALUE) \ */
/* OBSOLETE do { \ */
/* OBSOLETE int _num = WRITE64_NUM; \ */
/* OBSOLETE if (_num >= MAX_WRITE64) \ */
/* OBSOLETE sim_engine_abort (sd, STATE_CPU (sd, 0), cia, \ */
/* OBSOLETE "Too many queued 64-bit writes"); \ */
/* OBSOLETE WRITE64_PTR(_num) = PTR; \ */
/* OBSOLETE WRITE64_VALUE(_num) = VALUE; \ */
/* OBSOLETE WRITE64_NUM = _num+1; \ */
/* OBSOLETE } while (0) */
/* OBSOLETE */
/* OBSOLETE #define DPSW_VALID 0xbf005555 */
/* OBSOLETE #define PSW_VALID 0xb7005555 */
/* OBSOLETE #define EIT_VALID 0xfffff000 /* From page 7-4 of D30V/MPEG arch. manual */ */
/* OBSOLETE #define EIT_VB_DEFAULT 0xfffff000 /* Value of the EIT_VB register after reset */ */
/* OBSOLETE */
/* OBSOLETE /* Verify that the instruction is in the correct slot */ */
/* OBSOLETE */
/* OBSOLETE #define IS_WRONG_SLOT is_wrong_slot(sd, cia, MY_INDEX) */
/* OBSOLETE extern int is_wrong_slot */
/* OBSOLETE (SIM_DESC sd, */
/* OBSOLETE address_word cia, */
/* OBSOLETE itable_index index); */
/* OBSOLETE */
/* OBSOLETE #define IS_CONDITION_OK is_condition_ok(sd, cia, CCC) */
/* OBSOLETE extern int is_condition_ok */
/* OBSOLETE (SIM_DESC sd, */
/* OBSOLETE address_word cia, */
/* OBSOLETE int cond); */
/* OBSOLETE */
/* OBSOLETE #define SIM_HAVE_BREAKPOINTS /* Turn on internal breakpoint module */ */
/* OBSOLETE */
/* OBSOLETE /* Internal breakpoint instruction is syscall 5 */ */
/* OBSOLETE #define SIM_BREAKPOINT {0x0e, 0x00, 0x00, 0x05} */
/* OBSOLETE #define SIM_BREAKPOINT_SIZE (4) */
/* OBSOLETE */
/* OBSOLETE /* Call occurred */ */
/* OBSOLETE extern void call_occurred */
/* OBSOLETE (SIM_DESC sd, */
/* OBSOLETE sim_cpu *cpu, */
/* OBSOLETE address_word cia, */
/* OBSOLETE address_word nia); */
/* OBSOLETE */
/* OBSOLETE /* Return occurred */ */
/* OBSOLETE extern void return_occurred */
/* OBSOLETE (SIM_DESC sd, */
/* OBSOLETE sim_cpu *cpu, */
/* OBSOLETE address_word cia, */
/* OBSOLETE address_word nia); */
/* OBSOLETE */
/* OBSOLETE /* Whether to do call tracing. */ */
/* OBSOLETE extern int d30v_call_trace_p; */
/* OBSOLETE */
/* OBSOLETE /* Read/write functions for system call interface. */ */
/* OBSOLETE extern int d30v_read_mem */
/* OBSOLETE (host_callback *cb, */
/* OBSOLETE struct cb_syscall *sc, */
/* OBSOLETE unsigned long taddr, */
/* OBSOLETE char *buf, */
/* OBSOLETE int bytes); */
/* OBSOLETE */
/* OBSOLETE extern int d30v_write_mem */
/* OBSOLETE (host_callback *cb, */
/* OBSOLETE struct cb_syscall *sc, */
/* OBSOLETE unsigned long taddr, */
/* OBSOLETE const char *buf, */
/* OBSOLETE int bytes); */
/* OBSOLETE */
/* OBSOLETE /* Process all of the queued up writes in order now */ */
/* OBSOLETE void unqueue_writes */
/* OBSOLETE (SIM_DESC sd, */
/* OBSOLETE sim_cpu *cpu, */
/* OBSOLETE address_word cia); */
/* OBSOLETE */
/* OBSOLETE #endif /* _CPU_H_ */ */

4845
sim/d30v/d30v-insns
View File

File diff suppressed because it is too large Load Diff

44
sim/d30v/dc-short
View File

@ -1,22 +1,22 @@
//
// Mitsubishi Electric Corp. D30V Simulator.
// Copyright (C) 1997, Free Software Foundation, Inc.
// Contributed by Cygnus Solutions Inc.
//
// This file is part of GDB, the GNU debugger.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
//
switch: 4: 13: 4: 13
# OBSOLETE //
# OBSOLETE // Mitsubishi Electric Corp. D30V Simulator.
# OBSOLETE // Copyright (C) 1997, Free Software Foundation, Inc.
# OBSOLETE // Contributed by Cygnus Solutions Inc.
# OBSOLETE //
# OBSOLETE // This file is part of GDB, the GNU debugger.
# OBSOLETE //
# OBSOLETE // This program is free software; you can redistribute it and/or modify
# OBSOLETE // it under the terms of the GNU General Public License as published by
# OBSOLETE // the Free Software Foundation; either version 2 of the License, or
# OBSOLETE // (at your option) any later version.
# OBSOLETE //
# OBSOLETE // This program is distributed in the hope that it will be useful,
# OBSOLETE // but WITHOUT ANY WARRANTY; without even the implied warranty of
# OBSOLETE // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# OBSOLETE // GNU General Public License for more details.
# OBSOLETE //
# OBSOLETE // You should have received a copy of the GNU General Public License
# OBSOLETE // along with this program; if not, write to the Free Software
# OBSOLETE // Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
# OBSOLETE //
# OBSOLETE switch: 4: 13: 4: 13

992
sim/d30v/engine.c
View File

@ -1,496 +1,496 @@
/* This file is part of the program psim.
Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
Copyright (C) 1996, 1997, Free Software Foundation
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef ENGINE_C
#define ENGINE_C
#include "sim-main.h"
#include <stdio.h>
#include <ctype.h>
#ifdef HAVE_STDLIB_H
#include <stdlib.h>
#endif
#ifdef HAVE_STRING_H
#include <string.h>
#else
#ifdef HAVE_STRINGS_H
#include <strings.h>
#endif
#endif
static void
do_stack_swap (SIM_DESC sd)
{
sim_cpu *cpu = STATE_CPU (sd, 0);
unsigned new_sp = (PSW_VAL(PSW_SM) != 0);
if (cpu->regs.current_sp != new_sp)
{
cpu->regs.sp[cpu->regs.current_sp] = SP;
cpu->regs.current_sp = new_sp;
SP = cpu->regs.sp[cpu->regs.current_sp];
}
}
#if WITH_TRACE
/* Implement ALU tracing of 32-bit registers. */
static void
trace_alu32 (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
unsigned32 *ptr)
{
unsigned32 value = *ptr;
if (ptr >= &GPR[0] && ptr <= &GPR[NR_GENERAL_PURPOSE_REGISTERS])
trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu",
"Set register r%-2d = 0x%.8lx (%ld)",
ptr - &GPR[0], (long)value, (long)value);
else if (ptr == &PSW || ptr == &bPSW || ptr == &DPSW)
trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu",
"Set register %s = 0x%.8lx%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
(ptr == &PSW) ? "psw" : ((ptr == &bPSW) ? "bpsw" : "dpsw"),
(long)value,
(value & (0x80000000 >> PSW_SM)) ? ", sm" : "",
(value & (0x80000000 >> PSW_EA)) ? ", ea" : "",
(value & (0x80000000 >> PSW_DB)) ? ", db" : "",
(value & (0x80000000 >> PSW_DS)) ? ", ds" : "",
(value & (0x80000000 >> PSW_IE)) ? ", ie" : "",
(value & (0x80000000 >> PSW_RP)) ? ", rp" : "",
(value & (0x80000000 >> PSW_MD)) ? ", md" : "",
(value & (0x80000000 >> PSW_F0)) ? ", f0" : "",
(value & (0x80000000 >> PSW_F1)) ? ", f1" : "",
(value & (0x80000000 >> PSW_F2)) ? ", f2" : "",
(value & (0x80000000 >> PSW_F3)) ? ", f3" : "",
(value & (0x80000000 >> PSW_S)) ? ", s" : "",
(value & (0x80000000 >> PSW_V)) ? ", v" : "",
(value & (0x80000000 >> PSW_VA)) ? ", va" : "",
(value & (0x80000000 >> PSW_C)) ? ", c" : "");
else if (ptr >= &CREG[0] && ptr <= &CREG[NR_CONTROL_REGISTERS])
trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu",
"Set register cr%d = 0x%.8lx (%ld)",
ptr - &CREG[0], (long)value, (long)value);
}
/* Implement ALU tracing of 32-bit registers. */
static void
trace_alu64 (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
unsigned64 *ptr)
{
unsigned64 value = *ptr;
if (ptr >= &ACC[0] && ptr <= &ACC[NR_ACCUMULATORS])
trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu",
"Set register a%-2d = 0x%.8lx 0x%.8lx",
ptr - &ACC[0],
(unsigned long)(unsigned32)(value >> 32),
(unsigned long)(unsigned32)value);
}
#endif
/* Process all of the queued up writes in order now */
void
unqueue_writes (SIM_DESC sd,
sim_cpu *cpu,
address_word cia)
{
int i, num;
int did_psw = 0;
unsigned32 *psw_addr = &PSW;
num = WRITE32_NUM;
for (i = 0; i < num; i++)
{
unsigned32 mask = WRITE32_MASK (i);
unsigned32 *ptr = WRITE32_PTR (i);
unsigned32 value = (*ptr & ~mask) | (WRITE32_VALUE (i) & mask);
int j;
if (ptr == psw_addr)
{
/* If MU instruction was not a MVTSYS, resolve PSW
contention in favour of IU. */
if(! STATE_CPU (sd, 0)->mvtsys_left_p)
{
/* Detect contention in parallel writes to the same PSW flags.
The hardware allows the updates from IU to prevail over
those from MU. */
unsigned32 flag_bits =
BIT32 (PSW_F0) | BIT32 (PSW_F1) |
BIT32 (PSW_F2) | BIT32 (PSW_F3) |
BIT32 (PSW_S) | BIT32 (PSW_V) |
BIT32 (PSW_VA) | BIT32 (PSW_C);
unsigned32 my_flag_bits = mask & flag_bits;
for (j = i + 1; j < num; j++)
if (WRITE32_PTR (j) == psw_addr && /* write to PSW */
WRITE32_MASK (j) & my_flag_bits) /* some of the same flags */
{
/* Recompute local mask & value, to suppress this
earlier write to the same flag bits. */
unsigned32 new_mask = mask & ~(WRITE32_MASK (j) & my_flag_bits);
/* There is a special case for the VA (accumulated
overflow) flag, in that it is only included in the
second instruction's mask if the overflow
occurred. Yet the hardware still suppresses the
first instruction's update to VA. So we kludge
this by inferring PSW_V -> PSW_VA for the second
instruction. */
if (WRITE32_MASK (j) & BIT32 (PSW_V))
{
new_mask &= ~BIT32 (PSW_VA);
}
value = (*ptr & ~new_mask) | (WRITE32_VALUE (i) & new_mask);
}
}
did_psw = 1;
}
*ptr = value;
#if WITH_TRACE
if (TRACE_ALU_P (cpu))
trace_alu32 (sd, cpu, cia, ptr);
#endif
}
num = WRITE64_NUM;
for (i = 0; i < num; i++)
{
unsigned64 *ptr = WRITE64_PTR (i);
*ptr = WRITE64_VALUE (i);
#if WITH_TRACE
if (TRACE_ALU_P (cpu))
trace_alu64 (sd, cpu, cia, ptr);
#endif
}
WRITE32_NUM = 0;
WRITE64_NUM = 0;
if (DID_TRAP == 1) /* ordinary trap */
{
bPSW = PSW;
PSW &= (BIT32 (PSW_DB) | BIT32 (PSW_SM));
did_psw = 1;
}
else if (DID_TRAP == 2) /* debug trap */
{
DPSW = PSW;
PSW &= BIT32 (PSW_DS);
PSW |= BIT32 (PSW_DS);
did_psw = 1;
}
DID_TRAP = 0;
if (did_psw)
do_stack_swap (sd);
}
/* SIMULATE INSTRUCTIONS, various different ways of achieving the same
thing */
static address_word
do_long (SIM_DESC sd,
l_instruction_word instruction,
address_word cia)
{
address_word nia = l_idecode_issue(sd,
instruction,
cia);
unqueue_writes (sd, STATE_CPU (sd, 0), cia);
return nia;
}
static address_word
do_2_short (SIM_DESC sd,
s_instruction_word insn1,
s_instruction_word insn2,
cpu_units unit,
address_word cia)
{
address_word nia;
/* run the first instruction */
STATE_CPU (sd, 0)->unit = unit;
STATE_CPU (sd, 0)->left_kills_right_p = 0;
STATE_CPU (sd, 0)->mvtsys_left_p = 0;
nia = s_idecode_issue(sd,
insn1,
cia);
unqueue_writes (sd, STATE_CPU (sd, 0), cia);
/* Only do the second instruction if the PC has not changed */
if ((nia == INVALID_INSTRUCTION_ADDRESS) &&
(! STATE_CPU (sd, 0)->left_kills_right_p)) {
STATE_CPU (sd, 0)->unit = any_unit;
nia = s_idecode_issue (sd,
insn2,
cia);
unqueue_writes (sd, STATE_CPU (sd, 0), cia);
}
STATE_CPU (sd, 0)->left_kills_right_p = 0;
STATE_CPU (sd, 0)->mvtsys_left_p = 0;
return nia;
}
static address_word
do_parallel (SIM_DESC sd,
s_instruction_word left_insn,
s_instruction_word right_insn,
address_word cia)
{
address_word nia_left;
address_word nia_right;
address_word nia;
/* run the first instruction */
STATE_CPU (sd, 0)->unit = memory_unit;
STATE_CPU (sd, 0)->left_kills_right_p = 0;
STATE_CPU (sd, 0)->mvtsys_left_p = 0;
nia_left = s_idecode_issue(sd,
left_insn,
cia);
/* run the second instruction */
STATE_CPU (sd, 0)->unit = integer_unit;
nia_right = s_idecode_issue(sd,
right_insn,
cia);
/* merge the PC's */
if (nia_left == INVALID_INSTRUCTION_ADDRESS) {
if (nia_right == INVALID_INSTRUCTION_ADDRESS)
nia = INVALID_INSTRUCTION_ADDRESS;
else
nia = nia_right;
}
else {
if (nia_right == INVALID_INSTRUCTION_ADDRESS)
nia = nia_left;
else {
sim_engine_abort (sd, STATE_CPU (sd, 0), cia, "parallel jumps");
nia = INVALID_INSTRUCTION_ADDRESS;
}
}
unqueue_writes (sd, STATE_CPU (sd, 0), cia);
return nia;
}
typedef enum {
p_insn = 0,
long_insn = 3,
l_r_insn = 1,
r_l_insn = 2,
} instruction_types;
STATIC_INLINE instruction_types
instruction_type(l_instruction_word insn)
{
int fm0 = MASKED64(insn, 0, 0) != 0;
int fm1 = MASKED64(insn, 32, 32) != 0;
return ((fm0 << 1) | fm1);
}
void
sim_engine_run (SIM_DESC sd,
int last_cpu_nr,
int nr_cpus,
int siggnal)
{
while (1)
{
address_word cia = PC;
address_word nia;
l_instruction_word insn = IMEM(cia);
int rp_was_set;
int rpt_c_was_nonzero;
/* Before executing the instruction, we need to test whether or
not RPT_C is greater than zero, and save that state for use
after executing the instruction. In particular, we need to
not care whether the instruction changes RPT_C itself. */
rpt_c_was_nonzero = (RPT_C > 0);
/* Before executing the instruction, we need to check to see if
we have to decrement RPT_C, the repeat count register. Do this
if PC == RPT_E, but only if we are in an active repeat block. */
if (PC == RPT_E &&
(RPT_C > 0 || PSW_VAL (PSW_RP) != 0))
{
RPT_C --;
}
/* Now execute the instruction at PC */
switch (instruction_type (insn))
{
case long_insn:
nia = do_long (sd, insn, cia);
break;
case r_l_insn:
/* L <- R */
nia = do_2_short (sd, insn, insn >> 32, integer_unit, cia);
break;
case l_r_insn:
/* L -> R */
nia = do_2_short (sd, insn >> 32, insn, memory_unit, cia);
break;
case p_insn:
nia = do_parallel (sd, insn >> 32, insn, cia);
break;
default:
sim_engine_abort (sd, STATE_CPU (sd, 0), cia,
"internal error - engine_run_until_stop - bad switch");
nia = -1;
}
if (TRACE_ACTION)
{
if (TRACE_ACTION & TRACE_ACTION_CALL)
call_occurred (sd, STATE_CPU (sd, 0), cia, nia);
if (TRACE_ACTION & TRACE_ACTION_RETURN)
return_occurred (sd, STATE_CPU (sd, 0), cia, nia);
TRACE_ACTION = 0;
}
/* Check now to see if we need to reset the RP bit in the PSW.
There are three conditions for this, the RP bit is already
set (just a speed optimization), the instruction we just
executed is the last instruction in the loop, and the repeat
count is currently zero. */
rp_was_set = PSW_VAL (PSW_RP);
if (rp_was_set && (PC == RPT_E) && RPT_C == 0)
{
PSW_SET (PSW_RP, 0);
}
/* Now update the PC. If we just executed a jump instruction,
that takes precedence over everything else. Next comes
branching back to RPT_S as a result of a loop. Finally, the
default is to simply advance to the next inline
instruction. */
if (nia != INVALID_INSTRUCTION_ADDRESS)
{
PC = nia;
}
else if (rp_was_set && rpt_c_was_nonzero && (PC == RPT_E))
{
PC = RPT_S;
}
else
{
PC = cia + 8;
}
/* Check for DDBT (debugger debug trap) condition. Do this after
the repeat block checks so the excursion to the trap handler does
not alter looping state. */
if (cia == IBA && PSW_VAL (PSW_DB))
{
DPC = PC;
PSW_SET (PSW_EA, 1);
DPSW = PSW;
/* clear all bits in PSW except SM */
PSW &= BIT32 (PSW_SM);
/* add DS bit */
PSW |= BIT32 (PSW_DS);
/* dispatch to DDBT handler */
PC = 0xfffff128; /* debugger_debug_trap_address */
}
/* process any events */
/* FIXME - should L->R or L<-R insns count as two cycles? */
if (sim_events_tick (sd))
{
sim_events_process (sd);
}
}
}
/* d30v external interrupt handler.
Note: This should be replaced by a proper interrupt delivery
mechanism. This interrupt mechanism discards later interrupts if
an earlier interrupt hasn't been delivered.
Note: This interrupt mechanism does not reset its self when the
simulator is re-opened. */
void
d30v_interrupt_event (SIM_DESC sd,
void *data)
{
if (PSW_VAL (PSW_IE))
/* interrupts not masked */
{
/* scrub any pending interrupt */
if (sd->pending_interrupt != NULL)
sim_events_deschedule (sd, sd->pending_interrupt);
/* deliver */
bPSW = PSW;
bPC = PC;
PSW = 0;
PC = 0xfffff138; /* external interrupt */
do_stack_swap (sd);
}
else if (sd->pending_interrupt == NULL)
/* interrupts masked and no interrupt pending */
{
sd->pending_interrupt = sim_events_schedule (sd, 1,
d30v_interrupt_event,
data);
}
}
#endif
/* OBSOLETE /* This file is part of the program psim. */
/* OBSOLETE */
/* OBSOLETE Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au> */
/* OBSOLETE Copyright (C) 1996, 1997, Free Software Foundation */
/* OBSOLETE */
/* OBSOLETE This program is free software; you can redistribute it and/or modify */
/* OBSOLETE it under the terms of the GNU General Public License as published by */
/* OBSOLETE the Free Software Foundation; either version 2 of the License, or */
/* OBSOLETE (at your option) any later version. */
/* OBSOLETE */
/* OBSOLETE This program is distributed in the hope that it will be useful, */
/* OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of */
/* OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
/* OBSOLETE GNU General Public License for more details. */
/* OBSOLETE */
/* OBSOLETE You should have received a copy of the GNU General Public License */
/* OBSOLETE along with this program; if not, write to the Free Software */
/* OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
/* OBSOLETE */
/* OBSOLETE */ */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE #ifndef ENGINE_C */
/* OBSOLETE #define ENGINE_C */
/* OBSOLETE */
/* OBSOLETE #include "sim-main.h" */
/* OBSOLETE */
/* OBSOLETE #include <stdio.h> */
/* OBSOLETE #include <ctype.h> */
/* OBSOLETE */
/* OBSOLETE #ifdef HAVE_STDLIB_H */
/* OBSOLETE #include <stdlib.h> */
/* OBSOLETE #endif */
/* OBSOLETE */
/* OBSOLETE #ifdef HAVE_STRING_H */
/* OBSOLETE #include <string.h> */
/* OBSOLETE #else */
/* OBSOLETE #ifdef HAVE_STRINGS_H */
/* OBSOLETE #include <strings.h> */
/* OBSOLETE #endif */
/* OBSOLETE #endif */
/* OBSOLETE */
/* OBSOLETE static void */
/* OBSOLETE do_stack_swap (SIM_DESC sd) */
/* OBSOLETE { */
/* OBSOLETE sim_cpu *cpu = STATE_CPU (sd, 0); */
/* OBSOLETE unsigned new_sp = (PSW_VAL(PSW_SM) != 0); */
/* OBSOLETE if (cpu->regs.current_sp != new_sp) */
/* OBSOLETE { */
/* OBSOLETE cpu->regs.sp[cpu->regs.current_sp] = SP; */
/* OBSOLETE cpu->regs.current_sp = new_sp; */
/* OBSOLETE SP = cpu->regs.sp[cpu->regs.current_sp]; */
/* OBSOLETE } */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE #if WITH_TRACE */
/* OBSOLETE /* Implement ALU tracing of 32-bit registers. */ */
/* OBSOLETE static void */
/* OBSOLETE trace_alu32 (SIM_DESC sd, */
/* OBSOLETE sim_cpu *cpu, */
/* OBSOLETE address_word cia, */
/* OBSOLETE unsigned32 *ptr) */
/* OBSOLETE { */
/* OBSOLETE unsigned32 value = *ptr; */
/* OBSOLETE */
/* OBSOLETE if (ptr >= &GPR[0] && ptr <= &GPR[NR_GENERAL_PURPOSE_REGISTERS]) */
/* OBSOLETE trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu", */
/* OBSOLETE "Set register r%-2d = 0x%.8lx (%ld)", */
/* OBSOLETE ptr - &GPR[0], (long)value, (long)value); */
/* OBSOLETE */
/* OBSOLETE else if (ptr == &PSW || ptr == &bPSW || ptr == &DPSW) */
/* OBSOLETE trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu", */
/* OBSOLETE "Set register %s = 0x%.8lx%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", */
/* OBSOLETE (ptr == &PSW) ? "psw" : ((ptr == &bPSW) ? "bpsw" : "dpsw"), */
/* OBSOLETE (long)value, */
/* OBSOLETE (value & (0x80000000 >> PSW_SM)) ? ", sm" : "", */
/* OBSOLETE (value & (0x80000000 >> PSW_EA)) ? ", ea" : "", */
/* OBSOLETE (value & (0x80000000 >> PSW_DB)) ? ", db" : "", */
/* OBSOLETE (value & (0x80000000 >> PSW_DS)) ? ", ds" : "", */
/* OBSOLETE (value & (0x80000000 >> PSW_IE)) ? ", ie" : "", */
/* OBSOLETE (value & (0x80000000 >> PSW_RP)) ? ", rp" : "", */
/* OBSOLETE (value & (0x80000000 >> PSW_MD)) ? ", md" : "", */
/* OBSOLETE (value & (0x80000000 >> PSW_F0)) ? ", f0" : "", */
/* OBSOLETE (value & (0x80000000 >> PSW_F1)) ? ", f1" : "", */
/* OBSOLETE (value & (0x80000000 >> PSW_F2)) ? ", f2" : "", */
/* OBSOLETE (value & (0x80000000 >> PSW_F3)) ? ", f3" : "", */
/* OBSOLETE (value & (0x80000000 >> PSW_S)) ? ", s" : "", */
/* OBSOLETE (value & (0x80000000 >> PSW_V)) ? ", v" : "", */
/* OBSOLETE (value & (0x80000000 >> PSW_VA)) ? ", va" : "", */
/* OBSOLETE (value & (0x80000000 >> PSW_C)) ? ", c" : ""); */
/* OBSOLETE */
/* OBSOLETE else if (ptr >= &CREG[0] && ptr <= &CREG[NR_CONTROL_REGISTERS]) */
/* OBSOLETE trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu", */
/* OBSOLETE "Set register cr%d = 0x%.8lx (%ld)", */
/* OBSOLETE ptr - &CREG[0], (long)value, (long)value); */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE /* Implement ALU tracing of 32-bit registers. */ */
/* OBSOLETE static void */
/* OBSOLETE trace_alu64 (SIM_DESC sd, */
/* OBSOLETE sim_cpu *cpu, */
/* OBSOLETE address_word cia, */
/* OBSOLETE unsigned64 *ptr) */
/* OBSOLETE { */
/* OBSOLETE unsigned64 value = *ptr; */
/* OBSOLETE */
/* OBSOLETE if (ptr >= &ACC[0] && ptr <= &ACC[NR_ACCUMULATORS]) */
/* OBSOLETE trace_one_insn (sd, cpu, cia, 1, "engine.c", __LINE__, "alu", */
/* OBSOLETE "Set register a%-2d = 0x%.8lx 0x%.8lx", */
/* OBSOLETE ptr - &ACC[0], */
/* OBSOLETE (unsigned long)(unsigned32)(value >> 32), */
/* OBSOLETE (unsigned long)(unsigned32)value); */
/* OBSOLETE */
/* OBSOLETE } */
/* OBSOLETE #endif */
/* OBSOLETE */
/* OBSOLETE /* Process all of the queued up writes in order now */ */
/* OBSOLETE void */
/* OBSOLETE unqueue_writes (SIM_DESC sd, */
/* OBSOLETE sim_cpu *cpu, */
/* OBSOLETE address_word cia) */
/* OBSOLETE { */
/* OBSOLETE int i, num; */
/* OBSOLETE int did_psw = 0; */
/* OBSOLETE unsigned32 *psw_addr = &PSW; */
/* OBSOLETE */
/* OBSOLETE num = WRITE32_NUM; */
/* OBSOLETE for (i = 0; i < num; i++) */
/* OBSOLETE { */
/* OBSOLETE unsigned32 mask = WRITE32_MASK (i); */
/* OBSOLETE unsigned32 *ptr = WRITE32_PTR (i); */
/* OBSOLETE unsigned32 value = (*ptr & ~mask) | (WRITE32_VALUE (i) & mask); */
/* OBSOLETE int j; */
/* OBSOLETE */
/* OBSOLETE if (ptr == psw_addr) */
/* OBSOLETE { */
/* OBSOLETE /* If MU instruction was not a MVTSYS, resolve PSW */
/* OBSOLETE contention in favour of IU. */ */
/* OBSOLETE if(! STATE_CPU (sd, 0)->mvtsys_left_p) */
/* OBSOLETE { */
/* OBSOLETE /* Detect contention in parallel writes to the same PSW flags. */
/* OBSOLETE The hardware allows the updates from IU to prevail over */
/* OBSOLETE those from MU. */ */
/* OBSOLETE */
/* OBSOLETE unsigned32 flag_bits = */
/* OBSOLETE BIT32 (PSW_F0) | BIT32 (PSW_F1) | */
/* OBSOLETE BIT32 (PSW_F2) | BIT32 (PSW_F3) | */
/* OBSOLETE BIT32 (PSW_S) | BIT32 (PSW_V) | */
/* OBSOLETE BIT32 (PSW_VA) | BIT32 (PSW_C); */
/* OBSOLETE unsigned32 my_flag_bits = mask & flag_bits; */
/* OBSOLETE */
/* OBSOLETE for (j = i + 1; j < num; j++) */
/* OBSOLETE if (WRITE32_PTR (j) == psw_addr && /* write to PSW */ */
/* OBSOLETE WRITE32_MASK (j) & my_flag_bits) /* some of the same flags */ */
/* OBSOLETE { */
/* OBSOLETE /* Recompute local mask & value, to suppress this */
/* OBSOLETE earlier write to the same flag bits. */ */
/* OBSOLETE */
/* OBSOLETE unsigned32 new_mask = mask & ~(WRITE32_MASK (j) & my_flag_bits); */
/* OBSOLETE */
/* OBSOLETE /* There is a special case for the VA (accumulated */
/* OBSOLETE overflow) flag, in that it is only included in the */
/* OBSOLETE second instruction's mask if the overflow */
/* OBSOLETE occurred. Yet the hardware still suppresses the */
/* OBSOLETE first instruction's update to VA. So we kludge */
/* OBSOLETE this by inferring PSW_V -> PSW_VA for the second */
/* OBSOLETE instruction. */ */
/* OBSOLETE */
/* OBSOLETE if (WRITE32_MASK (j) & BIT32 (PSW_V)) */
/* OBSOLETE { */
/* OBSOLETE new_mask &= ~BIT32 (PSW_VA); */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE value = (*ptr & ~new_mask) | (WRITE32_VALUE (i) & new_mask); */
/* OBSOLETE } */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE did_psw = 1; */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE *ptr = value; */
/* OBSOLETE */
/* OBSOLETE #if WITH_TRACE */
/* OBSOLETE if (TRACE_ALU_P (cpu)) */
/* OBSOLETE trace_alu32 (sd, cpu, cia, ptr); */
/* OBSOLETE #endif */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE num = WRITE64_NUM; */
/* OBSOLETE for (i = 0; i < num; i++) */
/* OBSOLETE { */
/* OBSOLETE unsigned64 *ptr = WRITE64_PTR (i); */
/* OBSOLETE *ptr = WRITE64_VALUE (i); */
/* OBSOLETE */
/* OBSOLETE #if WITH_TRACE */
/* OBSOLETE if (TRACE_ALU_P (cpu)) */
/* OBSOLETE trace_alu64 (sd, cpu, cia, ptr); */
/* OBSOLETE #endif */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE WRITE32_NUM = 0; */
/* OBSOLETE WRITE64_NUM = 0; */
/* OBSOLETE */
/* OBSOLETE if (DID_TRAP == 1) /* ordinary trap */ */
/* OBSOLETE { */
/* OBSOLETE bPSW = PSW; */
/* OBSOLETE PSW &= (BIT32 (PSW_DB) | BIT32 (PSW_SM)); */
/* OBSOLETE did_psw = 1; */
/* OBSOLETE } */
/* OBSOLETE else if (DID_TRAP == 2) /* debug trap */ */
/* OBSOLETE { */
/* OBSOLETE DPSW = PSW; */
/* OBSOLETE PSW &= BIT32 (PSW_DS); */
/* OBSOLETE PSW |= BIT32 (PSW_DS); */
/* OBSOLETE did_psw = 1; */
/* OBSOLETE } */
/* OBSOLETE DID_TRAP = 0; */
/* OBSOLETE */
/* OBSOLETE if (did_psw) */
/* OBSOLETE do_stack_swap (sd); */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE /* SIMULATE INSTRUCTIONS, various different ways of achieving the same */
/* OBSOLETE thing */ */
/* OBSOLETE */
/* OBSOLETE static address_word */
/* OBSOLETE do_long (SIM_DESC sd, */
/* OBSOLETE l_instruction_word instruction, */
/* OBSOLETE address_word cia) */
/* OBSOLETE { */
/* OBSOLETE address_word nia = l_idecode_issue(sd, */
/* OBSOLETE instruction, */
/* OBSOLETE cia); */
/* OBSOLETE */
/* OBSOLETE unqueue_writes (sd, STATE_CPU (sd, 0), cia); */
/* OBSOLETE return nia; */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE static address_word */
/* OBSOLETE do_2_short (SIM_DESC sd, */
/* OBSOLETE s_instruction_word insn1, */
/* OBSOLETE s_instruction_word insn2, */
/* OBSOLETE cpu_units unit, */
/* OBSOLETE address_word cia) */
/* OBSOLETE { */
/* OBSOLETE address_word nia; */
/* OBSOLETE */
/* OBSOLETE /* run the first instruction */ */
/* OBSOLETE STATE_CPU (sd, 0)->unit = unit; */
/* OBSOLETE STATE_CPU (sd, 0)->left_kills_right_p = 0; */
/* OBSOLETE STATE_CPU (sd, 0)->mvtsys_left_p = 0; */
/* OBSOLETE nia = s_idecode_issue(sd, */
/* OBSOLETE insn1, */
/* OBSOLETE cia); */
/* OBSOLETE */
/* OBSOLETE unqueue_writes (sd, STATE_CPU (sd, 0), cia); */
/* OBSOLETE */
/* OBSOLETE /* Only do the second instruction if the PC has not changed */ */
/* OBSOLETE if ((nia == INVALID_INSTRUCTION_ADDRESS) && */
/* OBSOLETE (! STATE_CPU (sd, 0)->left_kills_right_p)) { */
/* OBSOLETE STATE_CPU (sd, 0)->unit = any_unit; */
/* OBSOLETE nia = s_idecode_issue (sd, */
/* OBSOLETE insn2, */
/* OBSOLETE cia); */
/* OBSOLETE */
/* OBSOLETE unqueue_writes (sd, STATE_CPU (sd, 0), cia); */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE STATE_CPU (sd, 0)->left_kills_right_p = 0; */
/* OBSOLETE STATE_CPU (sd, 0)->mvtsys_left_p = 0; */
/* OBSOLETE return nia; */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE static address_word */
/* OBSOLETE do_parallel (SIM_DESC sd, */
/* OBSOLETE s_instruction_word left_insn, */
/* OBSOLETE s_instruction_word right_insn, */
/* OBSOLETE address_word cia) */
/* OBSOLETE { */
/* OBSOLETE address_word nia_left; */
/* OBSOLETE address_word nia_right; */
/* OBSOLETE address_word nia; */
/* OBSOLETE */
/* OBSOLETE /* run the first instruction */ */
/* OBSOLETE STATE_CPU (sd, 0)->unit = memory_unit; */
/* OBSOLETE STATE_CPU (sd, 0)->left_kills_right_p = 0; */
/* OBSOLETE STATE_CPU (sd, 0)->mvtsys_left_p = 0; */
/* OBSOLETE nia_left = s_idecode_issue(sd, */
/* OBSOLETE left_insn, */
/* OBSOLETE cia); */
/* OBSOLETE */
/* OBSOLETE /* run the second instruction */ */
/* OBSOLETE STATE_CPU (sd, 0)->unit = integer_unit; */
/* OBSOLETE nia_right = s_idecode_issue(sd, */
/* OBSOLETE right_insn, */
/* OBSOLETE cia); */
/* OBSOLETE */
/* OBSOLETE /* merge the PC's */ */
/* OBSOLETE if (nia_left == INVALID_INSTRUCTION_ADDRESS) { */
/* OBSOLETE if (nia_right == INVALID_INSTRUCTION_ADDRESS) */
/* OBSOLETE nia = INVALID_INSTRUCTION_ADDRESS; */
/* OBSOLETE else */
/* OBSOLETE nia = nia_right; */
/* OBSOLETE } */
/* OBSOLETE else { */
/* OBSOLETE if (nia_right == INVALID_INSTRUCTION_ADDRESS) */
/* OBSOLETE nia = nia_left; */
/* OBSOLETE else { */
/* OBSOLETE sim_engine_abort (sd, STATE_CPU (sd, 0), cia, "parallel jumps"); */
/* OBSOLETE nia = INVALID_INSTRUCTION_ADDRESS; */
/* OBSOLETE } */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE unqueue_writes (sd, STATE_CPU (sd, 0), cia); */
/* OBSOLETE return nia; */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE typedef enum { */
/* OBSOLETE p_insn = 0, */
/* OBSOLETE long_insn = 3, */
/* OBSOLETE l_r_insn = 1, */
/* OBSOLETE r_l_insn = 2, */
/* OBSOLETE } instruction_types; */
/* OBSOLETE */
/* OBSOLETE STATIC_INLINE instruction_types */
/* OBSOLETE instruction_type(l_instruction_word insn) */
/* OBSOLETE { */
/* OBSOLETE int fm0 = MASKED64(insn, 0, 0) != 0; */
/* OBSOLETE int fm1 = MASKED64(insn, 32, 32) != 0; */
/* OBSOLETE return ((fm0 << 1) | fm1); */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE void */
/* OBSOLETE sim_engine_run (SIM_DESC sd, */
/* OBSOLETE int last_cpu_nr, */
/* OBSOLETE int nr_cpus, */
/* OBSOLETE int siggnal) */
/* OBSOLETE { */
/* OBSOLETE while (1) */
/* OBSOLETE { */
/* OBSOLETE address_word cia = PC; */
/* OBSOLETE address_word nia; */
/* OBSOLETE l_instruction_word insn = IMEM(cia); */
/* OBSOLETE int rp_was_set; */
/* OBSOLETE int rpt_c_was_nonzero; */
/* OBSOLETE */
/* OBSOLETE /* Before executing the instruction, we need to test whether or */
/* OBSOLETE not RPT_C is greater than zero, and save that state for use */
/* OBSOLETE after executing the instruction. In particular, we need to */
/* OBSOLETE not care whether the instruction changes RPT_C itself. */ */
/* OBSOLETE */
/* OBSOLETE rpt_c_was_nonzero = (RPT_C > 0); */
/* OBSOLETE */
/* OBSOLETE /* Before executing the instruction, we need to check to see if */
/* OBSOLETE we have to decrement RPT_C, the repeat count register. Do this */
/* OBSOLETE if PC == RPT_E, but only if we are in an active repeat block. */ */
/* OBSOLETE */
/* OBSOLETE if (PC == RPT_E && */
/* OBSOLETE (RPT_C > 0 || PSW_VAL (PSW_RP) != 0)) */
/* OBSOLETE { */
/* OBSOLETE RPT_C --; */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE /* Now execute the instruction at PC */ */
/* OBSOLETE */
/* OBSOLETE switch (instruction_type (insn)) */
/* OBSOLETE { */
/* OBSOLETE case long_insn: */
/* OBSOLETE nia = do_long (sd, insn, cia); */
/* OBSOLETE break; */
/* OBSOLETE case r_l_insn: */
/* OBSOLETE /* L <- R */ */
/* OBSOLETE nia = do_2_short (sd, insn, insn >> 32, integer_unit, cia); */
/* OBSOLETE break; */
/* OBSOLETE case l_r_insn: */
/* OBSOLETE /* L -> R */ */
/* OBSOLETE nia = do_2_short (sd, insn >> 32, insn, memory_unit, cia); */
/* OBSOLETE break; */
/* OBSOLETE case p_insn: */
/* OBSOLETE nia = do_parallel (sd, insn >> 32, insn, cia); */
/* OBSOLETE break; */
/* OBSOLETE default: */
/* OBSOLETE sim_engine_abort (sd, STATE_CPU (sd, 0), cia, */
/* OBSOLETE "internal error - engine_run_until_stop - bad switch"); */
/* OBSOLETE nia = -1; */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE if (TRACE_ACTION) */
/* OBSOLETE { */
/* OBSOLETE if (TRACE_ACTION & TRACE_ACTION_CALL) */
/* OBSOLETE call_occurred (sd, STATE_CPU (sd, 0), cia, nia); */
/* OBSOLETE */
/* OBSOLETE if (TRACE_ACTION & TRACE_ACTION_RETURN) */
/* OBSOLETE return_occurred (sd, STATE_CPU (sd, 0), cia, nia); */
/* OBSOLETE */
/* OBSOLETE TRACE_ACTION = 0; */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE /* Check now to see if we need to reset the RP bit in the PSW. */
/* OBSOLETE There are three conditions for this, the RP bit is already */
/* OBSOLETE set (just a speed optimization), the instruction we just */
/* OBSOLETE executed is the last instruction in the loop, and the repeat */
/* OBSOLETE count is currently zero. */ */
/* OBSOLETE */
/* OBSOLETE rp_was_set = PSW_VAL (PSW_RP); */
/* OBSOLETE if (rp_was_set && (PC == RPT_E) && RPT_C == 0) */
/* OBSOLETE { */
/* OBSOLETE PSW_SET (PSW_RP, 0); */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE /* Now update the PC. If we just executed a jump instruction, */
/* OBSOLETE that takes precedence over everything else. Next comes */
/* OBSOLETE branching back to RPT_S as a result of a loop. Finally, the */
/* OBSOLETE default is to simply advance to the next inline */
/* OBSOLETE instruction. */ */
/* OBSOLETE */
/* OBSOLETE if (nia != INVALID_INSTRUCTION_ADDRESS) */
/* OBSOLETE { */
/* OBSOLETE PC = nia; */
/* OBSOLETE } */
/* OBSOLETE else if (rp_was_set && rpt_c_was_nonzero && (PC == RPT_E)) */
/* OBSOLETE { */
/* OBSOLETE PC = RPT_S; */
/* OBSOLETE } */
/* OBSOLETE else */
/* OBSOLETE { */
/* OBSOLETE PC = cia + 8; */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE /* Check for DDBT (debugger debug trap) condition. Do this after */
/* OBSOLETE the repeat block checks so the excursion to the trap handler does */
/* OBSOLETE not alter looping state. */ */
/* OBSOLETE */
/* OBSOLETE if (cia == IBA && PSW_VAL (PSW_DB)) */
/* OBSOLETE { */
/* OBSOLETE DPC = PC; */
/* OBSOLETE PSW_SET (PSW_EA, 1); */
/* OBSOLETE DPSW = PSW; */
/* OBSOLETE /* clear all bits in PSW except SM */ */
/* OBSOLETE PSW &= BIT32 (PSW_SM); */
/* OBSOLETE /* add DS bit */ */
/* OBSOLETE PSW |= BIT32 (PSW_DS); */
/* OBSOLETE /* dispatch to DDBT handler */ */
/* OBSOLETE PC = 0xfffff128; /* debugger_debug_trap_address */ */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE /* process any events */ */
/* OBSOLETE /* FIXME - should L->R or L<-R insns count as two cycles? */ */
/* OBSOLETE if (sim_events_tick (sd)) */
/* OBSOLETE { */
/* OBSOLETE sim_events_process (sd); */
/* OBSOLETE } */
/* OBSOLETE } */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE /* d30v external interrupt handler. */
/* OBSOLETE */
/* OBSOLETE Note: This should be replaced by a proper interrupt delivery */
/* OBSOLETE mechanism. This interrupt mechanism discards later interrupts if */
/* OBSOLETE an earlier interrupt hasn't been delivered. */
/* OBSOLETE */
/* OBSOLETE Note: This interrupt mechanism does not reset its self when the */
/* OBSOLETE simulator is re-opened. */ */
/* OBSOLETE */
/* OBSOLETE void */
/* OBSOLETE d30v_interrupt_event (SIM_DESC sd, */
/* OBSOLETE void *data) */
/* OBSOLETE { */
/* OBSOLETE if (PSW_VAL (PSW_IE)) */
/* OBSOLETE /* interrupts not masked */ */
/* OBSOLETE { */
/* OBSOLETE /* scrub any pending interrupt */ */
/* OBSOLETE if (sd->pending_interrupt != NULL) */
/* OBSOLETE sim_events_deschedule (sd, sd->pending_interrupt); */
/* OBSOLETE /* deliver */ */
/* OBSOLETE bPSW = PSW; */
/* OBSOLETE bPC = PC; */
/* OBSOLETE PSW = 0; */
/* OBSOLETE PC = 0xfffff138; /* external interrupt */ */
/* OBSOLETE do_stack_swap (sd); */
/* OBSOLETE } */
/* OBSOLETE else if (sd->pending_interrupt == NULL) */
/* OBSOLETE /* interrupts masked and no interrupt pending */ */
/* OBSOLETE { */
/* OBSOLETE sd->pending_interrupt = sim_events_schedule (sd, 1, */
/* OBSOLETE d30v_interrupt_event, */
/* OBSOLETE data); */
/* OBSOLETE } */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE #endif */

160
sim/d30v/ic-d30v
View File

@ -1,80 +1,80 @@
# Instruction cache rules
#
# This file is part of the program psim.
#
# Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
#
compute:RA:RA::
compute:RA:Ra:signed32 *:(&GPR[RA])
compute:RA:RaH:signed16 *:AH2_4(Ra)
compute:RA:RaL:signed16 *:AL2_4(Ra)
compute:RA:val_Ra:signed32:(RA == 0 ? 0 : GPR[RA])
#
compute:RB:RB::
compute:RB:Rb:signed32:(RB == 0 ? 0 : GPR[RB])
compute:RB:RbU:unsigned32:(RB == 0 ? 0 : GPR[RB])
compute:RB:RbH:signed16:VH2_4(Rb)
compute:RB:RbL:signed16:VL2_4(Rb)
compute:RB:RbHU:unsigned16:VH2_4(Rb)
compute:RB:RbLU:unsigned16:VL2_4(Rb)
#
compute:RC:RC::
compute:RC:Rc:signed32:(RC == 0 ? 0 : GPR[RC])
compute:RC:RcU:unsigned32:(RC == 0 ? 0 : GPR[RC])
compute:RC:RcH:signed16:VH2_4(Rc)
compute:RC:RcL:signed16:VL2_4(Rc)
#
#
compute:IMM_6S:IMM_6S::
compute:IMM_6S:imm:signed32:SEXT32(IMM_6S, 32 - 6)
# NB - for short imm[HL] are the same value
compute:IMM_6S:immHL:signed32:((imm << 16) | MASKED32(imm, 16, 31))
compute:IMM_6S:immH:signed32:imm
compute:IMM_6S:immL:signed32:imm
compute:IMM_6S:imm_6:signed32:IMM_6S
compute:IMM_6S:imm_5:signed32:LSMASKED32(IMM_6S, 4, 0)
compute:IMM_6S:imm_6u:unsigned32:(IMM_6S & 0x3f)
#
compute:RC:pcdisp:signed32:(Rc & ~0x7)
compute:RC:pcaddr:signed32:pcdisp
#
compute:IMM_18S:IMM_18S::
compute:IMM_18S:pcdisp:signed32:(SEXT32(IMM_18S, 32 - 18) << 3)
compute:IMM_18S:pcaddr:signed32:pcdisp
compute:IMM_12S:IMM_12S::
compute:IMM_12S:pcdisp:signed32:(SEXT32(IMM_12S, 32 - 12) << 3)
compute:IMM_12S:pcaddr:signed32:pcdisp
#
compute:IMM_8L:IMM_8L::
compute:IMM_18L:IMM_18L::
compute:IMM_6L:IMM_6L::
compute:IMM_6L:imm:signed32:((((IMM_6L << 8) | IMM_8L) << 18) | IMM_18L)
compute:IMM_6L:immHL:signed32:imm
compute:IMM_6L:immH:signed32:EXTRACTED32(imm, 0, 15)
compute:IMM_6L:immL:signed32:EXTRACTED32(imm, 16, 31)
compute:IMM_6L:pcdisp:signed32:(imm & ~0x7)
compute:IMM_6L:pcaddr:signed32:pcdisp
#
#
compute:SRC_6:SRC_6::
compute:SRC_6:src:unsigned32:(XX == 2 ? SEXT32(SRC_6, 32 - 6) : GPR[SRC_6])
#
#
compute:AA:AA::
compute:AA:Aa:unsigned64*:((CPU)->regs.accumulator + AA)
compute:AB:AB::
compute:AB:Ab:unsigned64*:((CPU)->regs.accumulator + AB)
# OBSOLETE # Instruction cache rules
# OBSOLETE #
# OBSOLETE # This file is part of the program psim.
# OBSOLETE #
# OBSOLETE # Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
# OBSOLETE #
# OBSOLETE # This program is free software; you can redistribute it and/or modify
# OBSOLETE # it under the terms of the GNU General Public License as published by
# OBSOLETE # the Free Software Foundation; either version 2 of the License, or
# OBSOLETE # (at your option) any later version.
# OBSOLETE #
# OBSOLETE # This program is distributed in the hope that it will be useful,
# OBSOLETE # but WITHOUT ANY WARRANTY; without even the implied warranty of
# OBSOLETE # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# OBSOLETE # GNU General Public License for more details.
# OBSOLETE #
# OBSOLETE # You should have received a copy of the GNU General Public License
# OBSOLETE # along with this program; if not, write to the Free Software
# OBSOLETE # Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
# OBSOLETE #
# OBSOLETE compute:RA:RA::
# OBSOLETE compute:RA:Ra:signed32 *:(&GPR[RA])
# OBSOLETE compute:RA:RaH:signed16 *:AH2_4(Ra)
# OBSOLETE compute:RA:RaL:signed16 *:AL2_4(Ra)
# OBSOLETE compute:RA:val_Ra:signed32:(RA == 0 ? 0 : GPR[RA])
# OBSOLETE #
# OBSOLETE compute:RB:RB::
# OBSOLETE compute:RB:Rb:signed32:(RB == 0 ? 0 : GPR[RB])
# OBSOLETE compute:RB:RbU:unsigned32:(RB == 0 ? 0 : GPR[RB])
# OBSOLETE compute:RB:RbH:signed16:VH2_4(Rb)
# OBSOLETE compute:RB:RbL:signed16:VL2_4(Rb)
# OBSOLETE compute:RB:RbHU:unsigned16:VH2_4(Rb)
# OBSOLETE compute:RB:RbLU:unsigned16:VL2_4(Rb)
# OBSOLETE #
# OBSOLETE compute:RC:RC::
# OBSOLETE compute:RC:Rc:signed32:(RC == 0 ? 0 : GPR[RC])
# OBSOLETE compute:RC:RcU:unsigned32:(RC == 0 ? 0 : GPR[RC])
# OBSOLETE compute:RC:RcH:signed16:VH2_4(Rc)
# OBSOLETE compute:RC:RcL:signed16:VL2_4(Rc)
# OBSOLETE #
# OBSOLETE #
# OBSOLETE compute:IMM_6S:IMM_6S::
# OBSOLETE compute:IMM_6S:imm:signed32:SEXT32(IMM_6S, 32 - 6)
# OBSOLETE # NB - for short imm[HL] are the same value
# OBSOLETE compute:IMM_6S:immHL:signed32:((imm << 16) | MASKED32(imm, 16, 31))
# OBSOLETE compute:IMM_6S:immH:signed32:imm
# OBSOLETE compute:IMM_6S:immL:signed32:imm
# OBSOLETE compute:IMM_6S:imm_6:signed32:IMM_6S
# OBSOLETE compute:IMM_6S:imm_5:signed32:LSMASKED32(IMM_6S, 4, 0)
# OBSOLETE compute:IMM_6S:imm_6u:unsigned32:(IMM_6S & 0x3f)
# OBSOLETE #
# OBSOLETE compute:RC:pcdisp:signed32:(Rc & ~0x7)
# OBSOLETE compute:RC:pcaddr:signed32:pcdisp
# OBSOLETE #
# OBSOLETE compute:IMM_18S:IMM_18S::
# OBSOLETE compute:IMM_18S:pcdisp:signed32:(SEXT32(IMM_18S, 32 - 18) << 3)
# OBSOLETE compute:IMM_18S:pcaddr:signed32:pcdisp
# OBSOLETE compute:IMM_12S:IMM_12S::
# OBSOLETE compute:IMM_12S:pcdisp:signed32:(SEXT32(IMM_12S, 32 - 12) << 3)
# OBSOLETE compute:IMM_12S:pcaddr:signed32:pcdisp
# OBSOLETE #
# OBSOLETE compute:IMM_8L:IMM_8L::
# OBSOLETE compute:IMM_18L:IMM_18L::
# OBSOLETE compute:IMM_6L:IMM_6L::
# OBSOLETE compute:IMM_6L:imm:signed32:((((IMM_6L << 8) | IMM_8L) << 18) | IMM_18L)
# OBSOLETE compute:IMM_6L:immHL:signed32:imm
# OBSOLETE compute:IMM_6L:immH:signed32:EXTRACTED32(imm, 0, 15)
# OBSOLETE compute:IMM_6L:immL:signed32:EXTRACTED32(imm, 16, 31)
# OBSOLETE compute:IMM_6L:pcdisp:signed32:(imm & ~0x7)
# OBSOLETE compute:IMM_6L:pcaddr:signed32:pcdisp
# OBSOLETE #
# OBSOLETE #
# OBSOLETE compute:SRC_6:SRC_6::
# OBSOLETE compute:SRC_6:src:unsigned32:(XX == 2 ? SEXT32(SRC_6, 32 - 6) : GPR[SRC_6])
# OBSOLETE #
# OBSOLETE #
# OBSOLETE compute:AA:AA::
# OBSOLETE compute:AA:Aa:unsigned64*:((CPU)->regs.accumulator + AA)
# OBSOLETE compute:AB:AB::
# OBSOLETE compute:AB:Ab:unsigned64*:((CPU)->regs.accumulator + AB)

728
sim/d30v/sim-calls.c
View File

@ -1,364 +1,364 @@
/* This file is part of the program psim.
Copyright (C) 1994-1996, Andrew Cagney <cagney@highland.com.au>
Copyright (C) 1997, Free Software Foundation
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <stdarg.h>
#include <ctype.h>
#include "sim-main.h"
#include "sim-options.h"
#include "bfd.h"
#include "sim-utils.h"
#ifdef HAVE_STDLIB_H
#include <stdlib.h>
#endif
static unsigned long extmem_size = 1024*1024*8; /* 8 meg is the maximum listed in the arch. manual */
static const char * get_insn_name (sim_cpu *, int);
#define SIM_ADDR unsigned
#define OPTION_TRACE_CALL 200
#define OPTION_TRACE_TRAPDUMP 201
#define OPTION_EXTMEM_SIZE 202
static SIM_RC
d30v_option_handler (SIM_DESC sd,
sim_cpu *cpu,
int opt,
char *arg,
int command_p)
{
char *suffix;
switch (opt)
{
default:
break;
case OPTION_TRACE_CALL:
if (arg == NULL || strcmp (arg, "yes") == 0 || strcmp (arg, "on") == 0)
TRACE_CALL_P = 1;
else if (strcmp (arg, "no") == 0 || strcmp (arg, "off") == 0)
TRACE_CALL_P = 0;
else
{
sim_io_eprintf (sd, "Unreconized --trace-call option `%s'\n", arg);
return SIM_RC_FAIL;
}
return SIM_RC_OK;
case OPTION_TRACE_TRAPDUMP:
if (arg == NULL || strcmp (arg, "yes") == 0 || strcmp (arg, "on") == 0)
TRACE_TRAP_P = 1;
else if (strcmp (arg, "no") == 0 || strcmp (arg, "off") == 0)
TRACE_TRAP_P = 0;
else
{
sim_io_eprintf (sd, "Unreconized --trace-call option `%s'\n", arg);
return SIM_RC_FAIL;
}
return SIM_RC_OK;
case OPTION_EXTMEM_SIZE:
if (arg == NULL || !isdigit (*arg))
{
sim_io_eprintf (sd, "Invalid memory size `%s'", arg);
return SIM_RC_FAIL;
}
suffix = arg;
extmem_size = strtol (arg, &suffix, 0);
if (*suffix == 'm' || *suffix == 'M')
extmem_size <<= 20;
else if (*suffix == 'k' || *suffix == 'K')
extmem_size <<= 10;
sim_do_commandf (sd, "memory delete 0x80000000");
sim_do_commandf (sd, "memory region 0x80000000,0x%lx", extmem_size);
return SIM_RC_OK;
}
sim_io_eprintf (sd, "Unknown option (%d)\n", opt);
return SIM_RC_FAIL;
}
static const OPTION d30v_options[] =
{
{ {"trace-call", optional_argument, NULL, OPTION_TRACE_CALL},
'\0', "on|off", "Enable tracing of calls and returns, checking saved registers",
d30v_option_handler },
{ {"trace-trapdump", optional_argument, NULL, OPTION_TRACE_TRAPDUMP},
'\0', "on|off",
#if TRAPDUMP
"Traps 0..30 dump out all of the registers (defaults on)",
#else
"Traps 0..30 dump out all of the registers",
#endif
d30v_option_handler },
{ {"extmem-size", required_argument, NULL, OPTION_EXTMEM_SIZE},
'\0', "size", "Change size of external memory, default 8 meg",
d30v_option_handler },
{ {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
};
/* Return name of an insn, used by insn profiling. */
static const char *
get_insn_name (sim_cpu *cpu, int i)
{
return itable[i].name;
}
/* Structures used by the simulator, for gdb just have static structures */
SIM_DESC
sim_open (SIM_OPEN_KIND kind,
host_callback *callback,
struct _bfd *abfd,
char **argv)
{
SIM_DESC sd = sim_state_alloc (kind, callback);
/* FIXME: watchpoints code shouldn't need this */
STATE_WATCHPOINTS (sd)->pc = &(PC);
STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
STATE_WATCHPOINTS (sd)->interrupt_handler = d30v_interrupt_event;
/* Initialize the mechanism for doing insn profiling. */
CPU_INSN_NAME (STATE_CPU (sd, 0)) = get_insn_name;
CPU_MAX_INSNS (STATE_CPU (sd, 0)) = nr_itable_entries;
#ifdef TRAPDUMP
TRACE_TRAP_P = TRAPDUMP;
#endif
if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
return 0;
sim_add_option_table (sd, NULL, d30v_options);
/* Memory and EEPROM */
/* internal instruction RAM - fixed */
sim_do_commandf (sd, "memory region 0,0x10000");
/* internal data RAM - fixed */
sim_do_commandf (sd, "memory region 0x20000000,0x8000");
/* control register dummy area */
sim_do_commandf (sd, "memory region 0x40000000,0x10000");
/* external RAM */
sim_do_commandf (sd, "memory region 0x80000000,0x%lx", extmem_size);
/* EIT RAM */
sim_do_commandf (sd, "memory region 0xfffff000,0x1000");
/* getopt will print the error message so we just have to exit if this fails.
FIXME: Hmmm... in the case of gdb we need getopt to call
print_filtered. */
if (sim_parse_args (sd, argv) != SIM_RC_OK)
{
/* Uninstall the modules to avoid memory leaks,
file descriptor leaks, etc. */
sim_module_uninstall (sd);
return 0;
}
/* check for/establish the a reference program image */
if (sim_analyze_program (sd,
(STATE_PROG_ARGV (sd) != NULL
? *STATE_PROG_ARGV (sd)
: NULL),
abfd) != SIM_RC_OK)
{
sim_module_uninstall (sd);
return 0;
}
/* establish any remaining configuration options */
if (sim_config (sd) != SIM_RC_OK)
{
sim_module_uninstall (sd);
return 0;
}
if (sim_post_argv_init (sd) != SIM_RC_OK)
{
/* Uninstall the modules to avoid memory leaks,
file descriptor leaks, etc. */
sim_module_uninstall (sd);
return 0;
}
return sd;
}
void
sim_close (SIM_DESC sd, int quitting)
{
/* Uninstall the modules to avoid memory leaks,
file descriptor leaks, etc. */
sim_module_uninstall (sd);
}
SIM_RC
sim_create_inferior (SIM_DESC sd,
struct _bfd *abfd,
char **argv,
char **envp)
{
/* clear all registers */
memset (&STATE_CPU (sd, 0)->regs, 0, sizeof (STATE_CPU (sd, 0)->regs));
EIT_VB = EIT_VB_DEFAULT;
STATE_CPU (sd, 0)->unit = any_unit;
sim_module_init (sd);
if (abfd != NULL)
PC = bfd_get_start_address (abfd);
else
PC = 0xfffff000; /* reset value */
return SIM_RC_OK;
}
void
sim_do_command (SIM_DESC sd, char *cmd)
{
if (sim_args_command (sd, cmd) != SIM_RC_OK)
sim_io_printf (sd, "Unknown command `%s'\n", cmd);
}
/* The following register definitions were ripped off from
gdb/config/tm-d30v.h. If any of those defs changes, this table needs to
be updated. */
#define NUM_REGS 86
#define R0_REGNUM 0
#define FP_REGNUM 11
#define LR_REGNUM 62
#define SP_REGNUM 63
#define SPI_REGNUM 64 /* Interrupt stack pointer */
#define SPU_REGNUM 65 /* User stack pointer */
#define CREGS_START 66
#define PSW_REGNUM (CREGS_START + 0) /* psw, bpsw, or dpsw??? */
#define PSW_SM 0x80000000 /* Stack mode: 0 == interrupt (SPI),
1 == user (SPU) */
#define BPSW_REGNUM (CREGS_START + 1) /* Backup PSW (on interrupt) */
#define PC_REGNUM (CREGS_START + 2) /* pc, bpc, or dpc??? */
#define BPC_REGNUM (CREGS_START + 3) /* Backup PC (on interrupt) */
#define DPSW_REGNUM (CREGS_START + 4) /* Backup PSW (on debug trap) */
#define DPC_REGNUM (CREGS_START + 5) /* Backup PC (on debug trap) */
#define RPT_C_REGNUM (CREGS_START + 7) /* Loop count */
#define RPT_S_REGNUM (CREGS_START + 8) /* Loop start address*/
#define RPT_E_REGNUM (CREGS_START + 9) /* Loop end address */
#define MOD_S_REGNUM (CREGS_START + 10)
#define MOD_E_REGNUM (CREGS_START + 11)
#define IBA_REGNUM (CREGS_START + 14) /* Instruction break address */
#define EIT_VB_REGNUM (CREGS_START + 15) /* Vector base address */
#define INT_S_REGNUM (CREGS_START + 16) /* Interrupt status */
#define INT_M_REGNUM (CREGS_START + 17) /* Interrupt mask */
#define A0_REGNUM 84
#define A1_REGNUM 85
int
sim_fetch_register (sd, regno, buf, length)
SIM_DESC sd;
int regno;
unsigned char *buf;
int length;
{
if (regno < A0_REGNUM)
{
unsigned32 reg;
if (regno <= R0_REGNUM + 63)
reg = sd->cpu[0].regs.general_purpose[regno];
else if (regno <= SPU_REGNUM)
reg = sd->cpu[0].regs.sp[regno - SPI_REGNUM];
else
reg = sd->cpu[0].regs.control[regno - CREGS_START];
buf[0] = reg >> 24;
buf[1] = reg >> 16;
buf[2] = reg >> 8;
buf[3] = reg;
}
else if (regno < NUM_REGS)
{
unsigned32 reg;
reg = sd->cpu[0].regs.accumulator[regno - A0_REGNUM] >> 32;
buf[0] = reg >> 24;
buf[1] = reg >> 16;
buf[2] = reg >> 8;
buf[3] = reg;
reg = sd->cpu[0].regs.accumulator[regno - A0_REGNUM];
buf[4] = reg >> 24;
buf[5] = reg >> 16;
buf[6] = reg >> 8;
buf[7] = reg;
}
else
abort ();
return -1;
}
int
sim_store_register (sd, regno, buf, length)
SIM_DESC sd;
int regno;
unsigned char *buf;
int length;
{
if (regno < A0_REGNUM)
{
unsigned32 reg;
reg = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
if (regno <= R0_REGNUM + 63)
sd->cpu[0].regs.general_purpose[regno] = reg;
else if (regno <= SPU_REGNUM)
sd->cpu[0].regs.sp[regno - SPI_REGNUM] = reg;
else
sd->cpu[0].regs.control[regno - CREGS_START] = reg;
}
else if (regno < NUM_REGS)
{
unsigned32 reg;
reg = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
sd->cpu[0].regs.accumulator[regno - A0_REGNUM] = (unsigned64)reg << 32;
reg = (buf[4] << 24) | (buf[5] << 16) | (buf[6] << 8) | buf[7];
sd->cpu[0].regs.accumulator[regno - A0_REGNUM] |= reg;
}
else
abort ();
return -1;
}
/* OBSOLETE /* This file is part of the program psim. */
/* OBSOLETE */
/* OBSOLETE Copyright (C) 1994-1996, Andrew Cagney <cagney@highland.com.au> */
/* OBSOLETE Copyright (C) 1997, Free Software Foundation */
/* OBSOLETE */
/* OBSOLETE This program is free software; you can redistribute it and/or modify */
/* OBSOLETE it under the terms of the GNU General Public License as published by */
/* OBSOLETE the Free Software Foundation; either version 2 of the License, or */
/* OBSOLETE (at your option) any later version. */
/* OBSOLETE */
/* OBSOLETE This program is distributed in the hope that it will be useful, */
/* OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of */
/* OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
/* OBSOLETE GNU General Public License for more details. */
/* OBSOLETE */
/* OBSOLETE You should have received a copy of the GNU General Public License */
/* OBSOLETE along with this program; if not, write to the Free Software */
/* OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
/* OBSOLETE */
/* OBSOLETE */ */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE #include <stdarg.h> */
/* OBSOLETE #include <ctype.h> */
/* OBSOLETE */
/* OBSOLETE #include "sim-main.h" */
/* OBSOLETE #include "sim-options.h" */
/* OBSOLETE */
/* OBSOLETE #include "bfd.h" */
/* OBSOLETE #include "sim-utils.h" */
/* OBSOLETE */
/* OBSOLETE #ifdef HAVE_STDLIB_H */
/* OBSOLETE #include <stdlib.h> */
/* OBSOLETE #endif */
/* OBSOLETE */
/* OBSOLETE static unsigned long extmem_size = 1024*1024*8; /* 8 meg is the maximum listed in the arch. manual */ */
/* OBSOLETE */
/* OBSOLETE static const char * get_insn_name (sim_cpu *, int); */
/* OBSOLETE */
/* OBSOLETE #define SIM_ADDR unsigned */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE #define OPTION_TRACE_CALL 200 */
/* OBSOLETE #define OPTION_TRACE_TRAPDUMP 201 */
/* OBSOLETE #define OPTION_EXTMEM_SIZE 202 */
/* OBSOLETE */
/* OBSOLETE static SIM_RC */
/* OBSOLETE d30v_option_handler (SIM_DESC sd, */
/* OBSOLETE sim_cpu *cpu, */
/* OBSOLETE int opt, */
/* OBSOLETE char *arg, */
/* OBSOLETE int command_p) */
/* OBSOLETE { */
/* OBSOLETE char *suffix; */
/* OBSOLETE */
/* OBSOLETE switch (opt) */
/* OBSOLETE { */
/* OBSOLETE default: */
/* OBSOLETE break; */
/* OBSOLETE */
/* OBSOLETE case OPTION_TRACE_CALL: */
/* OBSOLETE if (arg == NULL || strcmp (arg, "yes") == 0 || strcmp (arg, "on") == 0) */
/* OBSOLETE TRACE_CALL_P = 1; */
/* OBSOLETE else if (strcmp (arg, "no") == 0 || strcmp (arg, "off") == 0) */
/* OBSOLETE TRACE_CALL_P = 0; */
/* OBSOLETE else */
/* OBSOLETE { */
/* OBSOLETE sim_io_eprintf (sd, "Unreconized --trace-call option `%s'\n", arg); */
/* OBSOLETE return SIM_RC_FAIL; */
/* OBSOLETE } */
/* OBSOLETE return SIM_RC_OK; */
/* OBSOLETE */
/* OBSOLETE case OPTION_TRACE_TRAPDUMP: */
/* OBSOLETE if (arg == NULL || strcmp (arg, "yes") == 0 || strcmp (arg, "on") == 0) */
/* OBSOLETE TRACE_TRAP_P = 1; */
/* OBSOLETE else if (strcmp (arg, "no") == 0 || strcmp (arg, "off") == 0) */
/* OBSOLETE TRACE_TRAP_P = 0; */
/* OBSOLETE else */
/* OBSOLETE { */
/* OBSOLETE sim_io_eprintf (sd, "Unreconized --trace-call option `%s'\n", arg); */
/* OBSOLETE return SIM_RC_FAIL; */
/* OBSOLETE } */
/* OBSOLETE return SIM_RC_OK; */
/* OBSOLETE */
/* OBSOLETE case OPTION_EXTMEM_SIZE: */
/* OBSOLETE if (arg == NULL || !isdigit (*arg)) */
/* OBSOLETE { */
/* OBSOLETE sim_io_eprintf (sd, "Invalid memory size `%s'", arg); */
/* OBSOLETE return SIM_RC_FAIL; */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE suffix = arg; */
/* OBSOLETE extmem_size = strtol (arg, &suffix, 0); */
/* OBSOLETE if (*suffix == 'm' || *suffix == 'M') */
/* OBSOLETE extmem_size <<= 20; */
/* OBSOLETE else if (*suffix == 'k' || *suffix == 'K') */
/* OBSOLETE extmem_size <<= 10; */
/* OBSOLETE sim_do_commandf (sd, "memory delete 0x80000000"); */
/* OBSOLETE sim_do_commandf (sd, "memory region 0x80000000,0x%lx", extmem_size); */
/* OBSOLETE */
/* OBSOLETE return SIM_RC_OK; */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE sim_io_eprintf (sd, "Unknown option (%d)\n", opt); */
/* OBSOLETE return SIM_RC_FAIL; */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE static const OPTION d30v_options[] = */
/* OBSOLETE { */
/* OBSOLETE { {"trace-call", optional_argument, NULL, OPTION_TRACE_CALL}, */
/* OBSOLETE '\0', "on|off", "Enable tracing of calls and returns, checking saved registers", */
/* OBSOLETE d30v_option_handler }, */
/* OBSOLETE { {"trace-trapdump", optional_argument, NULL, OPTION_TRACE_TRAPDUMP}, */
/* OBSOLETE '\0', "on|off", */
/* OBSOLETE #if TRAPDUMP */
/* OBSOLETE "Traps 0..30 dump out all of the registers (defaults on)", */
/* OBSOLETE #else */
/* OBSOLETE "Traps 0..30 dump out all of the registers", */
/* OBSOLETE #endif */
/* OBSOLETE d30v_option_handler }, */
/* OBSOLETE { {"extmem-size", required_argument, NULL, OPTION_EXTMEM_SIZE}, */
/* OBSOLETE '\0', "size", "Change size of external memory, default 8 meg", */
/* OBSOLETE d30v_option_handler }, */
/* OBSOLETE { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL } */
/* OBSOLETE }; */
/* OBSOLETE */
/* OBSOLETE /* Return name of an insn, used by insn profiling. */ */
/* OBSOLETE */
/* OBSOLETE static const char * */
/* OBSOLETE get_insn_name (sim_cpu *cpu, int i) */
/* OBSOLETE { */
/* OBSOLETE return itable[i].name; */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE /* Structures used by the simulator, for gdb just have static structures */ */
/* OBSOLETE */
/* OBSOLETE SIM_DESC */
/* OBSOLETE sim_open (SIM_OPEN_KIND kind, */
/* OBSOLETE host_callback *callback, */
/* OBSOLETE struct _bfd *abfd, */
/* OBSOLETE char **argv) */
/* OBSOLETE { */
/* OBSOLETE SIM_DESC sd = sim_state_alloc (kind, callback); */
/* OBSOLETE */
/* OBSOLETE /* FIXME: watchpoints code shouldn't need this */ */
/* OBSOLETE STATE_WATCHPOINTS (sd)->pc = &(PC); */
/* OBSOLETE STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC); */
/* OBSOLETE STATE_WATCHPOINTS (sd)->interrupt_handler = d30v_interrupt_event; */
/* OBSOLETE */
/* OBSOLETE /* Initialize the mechanism for doing insn profiling. */ */
/* OBSOLETE CPU_INSN_NAME (STATE_CPU (sd, 0)) = get_insn_name; */
/* OBSOLETE CPU_MAX_INSNS (STATE_CPU (sd, 0)) = nr_itable_entries; */
/* OBSOLETE */
/* OBSOLETE #ifdef TRAPDUMP */
/* OBSOLETE TRACE_TRAP_P = TRAPDUMP; */
/* OBSOLETE #endif */
/* OBSOLETE */
/* OBSOLETE if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) */
/* OBSOLETE return 0; */
/* OBSOLETE sim_add_option_table (sd, NULL, d30v_options); */
/* OBSOLETE */
/* OBSOLETE /* Memory and EEPROM */ */
/* OBSOLETE /* internal instruction RAM - fixed */ */
/* OBSOLETE sim_do_commandf (sd, "memory region 0,0x10000"); */
/* OBSOLETE /* internal data RAM - fixed */ */
/* OBSOLETE sim_do_commandf (sd, "memory region 0x20000000,0x8000"); */
/* OBSOLETE /* control register dummy area */ */
/* OBSOLETE sim_do_commandf (sd, "memory region 0x40000000,0x10000"); */
/* OBSOLETE /* external RAM */ */
/* OBSOLETE sim_do_commandf (sd, "memory region 0x80000000,0x%lx", extmem_size); */
/* OBSOLETE /* EIT RAM */ */
/* OBSOLETE sim_do_commandf (sd, "memory region 0xfffff000,0x1000"); */
/* OBSOLETE */
/* OBSOLETE /* getopt will print the error message so we just have to exit if this fails. */
/* OBSOLETE FIXME: Hmmm... in the case of gdb we need getopt to call */
/* OBSOLETE print_filtered. */ */
/* OBSOLETE if (sim_parse_args (sd, argv) != SIM_RC_OK) */
/* OBSOLETE { */
/* OBSOLETE /* Uninstall the modules to avoid memory leaks, */
/* OBSOLETE file descriptor leaks, etc. */ */
/* OBSOLETE sim_module_uninstall (sd); */
/* OBSOLETE return 0; */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE /* check for/establish the a reference program image */ */
/* OBSOLETE if (sim_analyze_program (sd, */
/* OBSOLETE (STATE_PROG_ARGV (sd) != NULL */
/* OBSOLETE ? *STATE_PROG_ARGV (sd) */
/* OBSOLETE : NULL), */
/* OBSOLETE abfd) != SIM_RC_OK) */
/* OBSOLETE { */
/* OBSOLETE sim_module_uninstall (sd); */
/* OBSOLETE return 0; */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE /* establish any remaining configuration options */ */
/* OBSOLETE if (sim_config (sd) != SIM_RC_OK) */
/* OBSOLETE { */
/* OBSOLETE sim_module_uninstall (sd); */
/* OBSOLETE return 0; */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE if (sim_post_argv_init (sd) != SIM_RC_OK) */
/* OBSOLETE { */
/* OBSOLETE /* Uninstall the modules to avoid memory leaks, */
/* OBSOLETE file descriptor leaks, etc. */ */
/* OBSOLETE sim_module_uninstall (sd); */
/* OBSOLETE return 0; */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE return sd; */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE void */
/* OBSOLETE sim_close (SIM_DESC sd, int quitting) */
/* OBSOLETE { */
/* OBSOLETE /* Uninstall the modules to avoid memory leaks, */
/* OBSOLETE file descriptor leaks, etc. */ */
/* OBSOLETE sim_module_uninstall (sd); */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE SIM_RC */
/* OBSOLETE sim_create_inferior (SIM_DESC sd, */
/* OBSOLETE struct _bfd *abfd, */
/* OBSOLETE char **argv, */
/* OBSOLETE char **envp) */
/* OBSOLETE { */
/* OBSOLETE /* clear all registers */ */
/* OBSOLETE memset (&STATE_CPU (sd, 0)->regs, 0, sizeof (STATE_CPU (sd, 0)->regs)); */
/* OBSOLETE EIT_VB = EIT_VB_DEFAULT; */
/* OBSOLETE STATE_CPU (sd, 0)->unit = any_unit; */
/* OBSOLETE sim_module_init (sd); */
/* OBSOLETE if (abfd != NULL) */
/* OBSOLETE PC = bfd_get_start_address (abfd); */
/* OBSOLETE else */
/* OBSOLETE PC = 0xfffff000; /* reset value */ */
/* OBSOLETE return SIM_RC_OK; */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE void */
/* OBSOLETE sim_do_command (SIM_DESC sd, char *cmd) */
/* OBSOLETE { */
/* OBSOLETE if (sim_args_command (sd, cmd) != SIM_RC_OK) */
/* OBSOLETE sim_io_printf (sd, "Unknown command `%s'\n", cmd); */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE /* The following register definitions were ripped off from */
/* OBSOLETE gdb/config/tm-d30v.h. If any of those defs changes, this table needs to */
/* OBSOLETE be updated. */ */
/* OBSOLETE */
/* OBSOLETE #define NUM_REGS 86 */
/* OBSOLETE */
/* OBSOLETE #define R0_REGNUM 0 */
/* OBSOLETE #define FP_REGNUM 11 */
/* OBSOLETE #define LR_REGNUM 62 */
/* OBSOLETE #define SP_REGNUM 63 */
/* OBSOLETE #define SPI_REGNUM 64 /* Interrupt stack pointer */ */
/* OBSOLETE #define SPU_REGNUM 65 /* User stack pointer */ */
/* OBSOLETE #define CREGS_START 66 */
/* OBSOLETE */
/* OBSOLETE #define PSW_REGNUM (CREGS_START + 0) /* psw, bpsw, or dpsw??? */ */
/* OBSOLETE #define PSW_SM 0x80000000 /* Stack mode: 0 == interrupt (SPI), */
/* OBSOLETE 1 == user (SPU) */ */
/* OBSOLETE #define BPSW_REGNUM (CREGS_START + 1) /* Backup PSW (on interrupt) */ */
/* OBSOLETE #define PC_REGNUM (CREGS_START + 2) /* pc, bpc, or dpc??? */ */
/* OBSOLETE #define BPC_REGNUM (CREGS_START + 3) /* Backup PC (on interrupt) */ */
/* OBSOLETE #define DPSW_REGNUM (CREGS_START + 4) /* Backup PSW (on debug trap) */ */
/* OBSOLETE #define DPC_REGNUM (CREGS_START + 5) /* Backup PC (on debug trap) */ */
/* OBSOLETE #define RPT_C_REGNUM (CREGS_START + 7) /* Loop count */ */
/* OBSOLETE #define RPT_S_REGNUM (CREGS_START + 8) /* Loop start address*/ */
/* OBSOLETE #define RPT_E_REGNUM (CREGS_START + 9) /* Loop end address */ */
/* OBSOLETE #define MOD_S_REGNUM (CREGS_START + 10) */
/* OBSOLETE #define MOD_E_REGNUM (CREGS_START + 11) */
/* OBSOLETE #define IBA_REGNUM (CREGS_START + 14) /* Instruction break address */ */
/* OBSOLETE #define EIT_VB_REGNUM (CREGS_START + 15) /* Vector base address */ */
/* OBSOLETE #define INT_S_REGNUM (CREGS_START + 16) /* Interrupt status */ */
/* OBSOLETE #define INT_M_REGNUM (CREGS_START + 17) /* Interrupt mask */ */
/* OBSOLETE #define A0_REGNUM 84 */
/* OBSOLETE #define A1_REGNUM 85 */
/* OBSOLETE */
/* OBSOLETE int */
/* OBSOLETE sim_fetch_register (sd, regno, buf, length) */
/* OBSOLETE SIM_DESC sd; */
/* OBSOLETE int regno; */
/* OBSOLETE unsigned char *buf; */
/* OBSOLETE int length; */
/* OBSOLETE { */
/* OBSOLETE if (regno < A0_REGNUM) */
/* OBSOLETE { */
/* OBSOLETE unsigned32 reg; */
/* OBSOLETE */
/* OBSOLETE if (regno <= R0_REGNUM + 63) */
/* OBSOLETE reg = sd->cpu[0].regs.general_purpose[regno]; */
/* OBSOLETE else if (regno <= SPU_REGNUM) */
/* OBSOLETE reg = sd->cpu[0].regs.sp[regno - SPI_REGNUM]; */
/* OBSOLETE else */
/* OBSOLETE reg = sd->cpu[0].regs.control[regno - CREGS_START]; */
/* OBSOLETE */
/* OBSOLETE buf[0] = reg >> 24; */
/* OBSOLETE buf[1] = reg >> 16; */
/* OBSOLETE buf[2] = reg >> 8; */
/* OBSOLETE buf[3] = reg; */
/* OBSOLETE } */
/* OBSOLETE else if (regno < NUM_REGS) */
/* OBSOLETE { */
/* OBSOLETE unsigned32 reg; */
/* OBSOLETE */
/* OBSOLETE reg = sd->cpu[0].regs.accumulator[regno - A0_REGNUM] >> 32; */
/* OBSOLETE */
/* OBSOLETE buf[0] = reg >> 24; */
/* OBSOLETE buf[1] = reg >> 16; */
/* OBSOLETE buf[2] = reg >> 8; */
/* OBSOLETE buf[3] = reg; */
/* OBSOLETE */
/* OBSOLETE reg = sd->cpu[0].regs.accumulator[regno - A0_REGNUM]; */
/* OBSOLETE */
/* OBSOLETE buf[4] = reg >> 24; */
/* OBSOLETE buf[5] = reg >> 16; */
/* OBSOLETE buf[6] = reg >> 8; */
/* OBSOLETE buf[7] = reg; */
/* OBSOLETE } */
/* OBSOLETE else */
/* OBSOLETE abort (); */
/* OBSOLETE return -1; */
/* OBSOLETE } */
/* OBSOLETE */
/* OBSOLETE int */
/* OBSOLETE sim_store_register (sd, regno, buf, length) */
/* OBSOLETE SIM_DESC sd; */
/* OBSOLETE int regno; */
/* OBSOLETE unsigned char *buf; */
/* OBSOLETE int length; */
/* OBSOLETE { */
/* OBSOLETE if (regno < A0_REGNUM) */
/* OBSOLETE { */
/* OBSOLETE unsigned32 reg; */
/* OBSOLETE */
/* OBSOLETE reg = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; */
/* OBSOLETE */
/* OBSOLETE if (regno <= R0_REGNUM + 63) */
/* OBSOLETE sd->cpu[0].regs.general_purpose[regno] = reg; */
/* OBSOLETE else if (regno <= SPU_REGNUM) */
/* OBSOLETE sd->cpu[0].regs.sp[regno - SPI_REGNUM] = reg; */
/* OBSOLETE else */
/* OBSOLETE sd->cpu[0].regs.control[regno - CREGS_START] = reg; */
/* OBSOLETE } */
/* OBSOLETE else if (regno < NUM_REGS) */
/* OBSOLETE { */
/* OBSOLETE unsigned32 reg; */
/* OBSOLETE */
/* OBSOLETE reg = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; */
/* OBSOLETE */
/* OBSOLETE sd->cpu[0].regs.accumulator[regno - A0_REGNUM] = (unsigned64)reg << 32; */
/* OBSOLETE */
/* OBSOLETE reg = (buf[4] << 24) | (buf[5] << 16) | (buf[6] << 8) | buf[7]; */
/* OBSOLETE */
/* OBSOLETE sd->cpu[0].regs.accumulator[regno - A0_REGNUM] |= reg; */
/* OBSOLETE } */
/* OBSOLETE else */
/* OBSOLETE abort (); */
/* OBSOLETE return -1; */
/* OBSOLETE } */

164
sim/d30v/sim-main.h
View File

@ -1,82 +1,82 @@
/* This file is part of the program psim.
Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
Copyright (C) 1997, 1998, Free Software Foundation
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _SIM_MAIN_H_
#define _SIM_MAIN_H_
/* This simulator suports watchpoints */
#define WITH_WATCHPOINTS 1
#include "sim-basics.h"
#include "sim-signal.h"
/* needed */
typedef address_word sim_cia;
#define INVALID_INSTRUCTION_ADDRESS ((address_word) 0 - 1)
/* This simulator doesn't cache anything so no saving of context is
needed during either of a halt or restart */
#define SIM_ENGINE_HALT_HOOK(SD,CPU,CIA) while (0)
#define SIM_ENGINE_RESTART_HOOK(SD,CPU,CIA) while (0)
#include "sim-base.h"
/* These are generated files. */
#include "itable.h"
#include "s_idecode.h"
#include "l_idecode.h"
#include "cpu.h"
#include "alu.h"
struct sim_state {
sim_event *pending_interrupt;
/* the processors proper */
sim_cpu cpu[MAX_NR_PROCESSORS];
#if (WITH_SMP)
#define STATE_CPU(sd, n) (&(sd)->cpu[n])
#else
#define STATE_CPU(sd, n) (&(sd)->cpu[0])
#endif
/* The base class. */
sim_state_base base;
};
/* deliver an interrupt */
sim_event_handler d30v_interrupt_event;
#ifdef HAVE_STRING_H
#include <string.h>
#else
#ifdef HAVE_STRINGS_H
#include <strings.h>
#endif
#endif
#endif /* _SIM_MAIN_H_ */
/* OBSOLETE /* This file is part of the program psim. */
/* OBSOLETE */
/* OBSOLETE Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au> */
/* OBSOLETE Copyright (C) 1997, 1998, Free Software Foundation */
/* OBSOLETE */
/* OBSOLETE This program is free software; you can redistribute it and/or modify */
/* OBSOLETE it under the terms of the GNU General Public License as published by */
/* OBSOLETE the Free Software Foundation; either version 2 of the License, or */
/* OBSOLETE (at your option) any later version. */
/* OBSOLETE */
/* OBSOLETE This program is distributed in the hope that it will be useful, */
/* OBSOLETE but WITHOUT ANY WARRANTY; without even the implied warranty of */
/* OBSOLETE MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
/* OBSOLETE GNU General Public License for more details. */
/* OBSOLETE */
/* OBSOLETE You should have received a copy of the GNU General Public License */
/* OBSOLETE along with this program; if not, write to the Free Software */
/* OBSOLETE Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
/* OBSOLETE */
/* OBSOLETE */ */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE #ifndef _SIM_MAIN_H_ */
/* OBSOLETE #define _SIM_MAIN_H_ */
/* OBSOLETE */
/* OBSOLETE /* This simulator suports watchpoints */ */
/* OBSOLETE #define WITH_WATCHPOINTS 1 */
/* OBSOLETE */
/* OBSOLETE #include "sim-basics.h" */
/* OBSOLETE #include "sim-signal.h" */
/* OBSOLETE */
/* OBSOLETE /* needed */ */
/* OBSOLETE typedef address_word sim_cia; */
/* OBSOLETE #define INVALID_INSTRUCTION_ADDRESS ((address_word) 0 - 1) */
/* OBSOLETE */
/* OBSOLETE /* This simulator doesn't cache anything so no saving of context is */
/* OBSOLETE needed during either of a halt or restart */ */
/* OBSOLETE #define SIM_ENGINE_HALT_HOOK(SD,CPU,CIA) while (0) */
/* OBSOLETE #define SIM_ENGINE_RESTART_HOOK(SD,CPU,CIA) while (0) */
/* OBSOLETE */
/* OBSOLETE #include "sim-base.h" */
/* OBSOLETE */
/* OBSOLETE /* These are generated files. */ */
/* OBSOLETE #include "itable.h" */
/* OBSOLETE #include "s_idecode.h" */
/* OBSOLETE #include "l_idecode.h" */
/* OBSOLETE */
/* OBSOLETE #include "cpu.h" */
/* OBSOLETE #include "alu.h" */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE struct sim_state { */
/* OBSOLETE */
/* OBSOLETE sim_event *pending_interrupt; */
/* OBSOLETE */
/* OBSOLETE /* the processors proper */ */
/* OBSOLETE sim_cpu cpu[MAX_NR_PROCESSORS]; */
/* OBSOLETE #if (WITH_SMP) */
/* OBSOLETE #define STATE_CPU(sd, n) (&(sd)->cpu[n]) */
/* OBSOLETE #else */
/* OBSOLETE #define STATE_CPU(sd, n) (&(sd)->cpu[0]) */
/* OBSOLETE #endif */
/* OBSOLETE */
/* OBSOLETE /* The base class. */ */
/* OBSOLETE sim_state_base base; */
/* OBSOLETE */
/* OBSOLETE }; */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE /* deliver an interrupt */ */
/* OBSOLETE sim_event_handler d30v_interrupt_event; */
/* OBSOLETE */
/* OBSOLETE */
/* OBSOLETE #ifdef HAVE_STRING_H */
/* OBSOLETE #include <string.h> */
/* OBSOLETE #else */
/* OBSOLETE #ifdef HAVE_STRINGS_H */
/* OBSOLETE #include <strings.h> */
/* OBSOLETE #endif */
/* OBSOLETE #endif */
/* OBSOLETE */
/* OBSOLETE #endif /* _SIM_MAIN_H_ */ */