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RISC-V: Don't generate the ELF privilege attributes when no CSR are used. 

gas/
	* config/tc-riscv.c (explicit_csr): New static boolean.
	Used to indicate CSR are explictly used.
	(riscv_ip): Set explicit_csr to TRUE if any CSR is used.
	(riscv_write_out_attrs): If we already have set elf priv
	attributes, then generate them.  Otherwise, don't generate
	them when no CSR are used.

	* testsuite/gas/riscv/attribute-01.d: Remove the priv attributes.
	* testsuite/gas/riscv/attribute-02.d: Likewise.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-04.d: Likewise.
	* testsuite/gas/riscv/attribute-05.d: Likewise.
	* testsuite/gas/riscv/attribute-06.d: Likewise.
	* testsuite/gas/riscv/attribute-07.d: Likewise.
	* testsuite/gas/riscv/attribute-08.d: Likewise.
	* testsuite/gas/riscv/attribute-09.d: Likewise.
	* testsuite/gas/riscv/attribute-10.d: Likewise.
	* testsuite/gas/riscv/attribute-unknown.d: Likewise.
	* testsuite/gas/riscv/attribute-11.s: New testcase.
	* testsuite/gas/riscv/attribute-11.d: New testcase.  The CSR is
	used, so we should output the ELF priv attributes.
	* testsuite/gas/riscv/attribute-12.d: New testcase.  The CSR is
	used, so output the priv attributes according to the -mpriv-spec.
	* testsuite/gas/riscv/attribute-13.d: New testcase.  The CSR isn't
	used, so ignore the -mpriv-spec setting.

	ld/
	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.
	* testsuite/ld-riscv-elf/call-relax.d: Add -mno-arch-attr.
This commit is contained in:
Nelson Chu 2020-05-29 15:31:46 +08:00
parent a975c88e65
commit 3fc6c3dc2a
27 changed files with 75 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
gas/ChangeLog
View File

@ -1,3 +1,30 @@
2020-06-05 Nelson Chu <nelson.chu@sifive.com>
* config/tc-riscv.c (explicit_csr): New static boolean.
Used to indicate CSR are explictly used.
(riscv_ip): Set explicit_csr to TRUE if any CSR is used.
(riscv_write_out_attrs): If we already have set elf priv
attributes, then generate them. Otherwise, don't generate
them when no CSR are used.
* testsuite/gas/riscv/attribute-01.d: Remove the priv attributes.
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* testsuite/gas/riscv/attribute-08.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: Likewise.
* testsuite/gas/riscv/attribute-10.d: Likewise.
* testsuite/gas/riscv/attribute-unknown.d: Likewise.
* testsuite/gas/riscv/attribute-11.s: New testcase.
* testsuite/gas/riscv/attribute-11.d: New testcase. The CSR is
used, so we should output the ELF priv attributes.
* testsuite/gas/riscv/attribute-12.d: New testcase. The CSR is
used, so output the priv attributes according to the -mpriv-spec.
* testsuite/gas/riscv/attribute-13.d: New testcase. The CSR isn't
used, so ignore the -mpriv-spec setting.
2020-06-04 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-ip2k. (ip2k_apply_fix): Pass endianness to

9
gas/config/tc-riscv.c
View File

@ -374,6 +374,9 @@ static bfd_boolean start_assemble = FALSE;
/* Indicate ELF attributes are explictly set. */
static bfd_boolean explicit_attr = FALSE;
/* Indicate CSR are explictly used. */
static bfd_boolean explicit_csr = FALSE;
/* Macros for encoding relaxation state for RVC branches and far jumps. */
#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
((relax_substateT) \
@ -2212,6 +2215,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
case 'E': /* Control register. */
insn_with_csr = TRUE;
explicit_csr = TRUE;
if (reg_lookup (&s, RCLASS_CSR, &regno))
INSERT_OPERAND (CSR, *ip, regno);
else
@ -3605,6 +3609,11 @@ riscv_write_out_attrs (void)
&& !riscv_set_default_priv_spec (NULL))
return;
/* If we already have set elf priv attributes, then generate them.
Otherwise, don't generate them when no CSR are used. */
if (!explicit_csr)
return;
/* Re-write priv attributes by default_priv_spec. */
priv_str = riscv_get_priv_spec_name (default_priv_spec);
p = priv_str;

3
gas/testsuite/gas/riscv/attribute-01.d
View File

@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0"
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

3
gas/testsuite/gas/riscv/attribute-02.d
View File

@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle0p0"
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

3
gas/testsuite/gas/riscv/attribute-03.d
View File

@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle0p0_xfoo0p0"
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

3
gas/testsuite/gas/riscv/attribute-04.d
View File

@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0"
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

3
gas/testsuite/gas/riscv/attribute-06.d
View File

@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0"
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

3
gas/testsuite/gas/riscv/attribute-07.d
View File

@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv64i2p0"
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

3
gas/testsuite/gas/riscv/attribute-08.d
View File

@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32e1p9"
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

3
gas/testsuite/gas/riscv/attribute-09.d
View File

@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p1_m2p0_zicsr0p0"
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

3
gas/testsuite/gas/riscv/attribute-10.d
View File

@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0"
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

8
gas/testsuite/gas/riscv/attribute-11.d Normal file
View File

@ -0,0 +1,8 @@
#as: -march-attr
#readelf: -A
#source: attribute-11.s
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_priv_spec: [0-9_\"].*
#...

1
gas/testsuite/gas/riscv/attribute-11.s Normal file
View File

@ -0,0 +1 @@
csrr a0, 0x0

9
gas/testsuite/gas/riscv/attribute-12.d Normal file
View File

@ -0,0 +1,9 @@
#as: -march-attr -mpriv-spec=1.9.1
#readelf: -A
#source: attribute-11.s
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_priv_spec: 1
Tag_RISCV_priv_spec_minor: 9
Tag_RISCV_priv_spec_revision: 1

6
gas/testsuite/gas/riscv/attribute-13.d Normal file
View File

@ -0,0 +1,6 @@
#as: -march-attr -mpriv-spec=1.9.1
#readelf: -A
#source: empty.s
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*

3
gas/testsuite/gas/riscv/attribute-unknown.d
View File

@ -4,8 +4,5 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...
Tag_unknown_255: "test"
Tag_unknown_256: 123 \(0x7b\)

14
ld/ChangeLog
View File

@ -1,3 +1,17 @@
2020-06-05 Nelson Chu <nelson.chu@sifive.com>
* testsuite/ld-riscv-elf/attr-merge-arch-01.d: The CSR isn't used,
so ignore the -mpriv-spec setting.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.
* testsuite/ld-riscv-elf/call-relax.d: Add -mno-arch-attr.
2020-06-04 H.J. Lu <hongjiu.lu@intel.com>
PR ld/26080

3
ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
View File

@ -7,6 +7,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0"
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

3
ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
View File

@ -7,6 +7,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0"
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

3
ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
View File

@ -7,6 +7,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_xbar2p0_xfoo2p0"
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

2
ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d
View File

@ -8,6 +8,4 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_stack_align: 16-bytes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

3
ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d
View File

@ -8,6 +8,3 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_unaligned_access: Unaligned access
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

3
ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d
View File

@ -8,6 +8,3 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_unaligned_access: Unaligned access
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

3
ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d
View File

@ -8,6 +8,3 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_unaligned_access: Unaligned access
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

3
ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d
View File

@ -7,6 +7,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

3
ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d
View File

@ -8,6 +8,3 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_unaligned_access: Unaligned access
Tag_RISCV_priv_spec: [0-9_\"].*
Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...

2
ld/testsuite/ld-riscv-elf/call-relax.d
View File

@ -3,7 +3,7 @@
#source: call-relax-1.s
#source: call-relax-2.s
#source: call-relax-3.s
#as: -march=rv32ic
#as: -march=rv32ic -mno-arch-attr
#ld: -melf32lriscv
#objdump: -d
#pass