2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
This commit is contained in:
Chris Demetriou
parent
a6befae84d
commit
402586aa26
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@ -1,3 +1,20 @@
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2002-05-01 Chris Demetriou <cgd@broadcom.com>
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* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
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which wouldn't compile anyway.
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* sim-main.h (unpredictable_action): New function prototype.
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(Unpredictable): Define to call igen function unpredictable().
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(NotWordValue): New macro to call igen function not_word_value().
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(UndefinedResult): Remove.
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* interp.c (undefined_result): Remove.
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(unpredictable_action): New function.
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* mips.igen (not_word_value, unpredictable): New functions.
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(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
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(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
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(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
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NotWordValue() to check for unpredictable inputs, then
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Unpredictable() to handle them.
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2002-02-24 Chris Demetriou <cgd@broadcom.com>
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* mips.igen: Fix formatting of calls to Unpredictable().
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@ -279,10 +279,6 @@ store_fpr (SIM_DESC sd,
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break;
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}
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}
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#if defined(WARN_RESULT)
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else
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UndefinedResult ();
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#endif /* WARN_RESULT */
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if (err)
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SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR ()");
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@ -1869,28 +1869,31 @@ signal_exception (SIM_DESC sd,
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#if defined(WARN_RESULT)
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/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
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/* This function indicates that the result of the operation is
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undefined. However, this should not affect the instruction
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stream. All that is meant to happen is that the destination
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register is set to an undefined result. To keep the simulator
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simple, we just don't bother updating the destination register, so
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the overall result will be undefined. If desired we can stop the
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simulator by raising a pseudo-exception. */
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#define UndefinedResult() undefined_result (sd,cia)
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static void
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undefined_result(sd,cia)
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SIM_DESC sd;
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address_word cia;
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/* This function implements what the MIPS32 and MIPS64 ISAs define as
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"UNPREDICTABLE" behaviour.
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About UNPREDICTABLE behaviour they say: "UNPREDICTABLE results
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may vary from processor implementation to processor implementation,
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instruction to instruction, or as a function of time on the same
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implementation or instruction. Software can never depend on results
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that are UNPREDICTABLE. ..." (MIPS64 Architecture for Programmers
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Volume II, The MIPS64 Instruction Set. MIPS Document MD00087 revision
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0.95, page 2.)
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For UNPREDICTABLE behaviour, we print a message, if possible print
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the offending instructions mips.igen instruction name (provided by
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the caller), and stop the simulator.
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XXX FIXME: eventually, stopping the simulator should be made conditional
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on a command-line option. */
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void
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unpredictable_action(sim_cpu *cpu, address_word cia)
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{
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sim_io_eprintf(sd,"UndefinedResult: PC = 0x%s\n",pr_addr(cia));
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#if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
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state |= simSTOP;
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#endif
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return;
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SIM_DESC sd = CPU_STATE(cpu);
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sim_io_eprintf(sd, "UNPREDICTABLE: PC = 0x%s\n", pr_addr (cia));
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sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGABRT);
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}
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#endif /* WARN_RESULT */
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/*-- co-processor support routines ------------------------------------------*/
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@ -142,6 +142,70 @@
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}
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// Helper:
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//
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// Check that a 32-bit register value is properly sign-extended.
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// (See NotWordValue in ISA spec.)
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//
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:function:::int:not_word_value:unsigned_word value
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*mipsI:
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*mipsII:
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*mipsIII:
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*mipsIV:
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*mipsV:
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*vr4100:
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*vr5000:
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*r3900:
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{
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/* For historical simulator compatibility (until documentation is
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found that makes these operations unpredictable on some of these
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architectures), this check never returns true. */
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return 0;
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}
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:function:::int:not_word_value:unsigned_word value
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*mips32:
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{
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/* On MIPS32, since registers are 32-bits, there's no check to be done. */
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return 0;
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}
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:function:::int:not_word_value:unsigned_word value
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*mips64:
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{
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return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0));
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}
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// Helper:
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//
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// Handle UNPREDICTABLE operation behaviour. The goal here is to prevent
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// theoretically portable code which invokes non-portable behaviour from
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// running with no indication of the portability issue.
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// (See definition of UNPREDICTABLE in ISA spec.)
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//
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:function:::void:unpredictable:
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*mipsI:
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*mipsII:
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*mipsIII:
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*mipsIV:
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*mipsV:
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*vr4100:
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*vr5000:
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*r3900:
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{
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}
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:function:::void:unpredictable:
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*mips32:
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*mips64:
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{
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unpredictable_action (CPU, CIA);
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}
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// Helper:
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//
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// Check that an access to a HI/LO register meets timing requirements
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@ -340,6 +404,8 @@
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*vr5000:
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*r3900:
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{
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if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
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Unpredictable ();
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TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
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{
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ALU32_BEGIN (GPR[RS]);
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@ -364,6 +430,8 @@
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*vr5000:
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*r3900:
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{
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if (NotWordValue (GPR[RS]))
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Unpredictable ();
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TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
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{
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ALU32_BEGIN (GPR[RS]);
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@ -377,6 +445,8 @@
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:function:::void:do_addiu:int rs, int rt, unsigned16 immediate
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{
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if (NotWordValue (GPR[rs]))
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Unpredictable ();
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TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
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GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
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TRACE_ALU_RESULT (GPR[rt]);
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@ -402,6 +472,8 @@
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:function:::void:do_addu:int rs, int rt, int rd
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{
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if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
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Unpredictable ();
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TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
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GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
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TRACE_ALU_RESULT (GPR[rd]);
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@ -558,6 +630,8 @@
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{
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address_word offset = EXTEND16 (OFFSET) << 2;
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check_branch_bug ();
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if (RS == 31)
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Unpredictable ();
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RA = (CIA + 8);
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if ((signed_word) GPR[RS] >= 0)
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{
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@ -582,6 +656,8 @@
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{
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address_word offset = EXTEND16 (OFFSET) << 2;
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check_branch_bug ();
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if (RS == 31)
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Unpredictable ();
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RA = (CIA + 8);
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/* NOTE: The branch occurs AFTER the next instruction has been
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executed */
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@ -762,6 +838,8 @@
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{
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address_word offset = EXTEND16 (OFFSET) << 2;
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check_branch_bug ();
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if (RS == 31)
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Unpredictable ();
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RA = (CIA + 8);
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/* NOTE: The branch occurs AFTER the next instruction has been
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executed */
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@ -788,6 +866,8 @@
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{
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address_word offset = EXTEND16 (OFFSET) << 2;
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check_branch_bug ();
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if (RS == 31)
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Unpredictable ();
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RA = (CIA + 8);
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if ((signed_word) GPR[RS] < 0)
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{
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@ -926,6 +1006,8 @@
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unsigned32 i, mask;
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if (RT != RD)
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Unpredictable ();
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if (NotWordValue (GPR[RS]))
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Unpredictable ();
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TRACE_ALU_INPUT1 (GPR[RS]);
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for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
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{
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@ -948,6 +1030,8 @@
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unsigned32 i, mask;
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if (RT != RD)
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Unpredictable ();
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if (NotWordValue (GPR[RS]))
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Unpredictable ();
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TRACE_ALU_INPUT1 (GPR[RS]);
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for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
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{
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@ -2099,6 +2183,8 @@
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{
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signed64 temp;
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check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
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if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
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Unpredictable ();
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TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
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temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
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+ ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
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@ -2116,6 +2202,8 @@
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{
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unsigned64 temp;
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check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
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if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
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Unpredictable ();
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TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
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temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
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+ ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
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@ -2212,6 +2300,8 @@
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{
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signed64 temp;
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check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
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if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
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Unpredictable ();
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TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
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temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
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- ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
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@ -2229,6 +2319,8 @@
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{
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unsigned64 temp;
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check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
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if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
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Unpredictable ();
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TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
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temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
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- ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
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@ -2283,6 +2375,8 @@
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*mips64:
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{
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signed64 prod;
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if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
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Unpredictable ();
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TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
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prod = (((signed64)(signed32) GPR[RS])
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* ((signed64)(signed32) GPR[RT]));
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@ -2296,6 +2390,8 @@
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{
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signed64 prod;
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check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
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if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
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Unpredictable ();
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TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
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prod = (((signed64)(signed32) GPR[rs])
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* ((signed64)(signed32) GPR[rt]));
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@ -2335,6 +2431,8 @@
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{
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unsigned64 prod;
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check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
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if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
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Unpredictable ();
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TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
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prod = (((unsigned64)(unsigned32) GPR[rs])
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* ((unsigned64)(unsigned32) GPR[rt]));
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@ -2893,6 +2991,8 @@
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:function:::void:do_sra:int rt, int rd, int shift
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{
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signed32 temp = (signed32) GPR[rt] >> shift;
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if (NotWordValue (GPR[rt]))
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Unpredictable ();
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TRACE_ALU_INPUT2 (GPR[rt], shift);
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GPR[rd] = EXTEND32 (temp);
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TRACE_ALU_RESULT (GPR[rd]);
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@ -2920,6 +3020,8 @@
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{
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int s = MASKED (GPR[rs], 4, 0);
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signed32 temp = (signed32) GPR[rt] >> s;
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if (NotWordValue (GPR[rt]))
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Unpredictable ();
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TRACE_ALU_INPUT2 (GPR[rt], s);
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GPR[rd] = EXTEND32 (temp);
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TRACE_ALU_RESULT (GPR[rd]);
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@ -2946,6 +3048,8 @@
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:function:::void:do_srl:int rt, int rd, int shift
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{
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unsigned32 temp = (unsigned32) GPR[rt] >> shift;
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if (NotWordValue (GPR[rt]))
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Unpredictable ();
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TRACE_ALU_INPUT2 (GPR[rt], shift);
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GPR[rd] = EXTEND32 (temp);
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TRACE_ALU_RESULT (GPR[rd]);
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@ -2972,6 +3076,8 @@
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{
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int s = MASKED (GPR[rs], 4, 0);
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unsigned32 temp = (unsigned32) GPR[rt] >> s;
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if (NotWordValue (GPR[rt]))
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Unpredictable ();
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TRACE_ALU_INPUT2 (GPR[rt], s);
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GPR[rd] = EXTEND32 (temp);
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TRACE_ALU_RESULT (GPR[rd]);
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@ -3007,6 +3113,8 @@
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*vr5000:
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*r3900:
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{
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if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
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Unpredictable ();
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TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
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{
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ALU32_BEGIN (GPR[RS]);
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@ -3019,6 +3127,8 @@
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:function:::void:do_subu:int rs, int rt, int rd
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{
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if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
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Unpredictable ();
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TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
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GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
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TRACE_ALU_RESULT (GPR[rd]);
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@ -771,8 +771,9 @@ INLINE_SIM_MAIN (void) prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word
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#define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
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prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
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#define UndefinedResult()
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#define Unpredictable()
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void unpredictable_action (sim_cpu *cpu, address_word cia);
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#define NotWordValue(val) not_word_value (SD_, (val))
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#define Unpredictable() unpredictable (SD_)
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INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
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#define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
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